1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 #include <linux/soc/mediatek/mtk-cmdq.h> 9 #include <linux/soc/mediatek/mtk-mmsys.h> 10 #include <linux/soc/mediatek/mtk-mutex.h> 11 12 #include <asm/barrier.h> 13 #include <soc/mediatek/smi.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_plane_helper.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_vblank.h> 20 21 #include "mtk_drm_drv.h" 22 #include "mtk_drm_crtc.h" 23 #include "mtk_drm_ddp_comp.h" 24 #include "mtk_drm_gem.h" 25 #include "mtk_drm_plane.h" 26 27 /* 28 * struct mtk_drm_crtc - MediaTek specific crtc structure. 29 * @base: crtc object. 30 * @enabled: records whether crtc_enable succeeded 31 * @planes: array of 4 drm_plane structures, one for each overlay plane 32 * @pending_planes: whether any plane has pending changes to be applied 33 * @mmsys_dev: pointer to the mmsys device for configuration registers 34 * @mutex: handle to one of the ten disp_mutex streams 35 * @ddp_comp_nr: number of components in ddp_comp 36 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 37 * 38 * TODO: Needs update: this header is missing a bunch of member descriptions. 39 */ 40 struct mtk_drm_crtc { 41 struct drm_crtc base; 42 bool enabled; 43 44 bool pending_needs_vblank; 45 struct drm_pending_vblank_event *event; 46 47 struct drm_plane *planes; 48 unsigned int layer_nr; 49 bool pending_planes; 50 bool pending_async_planes; 51 52 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 53 struct cmdq_client *cmdq_client; 54 u32 cmdq_event; 55 #endif 56 57 struct device *mmsys_dev; 58 struct mtk_mutex *mutex; 59 unsigned int ddp_comp_nr; 60 struct mtk_ddp_comp **ddp_comp; 61 62 /* lock for display hardware access */ 63 struct mutex hw_lock; 64 bool config_updating; 65 }; 66 67 struct mtk_crtc_state { 68 struct drm_crtc_state base; 69 70 bool pending_config; 71 unsigned int pending_width; 72 unsigned int pending_height; 73 unsigned int pending_vrefresh; 74 }; 75 76 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 77 { 78 return container_of(c, struct mtk_drm_crtc, base); 79 } 80 81 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 82 { 83 return container_of(s, struct mtk_crtc_state, base); 84 } 85 86 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 87 { 88 struct drm_crtc *crtc = &mtk_crtc->base; 89 unsigned long flags; 90 91 spin_lock_irqsave(&crtc->dev->event_lock, flags); 92 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 93 drm_crtc_vblank_put(crtc); 94 mtk_crtc->event = NULL; 95 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 96 } 97 98 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 99 { 100 drm_crtc_handle_vblank(&mtk_crtc->base); 101 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) { 102 mtk_drm_crtc_finish_page_flip(mtk_crtc); 103 mtk_crtc->pending_needs_vblank = false; 104 } 105 } 106 107 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 108 { 109 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 110 111 mtk_mutex_put(mtk_crtc->mutex); 112 113 drm_crtc_cleanup(crtc); 114 } 115 116 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 117 { 118 struct mtk_crtc_state *state; 119 120 if (crtc->state) 121 __drm_atomic_helper_crtc_destroy_state(crtc->state); 122 123 kfree(to_mtk_crtc_state(crtc->state)); 124 crtc->state = NULL; 125 126 state = kzalloc(sizeof(*state), GFP_KERNEL); 127 if (state) 128 __drm_atomic_helper_crtc_reset(crtc, &state->base); 129 } 130 131 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 132 { 133 struct mtk_crtc_state *state; 134 135 state = kzalloc(sizeof(*state), GFP_KERNEL); 136 if (!state) 137 return NULL; 138 139 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 140 141 WARN_ON(state->base.crtc != crtc); 142 state->base.crtc = crtc; 143 144 return &state->base; 145 } 146 147 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 148 struct drm_crtc_state *state) 149 { 150 __drm_atomic_helper_crtc_destroy_state(state); 151 kfree(to_mtk_crtc_state(state)); 152 } 153 154 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 155 const struct drm_display_mode *mode, 156 struct drm_display_mode *adjusted_mode) 157 { 158 /* Nothing to do here, but this callback is mandatory. */ 159 return true; 160 } 161 162 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 163 { 164 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 165 166 state->pending_width = crtc->mode.hdisplay; 167 state->pending_height = crtc->mode.vdisplay; 168 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 169 wmb(); /* Make sure the above parameters are set before update */ 170 state->pending_config = true; 171 } 172 173 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 174 { 175 int ret; 176 int i; 177 178 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 179 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 180 if (ret) { 181 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 182 goto err; 183 } 184 } 185 186 return 0; 187 err: 188 while (--i >= 0) 189 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 190 return ret; 191 } 192 193 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 194 { 195 int i; 196 197 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 198 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 199 } 200 201 static 202 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 203 struct drm_plane *plane, 204 unsigned int *local_layer) 205 { 206 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 207 struct mtk_ddp_comp *comp; 208 int i, count = 0; 209 unsigned int local_index = plane - mtk_crtc->planes; 210 211 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 212 comp = mtk_crtc->ddp_comp[i]; 213 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 214 *local_layer = local_index - count; 215 return comp; 216 } 217 count += mtk_ddp_comp_layer_nr(comp); 218 } 219 220 WARN(1, "Failed to find component for plane %d\n", plane->index); 221 return NULL; 222 } 223 224 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 225 static void ddp_cmdq_cb(struct cmdq_cb_data data) 226 { 227 cmdq_pkt_destroy(data.data); 228 } 229 #endif 230 231 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 232 { 233 struct drm_crtc *crtc = &mtk_crtc->base; 234 struct drm_connector *connector; 235 struct drm_encoder *encoder; 236 struct drm_connector_list_iter conn_iter; 237 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 238 int ret; 239 int i; 240 241 if (WARN_ON(!crtc->state)) 242 return -EINVAL; 243 244 width = crtc->state->adjusted_mode.hdisplay; 245 height = crtc->state->adjusted_mode.vdisplay; 246 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 247 248 drm_for_each_encoder(encoder, crtc->dev) { 249 if (encoder->crtc != crtc) 250 continue; 251 252 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 253 drm_for_each_connector_iter(connector, &conn_iter) { 254 if (connector->encoder != encoder) 255 continue; 256 if (connector->display_info.bpc != 0 && 257 bpc > connector->display_info.bpc) 258 bpc = connector->display_info.bpc; 259 } 260 drm_connector_list_iter_end(&conn_iter); 261 } 262 263 ret = pm_runtime_resume_and_get(crtc->dev->dev); 264 if (ret < 0) { 265 DRM_ERROR("Failed to enable power domain: %d\n", ret); 266 return ret; 267 } 268 269 ret = mtk_mutex_prepare(mtk_crtc->mutex); 270 if (ret < 0) { 271 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 272 goto err_pm_runtime_put; 273 } 274 275 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 276 if (ret < 0) { 277 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 278 goto err_mutex_unprepare; 279 } 280 281 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 282 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 283 mtk_crtc->ddp_comp[i]->id, 284 mtk_crtc->ddp_comp[i + 1]->id); 285 mtk_mutex_add_comp(mtk_crtc->mutex, 286 mtk_crtc->ddp_comp[i]->id); 287 } 288 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 289 mtk_mutex_enable(mtk_crtc->mutex); 290 291 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 292 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 293 294 if (i == 1) 295 mtk_ddp_comp_bgclr_in_on(comp); 296 297 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 298 mtk_ddp_comp_start(comp); 299 } 300 301 /* Initially configure all planes */ 302 for (i = 0; i < mtk_crtc->layer_nr; i++) { 303 struct drm_plane *plane = &mtk_crtc->planes[i]; 304 struct mtk_plane_state *plane_state; 305 struct mtk_ddp_comp *comp; 306 unsigned int local_layer; 307 308 plane_state = to_mtk_plane_state(plane->state); 309 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 310 if (comp) 311 mtk_ddp_comp_layer_config(comp, local_layer, 312 plane_state, NULL); 313 } 314 315 return 0; 316 317 err_mutex_unprepare: 318 mtk_mutex_unprepare(mtk_crtc->mutex); 319 err_pm_runtime_put: 320 pm_runtime_put(crtc->dev->dev); 321 return ret; 322 } 323 324 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 325 { 326 struct drm_device *drm = mtk_crtc->base.dev; 327 struct drm_crtc *crtc = &mtk_crtc->base; 328 int i; 329 330 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 331 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 332 if (i == 1) 333 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 334 } 335 336 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 337 mtk_mutex_remove_comp(mtk_crtc->mutex, 338 mtk_crtc->ddp_comp[i]->id); 339 mtk_mutex_disable(mtk_crtc->mutex); 340 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 341 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 342 mtk_crtc->ddp_comp[i]->id, 343 mtk_crtc->ddp_comp[i + 1]->id); 344 mtk_mutex_remove_comp(mtk_crtc->mutex, 345 mtk_crtc->ddp_comp[i]->id); 346 } 347 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 348 mtk_crtc_ddp_clk_disable(mtk_crtc); 349 mtk_mutex_unprepare(mtk_crtc->mutex); 350 351 pm_runtime_put(drm->dev); 352 353 if (crtc->state->event && !crtc->state->active) { 354 spin_lock_irq(&crtc->dev->event_lock); 355 drm_crtc_send_vblank_event(crtc, crtc->state->event); 356 crtc->state->event = NULL; 357 spin_unlock_irq(&crtc->dev->event_lock); 358 } 359 } 360 361 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 362 struct cmdq_pkt *cmdq_handle) 363 { 364 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 365 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 366 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 367 unsigned int i; 368 unsigned int local_layer; 369 370 /* 371 * TODO: instead of updating the registers here, we should prepare 372 * working registers in atomic_commit and let the hardware command 373 * queue update module registers on vblank. 374 */ 375 if (state->pending_config) { 376 mtk_ddp_comp_config(comp, state->pending_width, 377 state->pending_height, 378 state->pending_vrefresh, 0, 379 cmdq_handle); 380 381 state->pending_config = false; 382 } 383 384 if (mtk_crtc->pending_planes) { 385 for (i = 0; i < mtk_crtc->layer_nr; i++) { 386 struct drm_plane *plane = &mtk_crtc->planes[i]; 387 struct mtk_plane_state *plane_state; 388 389 plane_state = to_mtk_plane_state(plane->state); 390 391 if (!plane_state->pending.config) 392 continue; 393 394 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 395 &local_layer); 396 397 if (comp) 398 mtk_ddp_comp_layer_config(comp, local_layer, 399 plane_state, 400 cmdq_handle); 401 plane_state->pending.config = false; 402 } 403 mtk_crtc->pending_planes = false; 404 } 405 406 if (mtk_crtc->pending_async_planes) { 407 for (i = 0; i < mtk_crtc->layer_nr; i++) { 408 struct drm_plane *plane = &mtk_crtc->planes[i]; 409 struct mtk_plane_state *plane_state; 410 411 plane_state = to_mtk_plane_state(plane->state); 412 413 if (!plane_state->pending.async_config) 414 continue; 415 416 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 417 &local_layer); 418 419 if (comp) 420 mtk_ddp_comp_layer_config(comp, local_layer, 421 plane_state, 422 cmdq_handle); 423 plane_state->pending.async_config = false; 424 } 425 mtk_crtc->pending_async_planes = false; 426 } 427 } 428 429 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 430 bool needs_vblank) 431 { 432 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 433 struct cmdq_pkt *cmdq_handle; 434 #endif 435 struct drm_crtc *crtc = &mtk_crtc->base; 436 struct mtk_drm_private *priv = crtc->dev->dev_private; 437 unsigned int pending_planes = 0, pending_async_planes = 0; 438 int i; 439 440 mutex_lock(&mtk_crtc->hw_lock); 441 mtk_crtc->config_updating = true; 442 if (needs_vblank) 443 mtk_crtc->pending_needs_vblank = true; 444 445 for (i = 0; i < mtk_crtc->layer_nr; i++) { 446 struct drm_plane *plane = &mtk_crtc->planes[i]; 447 struct mtk_plane_state *plane_state; 448 449 plane_state = to_mtk_plane_state(plane->state); 450 if (plane_state->pending.dirty) { 451 plane_state->pending.config = true; 452 plane_state->pending.dirty = false; 453 pending_planes |= BIT(i); 454 } else if (plane_state->pending.async_dirty) { 455 plane_state->pending.async_config = true; 456 plane_state->pending.async_dirty = false; 457 pending_async_planes |= BIT(i); 458 } 459 } 460 if (pending_planes) 461 mtk_crtc->pending_planes = true; 462 if (pending_async_planes) 463 mtk_crtc->pending_async_planes = true; 464 465 if (priv->data->shadow_register) { 466 mtk_mutex_acquire(mtk_crtc->mutex); 467 mtk_crtc_ddp_config(crtc, NULL); 468 mtk_mutex_release(mtk_crtc->mutex); 469 } 470 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 471 if (mtk_crtc->cmdq_client) { 472 mbox_flush(mtk_crtc->cmdq_client->chan, 2000); 473 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 474 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 475 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 476 mtk_crtc_ddp_config(crtc, cmdq_handle); 477 cmdq_pkt_finalize(cmdq_handle); 478 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 479 } 480 #endif 481 mtk_crtc->config_updating = false; 482 mutex_unlock(&mtk_crtc->hw_lock); 483 } 484 485 static void mtk_crtc_ddp_irq(void *data) 486 { 487 struct drm_crtc *crtc = data; 488 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 489 struct mtk_drm_private *priv = crtc->dev->dev_private; 490 491 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 492 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 493 #else 494 if (!priv->data->shadow_register) 495 #endif 496 mtk_crtc_ddp_config(crtc, NULL); 497 498 mtk_drm_finish_page_flip(mtk_crtc); 499 } 500 501 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 502 { 503 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 504 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 505 506 mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base); 507 508 return 0; 509 } 510 511 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 512 { 513 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 514 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 515 516 mtk_ddp_comp_disable_vblank(comp); 517 } 518 519 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 520 struct mtk_plane_state *state) 521 { 522 unsigned int local_layer; 523 struct mtk_ddp_comp *comp; 524 525 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 526 if (comp) 527 return mtk_ddp_comp_layer_check(comp, local_layer, state); 528 return 0; 529 } 530 531 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 532 struct drm_atomic_state *state) 533 { 534 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 535 536 if (!mtk_crtc->enabled) 537 return; 538 539 mtk_drm_crtc_update_config(mtk_crtc, false); 540 } 541 542 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 543 struct drm_atomic_state *state) 544 { 545 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 546 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 547 int ret; 548 549 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 550 551 ret = mtk_smi_larb_get(comp->larb_dev); 552 if (ret) { 553 DRM_ERROR("Failed to get larb: %d\n", ret); 554 return; 555 } 556 557 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 558 if (ret) { 559 mtk_smi_larb_put(comp->larb_dev); 560 return; 561 } 562 563 drm_crtc_vblank_on(crtc); 564 mtk_crtc->enabled = true; 565 } 566 567 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 568 struct drm_atomic_state *state) 569 { 570 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 571 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 572 int i; 573 574 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 575 if (!mtk_crtc->enabled) 576 return; 577 578 /* Set all pending plane state to disabled */ 579 for (i = 0; i < mtk_crtc->layer_nr; i++) { 580 struct drm_plane *plane = &mtk_crtc->planes[i]; 581 struct mtk_plane_state *plane_state; 582 583 plane_state = to_mtk_plane_state(plane->state); 584 plane_state->pending.enable = false; 585 plane_state->pending.config = true; 586 } 587 mtk_crtc->pending_planes = true; 588 589 mtk_drm_crtc_update_config(mtk_crtc, false); 590 /* Wait for planes to be disabled */ 591 drm_crtc_wait_one_vblank(crtc); 592 593 drm_crtc_vblank_off(crtc); 594 mtk_crtc_ddp_hw_fini(mtk_crtc); 595 mtk_smi_larb_put(comp->larb_dev); 596 597 mtk_crtc->enabled = false; 598 } 599 600 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 601 struct drm_atomic_state *state) 602 { 603 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 604 crtc); 605 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 606 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 607 608 if (mtk_crtc->event && mtk_crtc_state->base.event) 609 DRM_ERROR("new event while there is still a pending event\n"); 610 611 if (mtk_crtc_state->base.event) { 612 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 613 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 614 mtk_crtc->event = mtk_crtc_state->base.event; 615 mtk_crtc_state->base.event = NULL; 616 } 617 } 618 619 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 620 struct drm_atomic_state *state) 621 { 622 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 623 int i; 624 625 if (crtc->state->color_mgmt_changed) 626 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 627 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 628 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 629 } 630 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event); 631 } 632 633 static const struct drm_crtc_funcs mtk_crtc_funcs = { 634 .set_config = drm_atomic_helper_set_config, 635 .page_flip = drm_atomic_helper_page_flip, 636 .destroy = mtk_drm_crtc_destroy, 637 .reset = mtk_drm_crtc_reset, 638 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 639 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 640 .enable_vblank = mtk_drm_crtc_enable_vblank, 641 .disable_vblank = mtk_drm_crtc_disable_vblank, 642 }; 643 644 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 645 .mode_fixup = mtk_drm_crtc_mode_fixup, 646 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 647 .atomic_begin = mtk_drm_crtc_atomic_begin, 648 .atomic_flush = mtk_drm_crtc_atomic_flush, 649 .atomic_enable = mtk_drm_crtc_atomic_enable, 650 .atomic_disable = mtk_drm_crtc_atomic_disable, 651 }; 652 653 static int mtk_drm_crtc_init(struct drm_device *drm, 654 struct mtk_drm_crtc *mtk_crtc, 655 unsigned int pipe) 656 { 657 struct drm_plane *primary = NULL; 658 struct drm_plane *cursor = NULL; 659 int i, ret; 660 661 for (i = 0; i < mtk_crtc->layer_nr; i++) { 662 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 663 primary = &mtk_crtc->planes[i]; 664 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 665 cursor = &mtk_crtc->planes[i]; 666 } 667 668 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 669 &mtk_crtc_funcs, NULL); 670 if (ret) 671 goto err_cleanup_crtc; 672 673 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 674 675 return 0; 676 677 err_cleanup_crtc: 678 drm_crtc_cleanup(&mtk_crtc->base); 679 return ret; 680 } 681 682 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 683 int comp_idx) 684 { 685 struct mtk_ddp_comp *comp; 686 687 if (comp_idx > 1) 688 return 0; 689 690 comp = mtk_crtc->ddp_comp[comp_idx]; 691 if (!comp->funcs) 692 return 0; 693 694 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 695 return 0; 696 697 return mtk_ddp_comp_layer_nr(comp); 698 } 699 700 static inline 701 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 702 unsigned int num_planes) 703 { 704 if (plane_idx == 0) 705 return DRM_PLANE_TYPE_PRIMARY; 706 else if (plane_idx == (num_planes - 1)) 707 return DRM_PLANE_TYPE_CURSOR; 708 else 709 return DRM_PLANE_TYPE_OVERLAY; 710 711 } 712 713 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 714 struct mtk_drm_crtc *mtk_crtc, 715 int comp_idx, int pipe) 716 { 717 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 718 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 719 int i, ret; 720 721 for (i = 0; i < num_planes; i++) { 722 ret = mtk_plane_init(drm_dev, 723 &mtk_crtc->planes[mtk_crtc->layer_nr], 724 BIT(pipe), 725 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 726 num_planes), 727 mtk_ddp_comp_supported_rotations(comp)); 728 if (ret) 729 return ret; 730 731 mtk_crtc->layer_nr++; 732 } 733 return 0; 734 } 735 736 int mtk_drm_crtc_create(struct drm_device *drm_dev, 737 const enum mtk_ddp_comp_id *path, unsigned int path_len) 738 { 739 struct mtk_drm_private *priv = drm_dev->dev_private; 740 struct device *dev = drm_dev->dev; 741 struct mtk_drm_crtc *mtk_crtc; 742 unsigned int num_comp_planes = 0; 743 int pipe = priv->num_pipes; 744 int ret; 745 int i; 746 bool has_ctm = false; 747 uint gamma_lut_size = 0; 748 749 if (!path) 750 return 0; 751 752 for (i = 0; i < path_len; i++) { 753 enum mtk_ddp_comp_id comp_id = path[i]; 754 struct device_node *node; 755 struct mtk_ddp_comp *comp; 756 757 node = priv->comp_node[comp_id]; 758 comp = &priv->ddp_comp[comp_id]; 759 760 if (!node) { 761 dev_info(dev, 762 "Not creating crtc %d because component %d is disabled or missing\n", 763 pipe, comp_id); 764 return 0; 765 } 766 767 if (!comp->dev) { 768 dev_err(dev, "Component %pOF not initialized\n", node); 769 return -ENODEV; 770 } 771 } 772 773 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 774 if (!mtk_crtc) 775 return -ENOMEM; 776 777 mtk_crtc->mmsys_dev = priv->mmsys_dev; 778 mtk_crtc->ddp_comp_nr = path_len; 779 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 780 sizeof(*mtk_crtc->ddp_comp), 781 GFP_KERNEL); 782 if (!mtk_crtc->ddp_comp) 783 return -ENOMEM; 784 785 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); 786 if (IS_ERR(mtk_crtc->mutex)) { 787 ret = PTR_ERR(mtk_crtc->mutex); 788 dev_err(dev, "Failed to get mutex: %d\n", ret); 789 return ret; 790 } 791 792 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 793 enum mtk_ddp_comp_id comp_id = path[i]; 794 struct mtk_ddp_comp *comp; 795 796 comp = &priv->ddp_comp[comp_id]; 797 mtk_crtc->ddp_comp[i] = comp; 798 799 if (comp->funcs) { 800 if (comp->funcs->gamma_set) 801 gamma_lut_size = MTK_LUT_SIZE; 802 803 if (comp->funcs->ctm_set) 804 has_ctm = true; 805 } 806 } 807 808 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 809 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 810 811 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 812 sizeof(struct drm_plane), GFP_KERNEL); 813 814 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 815 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 816 pipe); 817 if (ret) 818 return ret; 819 } 820 821 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); 822 if (ret < 0) 823 return ret; 824 825 if (gamma_lut_size) 826 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 827 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 828 priv->num_pipes++; 829 mutex_init(&mtk_crtc->hw_lock); 830 831 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 832 mtk_crtc->cmdq_client = 833 cmdq_mbox_create(mtk_crtc->mmsys_dev, 834 drm_crtc_index(&mtk_crtc->base)); 835 if (IS_ERR(mtk_crtc->cmdq_client)) { 836 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 837 drm_crtc_index(&mtk_crtc->base)); 838 mtk_crtc->cmdq_client = NULL; 839 } 840 841 if (mtk_crtc->cmdq_client) { 842 ret = of_property_read_u32_index(priv->mutex_node, 843 "mediatek,gce-events", 844 drm_crtc_index(&mtk_crtc->base), 845 &mtk_crtc->cmdq_event); 846 if (ret) { 847 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 848 drm_crtc_index(&mtk_crtc->base)); 849 cmdq_mbox_destroy(mtk_crtc->cmdq_client); 850 mtk_crtc->cmdq_client = NULL; 851 } 852 } 853 #endif 854 return 0; 855 } 856