1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/mailbox_controller.h> 9 #include <linux/of.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/soc/mediatek/mtk-cmdq.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 15 #include <asm/barrier.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_probe_helper.h> 20 #include <drm/drm_vblank.h> 21 22 #include "mtk_drm_drv.h" 23 #include "mtk_drm_crtc.h" 24 #include "mtk_drm_ddp_comp.h" 25 #include "mtk_drm_gem.h" 26 #include "mtk_drm_plane.h" 27 28 /* 29 * struct mtk_drm_crtc - MediaTek specific crtc structure. 30 * @base: crtc object. 31 * @enabled: records whether crtc_enable succeeded 32 * @planes: array of 4 drm_plane structures, one for each overlay plane 33 * @pending_planes: whether any plane has pending changes to be applied 34 * @mmsys_dev: pointer to the mmsys device for configuration registers 35 * @mutex: handle to one of the ten disp_mutex streams 36 * @ddp_comp_nr: number of components in ddp_comp 37 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 38 * 39 * TODO: Needs update: this header is missing a bunch of member descriptions. 40 */ 41 struct mtk_drm_crtc { 42 struct drm_crtc base; 43 bool enabled; 44 45 bool pending_needs_vblank; 46 struct drm_pending_vblank_event *event; 47 48 struct drm_plane *planes; 49 unsigned int layer_nr; 50 bool pending_planes; 51 bool pending_async_planes; 52 53 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 54 struct cmdq_client cmdq_client; 55 struct cmdq_pkt cmdq_handle; 56 u32 cmdq_event; 57 u32 cmdq_vblank_cnt; 58 wait_queue_head_t cb_blocking_queue; 59 #endif 60 61 struct device *mmsys_dev; 62 struct device *dma_dev; 63 struct mtk_mutex *mutex; 64 unsigned int ddp_comp_nr; 65 struct mtk_ddp_comp **ddp_comp; 66 67 /* lock for display hardware access */ 68 struct mutex hw_lock; 69 bool config_updating; 70 }; 71 72 struct mtk_crtc_state { 73 struct drm_crtc_state base; 74 75 bool pending_config; 76 unsigned int pending_width; 77 unsigned int pending_height; 78 unsigned int pending_vrefresh; 79 }; 80 81 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 82 { 83 return container_of(c, struct mtk_drm_crtc, base); 84 } 85 86 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 87 { 88 return container_of(s, struct mtk_crtc_state, base); 89 } 90 91 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 92 { 93 struct drm_crtc *crtc = &mtk_crtc->base; 94 unsigned long flags; 95 96 spin_lock_irqsave(&crtc->dev->event_lock, flags); 97 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 98 drm_crtc_vblank_put(crtc); 99 mtk_crtc->event = NULL; 100 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 101 } 102 103 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 104 { 105 drm_crtc_handle_vblank(&mtk_crtc->base); 106 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) { 107 mtk_drm_crtc_finish_page_flip(mtk_crtc); 108 mtk_crtc->pending_needs_vblank = false; 109 } 110 } 111 112 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 113 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, 114 size_t size) 115 { 116 struct device *dev; 117 dma_addr_t dma_addr; 118 119 pkt->va_base = kzalloc(size, GFP_KERNEL); 120 if (!pkt->va_base) 121 return -ENOMEM; 122 123 pkt->buf_size = size; 124 pkt->cl = (void *)client; 125 126 dev = client->chan->mbox->dev; 127 dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, 128 DMA_TO_DEVICE); 129 if (dma_mapping_error(dev, dma_addr)) { 130 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); 131 kfree(pkt->va_base); 132 return -ENOMEM; 133 } 134 135 pkt->pa_base = dma_addr; 136 137 return 0; 138 } 139 140 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt) 141 { 142 struct cmdq_client *client = (struct cmdq_client *)pkt->cl; 143 144 dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, 145 DMA_TO_DEVICE); 146 kfree(pkt->va_base); 147 } 148 #endif 149 150 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 151 { 152 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 153 int i; 154 155 mtk_mutex_put(mtk_crtc->mutex); 156 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 157 mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle); 158 159 if (mtk_crtc->cmdq_client.chan) { 160 mbox_free_channel(mtk_crtc->cmdq_client.chan); 161 mtk_crtc->cmdq_client.chan = NULL; 162 } 163 #endif 164 165 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 166 struct mtk_ddp_comp *comp; 167 168 comp = mtk_crtc->ddp_comp[i]; 169 mtk_ddp_comp_unregister_vblank_cb(comp); 170 } 171 172 drm_crtc_cleanup(crtc); 173 } 174 175 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 176 { 177 struct mtk_crtc_state *state; 178 179 if (crtc->state) 180 __drm_atomic_helper_crtc_destroy_state(crtc->state); 181 182 kfree(to_mtk_crtc_state(crtc->state)); 183 crtc->state = NULL; 184 185 state = kzalloc(sizeof(*state), GFP_KERNEL); 186 if (state) 187 __drm_atomic_helper_crtc_reset(crtc, &state->base); 188 } 189 190 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 191 { 192 struct mtk_crtc_state *state; 193 194 state = kmalloc(sizeof(*state), GFP_KERNEL); 195 if (!state) 196 return NULL; 197 198 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 199 200 WARN_ON(state->base.crtc != crtc); 201 state->base.crtc = crtc; 202 state->pending_config = false; 203 204 return &state->base; 205 } 206 207 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 208 struct drm_crtc_state *state) 209 { 210 __drm_atomic_helper_crtc_destroy_state(state); 211 kfree(to_mtk_crtc_state(state)); 212 } 213 214 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 215 const struct drm_display_mode *mode, 216 struct drm_display_mode *adjusted_mode) 217 { 218 /* Nothing to do here, but this callback is mandatory. */ 219 return true; 220 } 221 222 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 223 { 224 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 225 226 state->pending_width = crtc->mode.hdisplay; 227 state->pending_height = crtc->mode.vdisplay; 228 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 229 wmb(); /* Make sure the above parameters are set before update */ 230 state->pending_config = true; 231 } 232 233 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 234 { 235 int ret; 236 int i; 237 238 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 239 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 240 if (ret) { 241 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 242 goto err; 243 } 244 } 245 246 return 0; 247 err: 248 while (--i >= 0) 249 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 250 return ret; 251 } 252 253 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 254 { 255 int i; 256 257 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 258 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 259 } 260 261 static 262 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 263 struct drm_plane *plane, 264 unsigned int *local_layer) 265 { 266 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 267 struct mtk_ddp_comp *comp; 268 int i, count = 0; 269 unsigned int local_index = plane - mtk_crtc->planes; 270 271 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 272 comp = mtk_crtc->ddp_comp[i]; 273 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 274 *local_layer = local_index - count; 275 return comp; 276 } 277 count += mtk_ddp_comp_layer_nr(comp); 278 } 279 280 WARN(1, "Failed to find component for plane %d\n", plane->index); 281 return NULL; 282 } 283 284 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 285 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) 286 { 287 struct cmdq_cb_data *data = mssg; 288 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); 289 struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); 290 struct mtk_crtc_state *state; 291 unsigned int i; 292 293 if (data->sta < 0) 294 return; 295 296 state = to_mtk_crtc_state(mtk_crtc->base.state); 297 298 state->pending_config = false; 299 300 if (mtk_crtc->pending_planes) { 301 for (i = 0; i < mtk_crtc->layer_nr; i++) { 302 struct drm_plane *plane = &mtk_crtc->planes[i]; 303 struct mtk_plane_state *plane_state; 304 305 plane_state = to_mtk_plane_state(plane->state); 306 307 plane_state->pending.config = false; 308 } 309 mtk_crtc->pending_planes = false; 310 } 311 312 if (mtk_crtc->pending_async_planes) { 313 for (i = 0; i < mtk_crtc->layer_nr; i++) { 314 struct drm_plane *plane = &mtk_crtc->planes[i]; 315 struct mtk_plane_state *plane_state; 316 317 plane_state = to_mtk_plane_state(plane->state); 318 319 plane_state->pending.async_config = false; 320 } 321 mtk_crtc->pending_async_planes = false; 322 } 323 324 mtk_crtc->cmdq_vblank_cnt = 0; 325 wake_up(&mtk_crtc->cb_blocking_queue); 326 } 327 #endif 328 329 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 330 { 331 struct drm_crtc *crtc = &mtk_crtc->base; 332 struct drm_connector *connector; 333 struct drm_encoder *encoder; 334 struct drm_connector_list_iter conn_iter; 335 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 336 int ret; 337 int i; 338 339 if (WARN_ON(!crtc->state)) 340 return -EINVAL; 341 342 width = crtc->state->adjusted_mode.hdisplay; 343 height = crtc->state->adjusted_mode.vdisplay; 344 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 345 346 drm_for_each_encoder(encoder, crtc->dev) { 347 if (encoder->crtc != crtc) 348 continue; 349 350 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 351 drm_for_each_connector_iter(connector, &conn_iter) { 352 if (connector->encoder != encoder) 353 continue; 354 if (connector->display_info.bpc != 0 && 355 bpc > connector->display_info.bpc) 356 bpc = connector->display_info.bpc; 357 } 358 drm_connector_list_iter_end(&conn_iter); 359 } 360 361 ret = pm_runtime_resume_and_get(crtc->dev->dev); 362 if (ret < 0) { 363 DRM_ERROR("Failed to enable power domain: %d\n", ret); 364 return ret; 365 } 366 367 ret = mtk_mutex_prepare(mtk_crtc->mutex); 368 if (ret < 0) { 369 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 370 goto err_pm_runtime_put; 371 } 372 373 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 374 if (ret < 0) { 375 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 376 goto err_mutex_unprepare; 377 } 378 379 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 380 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 381 mtk_crtc->ddp_comp[i + 1]->id)) 382 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 383 mtk_crtc->ddp_comp[i]->id, 384 mtk_crtc->ddp_comp[i + 1]->id); 385 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 386 mtk_mutex_add_comp(mtk_crtc->mutex, 387 mtk_crtc->ddp_comp[i]->id); 388 } 389 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 390 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 391 mtk_mutex_enable(mtk_crtc->mutex); 392 393 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 394 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 395 396 if (i == 1) 397 mtk_ddp_comp_bgclr_in_on(comp); 398 399 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 400 mtk_ddp_comp_start(comp); 401 } 402 403 /* Initially configure all planes */ 404 for (i = 0; i < mtk_crtc->layer_nr; i++) { 405 struct drm_plane *plane = &mtk_crtc->planes[i]; 406 struct mtk_plane_state *plane_state; 407 struct mtk_ddp_comp *comp; 408 unsigned int local_layer; 409 410 plane_state = to_mtk_plane_state(plane->state); 411 412 /* should not enable layer before crtc enabled */ 413 plane_state->pending.enable = false; 414 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 415 if (comp) 416 mtk_ddp_comp_layer_config(comp, local_layer, 417 plane_state, NULL); 418 } 419 420 return 0; 421 422 err_mutex_unprepare: 423 mtk_mutex_unprepare(mtk_crtc->mutex); 424 err_pm_runtime_put: 425 pm_runtime_put(crtc->dev->dev); 426 return ret; 427 } 428 429 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 430 { 431 struct drm_device *drm = mtk_crtc->base.dev; 432 struct drm_crtc *crtc = &mtk_crtc->base; 433 int i; 434 435 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 436 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 437 if (i == 1) 438 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 439 } 440 441 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 442 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 443 mtk_mutex_remove_comp(mtk_crtc->mutex, 444 mtk_crtc->ddp_comp[i]->id); 445 mtk_mutex_disable(mtk_crtc->mutex); 446 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 447 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 448 mtk_crtc->ddp_comp[i + 1]->id)) 449 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 450 mtk_crtc->ddp_comp[i]->id, 451 mtk_crtc->ddp_comp[i + 1]->id); 452 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 453 mtk_mutex_remove_comp(mtk_crtc->mutex, 454 mtk_crtc->ddp_comp[i]->id); 455 } 456 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 457 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 458 mtk_crtc_ddp_clk_disable(mtk_crtc); 459 mtk_mutex_unprepare(mtk_crtc->mutex); 460 461 pm_runtime_put(drm->dev); 462 463 if (crtc->state->event && !crtc->state->active) { 464 spin_lock_irq(&crtc->dev->event_lock); 465 drm_crtc_send_vblank_event(crtc, crtc->state->event); 466 crtc->state->event = NULL; 467 spin_unlock_irq(&crtc->dev->event_lock); 468 } 469 } 470 471 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 472 struct cmdq_pkt *cmdq_handle) 473 { 474 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 475 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 476 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 477 unsigned int i; 478 unsigned int local_layer; 479 480 /* 481 * TODO: instead of updating the registers here, we should prepare 482 * working registers in atomic_commit and let the hardware command 483 * queue update module registers on vblank. 484 */ 485 if (state->pending_config) { 486 mtk_ddp_comp_config(comp, state->pending_width, 487 state->pending_height, 488 state->pending_vrefresh, 0, 489 cmdq_handle); 490 491 if (!cmdq_handle) 492 state->pending_config = false; 493 } 494 495 if (mtk_crtc->pending_planes) { 496 for (i = 0; i < mtk_crtc->layer_nr; i++) { 497 struct drm_plane *plane = &mtk_crtc->planes[i]; 498 struct mtk_plane_state *plane_state; 499 500 plane_state = to_mtk_plane_state(plane->state); 501 502 if (!plane_state->pending.config) 503 continue; 504 505 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 506 &local_layer); 507 508 if (comp) 509 mtk_ddp_comp_layer_config(comp, local_layer, 510 plane_state, 511 cmdq_handle); 512 if (!cmdq_handle) 513 plane_state->pending.config = false; 514 } 515 516 if (!cmdq_handle) 517 mtk_crtc->pending_planes = false; 518 } 519 520 if (mtk_crtc->pending_async_planes) { 521 for (i = 0; i < mtk_crtc->layer_nr; i++) { 522 struct drm_plane *plane = &mtk_crtc->planes[i]; 523 struct mtk_plane_state *plane_state; 524 525 plane_state = to_mtk_plane_state(plane->state); 526 527 if (!plane_state->pending.async_config) 528 continue; 529 530 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 531 &local_layer); 532 533 if (comp) 534 mtk_ddp_comp_layer_config(comp, local_layer, 535 plane_state, 536 cmdq_handle); 537 if (!cmdq_handle) 538 plane_state->pending.async_config = false; 539 } 540 541 if (!cmdq_handle) 542 mtk_crtc->pending_async_planes = false; 543 } 544 } 545 546 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 547 bool needs_vblank) 548 { 549 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 550 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle; 551 #endif 552 struct drm_crtc *crtc = &mtk_crtc->base; 553 struct mtk_drm_private *priv = crtc->dev->dev_private; 554 unsigned int pending_planes = 0, pending_async_planes = 0; 555 int i; 556 557 mutex_lock(&mtk_crtc->hw_lock); 558 mtk_crtc->config_updating = true; 559 if (needs_vblank) 560 mtk_crtc->pending_needs_vblank = true; 561 562 for (i = 0; i < mtk_crtc->layer_nr; i++) { 563 struct drm_plane *plane = &mtk_crtc->planes[i]; 564 struct mtk_plane_state *plane_state; 565 566 plane_state = to_mtk_plane_state(plane->state); 567 if (plane_state->pending.dirty) { 568 plane_state->pending.config = true; 569 plane_state->pending.dirty = false; 570 pending_planes |= BIT(i); 571 } else if (plane_state->pending.async_dirty) { 572 plane_state->pending.async_config = true; 573 plane_state->pending.async_dirty = false; 574 pending_async_planes |= BIT(i); 575 } 576 } 577 if (pending_planes) 578 mtk_crtc->pending_planes = true; 579 if (pending_async_planes) 580 mtk_crtc->pending_async_planes = true; 581 582 if (priv->data->shadow_register) { 583 mtk_mutex_acquire(mtk_crtc->mutex); 584 mtk_crtc_ddp_config(crtc, NULL); 585 mtk_mutex_release(mtk_crtc->mutex); 586 } 587 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 588 if (mtk_crtc->cmdq_client.chan) { 589 mbox_flush(mtk_crtc->cmdq_client.chan, 2000); 590 cmdq_handle->cmd_buf_size = 0; 591 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 592 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 593 mtk_crtc_ddp_config(crtc, cmdq_handle); 594 cmdq_pkt_finalize(cmdq_handle); 595 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev, 596 cmdq_handle->pa_base, 597 cmdq_handle->cmd_buf_size, 598 DMA_TO_DEVICE); 599 /* 600 * CMDQ command should execute in next 3 vblank. 601 * One vblank interrupt before send message (occasionally) 602 * and one vblank interrupt after cmdq done, 603 * so it's timeout after 3 vblank interrupt. 604 * If it fail to execute in next 3 vblank, timeout happen. 605 */ 606 mtk_crtc->cmdq_vblank_cnt = 3; 607 608 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); 609 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); 610 } 611 #endif 612 mtk_crtc->config_updating = false; 613 mutex_unlock(&mtk_crtc->hw_lock); 614 } 615 616 static void mtk_crtc_ddp_irq(void *data) 617 { 618 struct drm_crtc *crtc = data; 619 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 620 struct mtk_drm_private *priv = crtc->dev->dev_private; 621 622 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 623 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) 624 mtk_crtc_ddp_config(crtc, NULL); 625 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) 626 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", 627 drm_crtc_index(&mtk_crtc->base)); 628 #else 629 if (!priv->data->shadow_register) 630 mtk_crtc_ddp_config(crtc, NULL); 631 #endif 632 mtk_drm_finish_page_flip(mtk_crtc); 633 } 634 635 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 636 { 637 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 638 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 639 640 mtk_ddp_comp_enable_vblank(comp); 641 642 return 0; 643 } 644 645 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 646 { 647 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 648 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 649 650 mtk_ddp_comp_disable_vblank(comp); 651 } 652 653 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 654 struct mtk_plane_state *state) 655 { 656 unsigned int local_layer; 657 struct mtk_ddp_comp *comp; 658 659 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 660 if (comp) 661 return mtk_ddp_comp_layer_check(comp, local_layer, state); 662 return 0; 663 } 664 665 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 666 struct drm_atomic_state *state) 667 { 668 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 669 670 if (!mtk_crtc->enabled) 671 return; 672 673 mtk_drm_crtc_update_config(mtk_crtc, false); 674 } 675 676 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 677 struct drm_atomic_state *state) 678 { 679 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 680 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 681 int ret; 682 683 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 684 685 ret = pm_runtime_resume_and_get(comp->dev); 686 if (ret < 0) { 687 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret); 688 return; 689 } 690 691 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 692 if (ret) { 693 pm_runtime_put(comp->dev); 694 return; 695 } 696 697 drm_crtc_vblank_on(crtc); 698 mtk_crtc->enabled = true; 699 } 700 701 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 702 struct drm_atomic_state *state) 703 { 704 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 705 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 706 int i, ret; 707 708 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 709 if (!mtk_crtc->enabled) 710 return; 711 712 /* Set all pending plane state to disabled */ 713 for (i = 0; i < mtk_crtc->layer_nr; i++) { 714 struct drm_plane *plane = &mtk_crtc->planes[i]; 715 struct mtk_plane_state *plane_state; 716 717 plane_state = to_mtk_plane_state(plane->state); 718 plane_state->pending.enable = false; 719 plane_state->pending.config = true; 720 } 721 mtk_crtc->pending_planes = true; 722 723 mtk_drm_crtc_update_config(mtk_crtc, false); 724 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 725 /* Wait for planes to be disabled by cmdq */ 726 if (mtk_crtc->cmdq_client.chan) 727 wait_event_timeout(mtk_crtc->cb_blocking_queue, 728 mtk_crtc->cmdq_vblank_cnt == 0, 729 msecs_to_jiffies(500)); 730 #endif 731 /* Wait for planes to be disabled */ 732 drm_crtc_wait_one_vblank(crtc); 733 734 drm_crtc_vblank_off(crtc); 735 mtk_crtc_ddp_hw_fini(mtk_crtc); 736 ret = pm_runtime_put(comp->dev); 737 if (ret < 0) 738 DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret); 739 740 mtk_crtc->enabled = false; 741 } 742 743 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 744 struct drm_atomic_state *state) 745 { 746 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 747 crtc); 748 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 749 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 750 unsigned long flags; 751 752 if (mtk_crtc->event && mtk_crtc_state->base.event) 753 DRM_ERROR("new event while there is still a pending event\n"); 754 755 if (mtk_crtc_state->base.event) { 756 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 757 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 758 759 spin_lock_irqsave(&crtc->dev->event_lock, flags); 760 mtk_crtc->event = mtk_crtc_state->base.event; 761 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 762 763 mtk_crtc_state->base.event = NULL; 764 } 765 } 766 767 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 768 struct drm_atomic_state *state) 769 { 770 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 771 int i; 772 773 if (crtc->state->color_mgmt_changed) 774 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 775 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 776 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 777 } 778 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event); 779 } 780 781 static const struct drm_crtc_funcs mtk_crtc_funcs = { 782 .set_config = drm_atomic_helper_set_config, 783 .page_flip = drm_atomic_helper_page_flip, 784 .destroy = mtk_drm_crtc_destroy, 785 .reset = mtk_drm_crtc_reset, 786 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 787 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 788 .enable_vblank = mtk_drm_crtc_enable_vblank, 789 .disable_vblank = mtk_drm_crtc_disable_vblank, 790 }; 791 792 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 793 .mode_fixup = mtk_drm_crtc_mode_fixup, 794 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 795 .atomic_begin = mtk_drm_crtc_atomic_begin, 796 .atomic_flush = mtk_drm_crtc_atomic_flush, 797 .atomic_enable = mtk_drm_crtc_atomic_enable, 798 .atomic_disable = mtk_drm_crtc_atomic_disable, 799 }; 800 801 static int mtk_drm_crtc_init(struct drm_device *drm, 802 struct mtk_drm_crtc *mtk_crtc, 803 unsigned int pipe) 804 { 805 struct drm_plane *primary = NULL; 806 struct drm_plane *cursor = NULL; 807 int i, ret; 808 809 for (i = 0; i < mtk_crtc->layer_nr; i++) { 810 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 811 primary = &mtk_crtc->planes[i]; 812 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 813 cursor = &mtk_crtc->planes[i]; 814 } 815 816 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 817 &mtk_crtc_funcs, NULL); 818 if (ret) 819 goto err_cleanup_crtc; 820 821 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 822 823 return 0; 824 825 err_cleanup_crtc: 826 drm_crtc_cleanup(&mtk_crtc->base); 827 return ret; 828 } 829 830 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 831 int comp_idx) 832 { 833 struct mtk_ddp_comp *comp; 834 835 if (comp_idx > 1) 836 return 0; 837 838 comp = mtk_crtc->ddp_comp[comp_idx]; 839 if (!comp->funcs) 840 return 0; 841 842 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 843 return 0; 844 845 return mtk_ddp_comp_layer_nr(comp); 846 } 847 848 static inline 849 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 850 unsigned int num_planes) 851 { 852 if (plane_idx == 0) 853 return DRM_PLANE_TYPE_PRIMARY; 854 else if (plane_idx == (num_planes - 1)) 855 return DRM_PLANE_TYPE_CURSOR; 856 else 857 return DRM_PLANE_TYPE_OVERLAY; 858 859 } 860 861 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 862 struct mtk_drm_crtc *mtk_crtc, 863 int comp_idx, int pipe) 864 { 865 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 866 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 867 int i, ret; 868 869 for (i = 0; i < num_planes; i++) { 870 ret = mtk_plane_init(drm_dev, 871 &mtk_crtc->planes[mtk_crtc->layer_nr], 872 BIT(pipe), 873 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 874 num_planes), 875 mtk_ddp_comp_supported_rotations(comp), 876 mtk_ddp_comp_get_formats(comp), 877 mtk_ddp_comp_get_num_formats(comp)); 878 if (ret) 879 return ret; 880 881 mtk_crtc->layer_nr++; 882 } 883 return 0; 884 } 885 886 struct device *mtk_drm_crtc_dma_dev_get(struct drm_crtc *crtc) 887 { 888 struct mtk_drm_crtc *mtk_crtc = NULL; 889 890 if (!crtc) 891 return NULL; 892 893 mtk_crtc = to_mtk_crtc(crtc); 894 if (!mtk_crtc) 895 return NULL; 896 897 return mtk_crtc->dma_dev; 898 } 899 900 int mtk_drm_crtc_create(struct drm_device *drm_dev, 901 const unsigned int *path, unsigned int path_len, 902 int priv_data_index) 903 { 904 struct mtk_drm_private *priv = drm_dev->dev_private; 905 struct device *dev = drm_dev->dev; 906 struct mtk_drm_crtc *mtk_crtc; 907 unsigned int num_comp_planes = 0; 908 int ret; 909 int i; 910 bool has_ctm = false; 911 uint gamma_lut_size = 0; 912 struct drm_crtc *tmp; 913 int crtc_i = 0; 914 915 if (!path) 916 return 0; 917 918 priv = priv->all_drm_private[priv_data_index]; 919 920 drm_for_each_crtc(tmp, drm_dev) 921 crtc_i++; 922 923 for (i = 0; i < path_len; i++) { 924 enum mtk_ddp_comp_id comp_id = path[i]; 925 struct device_node *node; 926 struct mtk_ddp_comp *comp; 927 928 node = priv->comp_node[comp_id]; 929 comp = &priv->ddp_comp[comp_id]; 930 931 /* Not all drm components have a DTS device node, such as ovl_adaptor, 932 * which is the drm bring up sub driver 933 */ 934 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) { 935 dev_info(dev, 936 "Not creating crtc %d because component %d is disabled or missing\n", 937 crtc_i, comp_id); 938 return 0; 939 } 940 941 if (!comp->dev) { 942 dev_err(dev, "Component %pOF not initialized\n", node); 943 return -ENODEV; 944 } 945 } 946 947 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 948 if (!mtk_crtc) 949 return -ENOMEM; 950 951 mtk_crtc->mmsys_dev = priv->mmsys_dev; 952 mtk_crtc->ddp_comp_nr = path_len; 953 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 954 sizeof(*mtk_crtc->ddp_comp), 955 GFP_KERNEL); 956 if (!mtk_crtc->ddp_comp) 957 return -ENOMEM; 958 959 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); 960 if (IS_ERR(mtk_crtc->mutex)) { 961 ret = PTR_ERR(mtk_crtc->mutex); 962 dev_err(dev, "Failed to get mutex: %d\n", ret); 963 return ret; 964 } 965 966 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 967 unsigned int comp_id = path[i]; 968 struct mtk_ddp_comp *comp; 969 970 comp = &priv->ddp_comp[comp_id]; 971 mtk_crtc->ddp_comp[i] = comp; 972 973 if (comp->funcs) { 974 if (comp->funcs->gamma_set) 975 gamma_lut_size = MTK_LUT_SIZE; 976 977 if (comp->funcs->ctm_set) 978 has_ctm = true; 979 } 980 981 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, 982 &mtk_crtc->base); 983 } 984 985 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 986 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 987 988 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 989 sizeof(struct drm_plane), GFP_KERNEL); 990 if (!mtk_crtc->planes) 991 return -ENOMEM; 992 993 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 994 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 995 crtc_i); 996 if (ret) 997 return ret; 998 } 999 1000 /* 1001 * Default to use the first component as the dma dev. 1002 * In the case of ovl_adaptor sub driver, it needs to use the 1003 * dma_dev_get function to get representative dma dev. 1004 */ 1005 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]); 1006 1007 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i); 1008 if (ret < 0) 1009 return ret; 1010 1011 if (gamma_lut_size) 1012 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 1013 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 1014 mutex_init(&mtk_crtc->hw_lock); 1015 1016 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 1017 i = priv->mbox_index++; 1018 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev; 1019 mtk_crtc->cmdq_client.client.tx_block = false; 1020 mtk_crtc->cmdq_client.client.knows_txdone = true; 1021 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb; 1022 mtk_crtc->cmdq_client.chan = 1023 mbox_request_channel(&mtk_crtc->cmdq_client.client, i); 1024 if (IS_ERR(mtk_crtc->cmdq_client.chan)) { 1025 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 1026 drm_crtc_index(&mtk_crtc->base)); 1027 mtk_crtc->cmdq_client.chan = NULL; 1028 } 1029 1030 if (mtk_crtc->cmdq_client.chan) { 1031 ret = of_property_read_u32_index(priv->mutex_node, 1032 "mediatek,gce-events", 1033 i, 1034 &mtk_crtc->cmdq_event); 1035 if (ret) { 1036 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 1037 drm_crtc_index(&mtk_crtc->base)); 1038 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1039 mtk_crtc->cmdq_client.chan = NULL; 1040 } else { 1041 ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client, 1042 &mtk_crtc->cmdq_handle, 1043 PAGE_SIZE); 1044 if (ret) { 1045 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n", 1046 drm_crtc_index(&mtk_crtc->base)); 1047 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1048 mtk_crtc->cmdq_client.chan = NULL; 1049 } 1050 } 1051 1052 /* for sending blocking cmd in crtc disable */ 1053 init_waitqueue_head(&mtk_crtc->cb_blocking_queue); 1054 } 1055 #endif 1056 return 0; 1057 } 1058