1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/mailbox_controller.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/soc/mediatek/mtk-cmdq.h>
11 #include <linux/soc/mediatek/mtk-mmsys.h>
12 #include <linux/soc/mediatek/mtk-mutex.h>
13 
14 #include <asm/barrier.h>
15 
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_vblank.h>
20 
21 #include "mtk_drm_drv.h"
22 #include "mtk_drm_crtc.h"
23 #include "mtk_drm_ddp_comp.h"
24 #include "mtk_drm_gem.h"
25 #include "mtk_drm_plane.h"
26 
27 /*
28  * struct mtk_drm_crtc - MediaTek specific crtc structure.
29  * @base: crtc object.
30  * @enabled: records whether crtc_enable succeeded
31  * @planes: array of 4 drm_plane structures, one for each overlay plane
32  * @pending_planes: whether any plane has pending changes to be applied
33  * @mmsys_dev: pointer to the mmsys device for configuration registers
34  * @mutex: handle to one of the ten disp_mutex streams
35  * @ddp_comp_nr: number of components in ddp_comp
36  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
37  *
38  * TODO: Needs update: this header is missing a bunch of member descriptions.
39  */
40 struct mtk_drm_crtc {
41 	struct drm_crtc			base;
42 	bool				enabled;
43 
44 	bool				pending_needs_vblank;
45 	struct drm_pending_vblank_event	*event;
46 
47 	struct drm_plane		*planes;
48 	unsigned int			layer_nr;
49 	bool				pending_planes;
50 	bool				pending_async_planes;
51 
52 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
53 	struct cmdq_client		cmdq_client;
54 	struct cmdq_pkt			cmdq_handle;
55 	u32				cmdq_event;
56 	u32				cmdq_vblank_cnt;
57 	wait_queue_head_t		cb_blocking_queue;
58 #endif
59 
60 	struct device			*mmsys_dev;
61 	struct mtk_mutex		*mutex;
62 	unsigned int			ddp_comp_nr;
63 	struct mtk_ddp_comp		**ddp_comp;
64 
65 	/* lock for display hardware access */
66 	struct mutex			hw_lock;
67 	bool				config_updating;
68 };
69 
70 struct mtk_crtc_state {
71 	struct drm_crtc_state		base;
72 
73 	bool				pending_config;
74 	unsigned int			pending_width;
75 	unsigned int			pending_height;
76 	unsigned int			pending_vrefresh;
77 };
78 
79 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
80 {
81 	return container_of(c, struct mtk_drm_crtc, base);
82 }
83 
84 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
85 {
86 	return container_of(s, struct mtk_crtc_state, base);
87 }
88 
89 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
90 {
91 	struct drm_crtc *crtc = &mtk_crtc->base;
92 	unsigned long flags;
93 
94 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
95 	drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
96 	drm_crtc_vblank_put(crtc);
97 	mtk_crtc->event = NULL;
98 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
99 }
100 
101 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
102 {
103 	drm_crtc_handle_vblank(&mtk_crtc->base);
104 	if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
105 		mtk_drm_crtc_finish_page_flip(mtk_crtc);
106 		mtk_crtc->pending_needs_vblank = false;
107 	}
108 }
109 
110 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
111 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,
112 				   size_t size)
113 {
114 	struct device *dev;
115 	dma_addr_t dma_addr;
116 
117 	pkt->va_base = kzalloc(size, GFP_KERNEL);
118 	if (!pkt->va_base) {
119 		kfree(pkt);
120 		return -ENOMEM;
121 	}
122 	pkt->buf_size = size;
123 	pkt->cl = (void *)client;
124 
125 	dev = client->chan->mbox->dev;
126 	dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
127 				  DMA_TO_DEVICE);
128 	if (dma_mapping_error(dev, dma_addr)) {
129 		dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
130 		kfree(pkt->va_base);
131 		kfree(pkt);
132 		return -ENOMEM;
133 	}
134 
135 	pkt->pa_base = dma_addr;
136 
137 	return 0;
138 }
139 
140 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt)
141 {
142 	struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
143 
144 	dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
145 			 DMA_TO_DEVICE);
146 	kfree(pkt->va_base);
147 	kfree(pkt);
148 }
149 #endif
150 
151 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
152 {
153 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
154 	int i;
155 
156 	mtk_mutex_put(mtk_crtc->mutex);
157 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
158 	mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle);
159 
160 	if (mtk_crtc->cmdq_client.chan) {
161 		mbox_free_channel(mtk_crtc->cmdq_client.chan);
162 		mtk_crtc->cmdq_client.chan = NULL;
163 	}
164 #endif
165 
166 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
167 		struct mtk_ddp_comp *comp;
168 
169 		comp = mtk_crtc->ddp_comp[i];
170 		mtk_ddp_comp_unregister_vblank_cb(comp);
171 	}
172 
173 	drm_crtc_cleanup(crtc);
174 }
175 
176 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
177 {
178 	struct mtk_crtc_state *state;
179 
180 	if (crtc->state)
181 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
182 
183 	kfree(to_mtk_crtc_state(crtc->state));
184 	crtc->state = NULL;
185 
186 	state = kzalloc(sizeof(*state), GFP_KERNEL);
187 	if (state)
188 		__drm_atomic_helper_crtc_reset(crtc, &state->base);
189 }
190 
191 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
192 {
193 	struct mtk_crtc_state *state;
194 
195 	state = kmalloc(sizeof(*state), GFP_KERNEL);
196 	if (!state)
197 		return NULL;
198 
199 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
200 
201 	WARN_ON(state->base.crtc != crtc);
202 	state->base.crtc = crtc;
203 	state->pending_config = false;
204 
205 	return &state->base;
206 }
207 
208 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
209 				       struct drm_crtc_state *state)
210 {
211 	__drm_atomic_helper_crtc_destroy_state(state);
212 	kfree(to_mtk_crtc_state(state));
213 }
214 
215 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
216 				    const struct drm_display_mode *mode,
217 				    struct drm_display_mode *adjusted_mode)
218 {
219 	/* Nothing to do here, but this callback is mandatory. */
220 	return true;
221 }
222 
223 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
224 {
225 	struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
226 
227 	state->pending_width = crtc->mode.hdisplay;
228 	state->pending_height = crtc->mode.vdisplay;
229 	state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
230 	wmb();	/* Make sure the above parameters are set before update */
231 	state->pending_config = true;
232 }
233 
234 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
235 {
236 	int ret;
237 	int i;
238 
239 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
240 		ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
241 		if (ret) {
242 			DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
243 			goto err;
244 		}
245 	}
246 
247 	return 0;
248 err:
249 	while (--i >= 0)
250 		mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
251 	return ret;
252 }
253 
254 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
255 {
256 	int i;
257 
258 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
259 		mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
260 }
261 
262 static
263 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
264 						struct drm_plane *plane,
265 						unsigned int *local_layer)
266 {
267 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
268 	struct mtk_ddp_comp *comp;
269 	int i, count = 0;
270 	unsigned int local_index = plane - mtk_crtc->planes;
271 
272 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
273 		comp = mtk_crtc->ddp_comp[i];
274 		if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
275 			*local_layer = local_index - count;
276 			return comp;
277 		}
278 		count += mtk_ddp_comp_layer_nr(comp);
279 	}
280 
281 	WARN(1, "Failed to find component for plane %d\n", plane->index);
282 	return NULL;
283 }
284 
285 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
286 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
287 {
288 	struct cmdq_cb_data *data = mssg;
289 	struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
290 	struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client);
291 	struct mtk_crtc_state *state;
292 	unsigned int i;
293 
294 	if (data->sta < 0)
295 		return;
296 
297 	state = to_mtk_crtc_state(mtk_crtc->base.state);
298 
299 	state->pending_config = false;
300 
301 	if (mtk_crtc->pending_planes) {
302 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
303 			struct drm_plane *plane = &mtk_crtc->planes[i];
304 			struct mtk_plane_state *plane_state;
305 
306 			plane_state = to_mtk_plane_state(plane->state);
307 
308 			plane_state->pending.config = false;
309 		}
310 		mtk_crtc->pending_planes = false;
311 	}
312 
313 	if (mtk_crtc->pending_async_planes) {
314 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
315 			struct drm_plane *plane = &mtk_crtc->planes[i];
316 			struct mtk_plane_state *plane_state;
317 
318 			plane_state = to_mtk_plane_state(plane->state);
319 
320 			plane_state->pending.async_config = false;
321 		}
322 		mtk_crtc->pending_async_planes = false;
323 	}
324 
325 	mtk_crtc->cmdq_vblank_cnt = 0;
326 	wake_up(&mtk_crtc->cb_blocking_queue);
327 }
328 #endif
329 
330 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
331 {
332 	struct drm_crtc *crtc = &mtk_crtc->base;
333 	struct drm_connector *connector;
334 	struct drm_encoder *encoder;
335 	struct drm_connector_list_iter conn_iter;
336 	unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
337 	int ret;
338 	int i;
339 
340 	if (WARN_ON(!crtc->state))
341 		return -EINVAL;
342 
343 	width = crtc->state->adjusted_mode.hdisplay;
344 	height = crtc->state->adjusted_mode.vdisplay;
345 	vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
346 
347 	drm_for_each_encoder(encoder, crtc->dev) {
348 		if (encoder->crtc != crtc)
349 			continue;
350 
351 		drm_connector_list_iter_begin(crtc->dev, &conn_iter);
352 		drm_for_each_connector_iter(connector, &conn_iter) {
353 			if (connector->encoder != encoder)
354 				continue;
355 			if (connector->display_info.bpc != 0 &&
356 			    bpc > connector->display_info.bpc)
357 				bpc = connector->display_info.bpc;
358 		}
359 		drm_connector_list_iter_end(&conn_iter);
360 	}
361 
362 	ret = pm_runtime_resume_and_get(crtc->dev->dev);
363 	if (ret < 0) {
364 		DRM_ERROR("Failed to enable power domain: %d\n", ret);
365 		return ret;
366 	}
367 
368 	ret = mtk_mutex_prepare(mtk_crtc->mutex);
369 	if (ret < 0) {
370 		DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
371 		goto err_pm_runtime_put;
372 	}
373 
374 	ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
375 	if (ret < 0) {
376 		DRM_ERROR("Failed to enable component clocks: %d\n", ret);
377 		goto err_mutex_unprepare;
378 	}
379 
380 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
381 		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
382 				      mtk_crtc->ddp_comp[i]->id,
383 				      mtk_crtc->ddp_comp[i + 1]->id);
384 		mtk_mutex_add_comp(mtk_crtc->mutex,
385 					mtk_crtc->ddp_comp[i]->id);
386 	}
387 	mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
388 	mtk_mutex_enable(mtk_crtc->mutex);
389 
390 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
391 		struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
392 
393 		if (i == 1)
394 			mtk_ddp_comp_bgclr_in_on(comp);
395 
396 		mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
397 		mtk_ddp_comp_start(comp);
398 	}
399 
400 	/* Initially configure all planes */
401 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
402 		struct drm_plane *plane = &mtk_crtc->planes[i];
403 		struct mtk_plane_state *plane_state;
404 		struct mtk_ddp_comp *comp;
405 		unsigned int local_layer;
406 
407 		plane_state = to_mtk_plane_state(plane->state);
408 		comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
409 		if (comp)
410 			mtk_ddp_comp_layer_config(comp, local_layer,
411 						  plane_state, NULL);
412 	}
413 
414 	return 0;
415 
416 err_mutex_unprepare:
417 	mtk_mutex_unprepare(mtk_crtc->mutex);
418 err_pm_runtime_put:
419 	pm_runtime_put(crtc->dev->dev);
420 	return ret;
421 }
422 
423 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
424 {
425 	struct drm_device *drm = mtk_crtc->base.dev;
426 	struct drm_crtc *crtc = &mtk_crtc->base;
427 	int i;
428 
429 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
430 		mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
431 		if (i == 1)
432 			mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
433 	}
434 
435 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
436 		mtk_mutex_remove_comp(mtk_crtc->mutex,
437 					   mtk_crtc->ddp_comp[i]->id);
438 	mtk_mutex_disable(mtk_crtc->mutex);
439 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
440 		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
441 					 mtk_crtc->ddp_comp[i]->id,
442 					 mtk_crtc->ddp_comp[i + 1]->id);
443 		mtk_mutex_remove_comp(mtk_crtc->mutex,
444 					   mtk_crtc->ddp_comp[i]->id);
445 	}
446 	mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
447 	mtk_crtc_ddp_clk_disable(mtk_crtc);
448 	mtk_mutex_unprepare(mtk_crtc->mutex);
449 
450 	pm_runtime_put(drm->dev);
451 
452 	if (crtc->state->event && !crtc->state->active) {
453 		spin_lock_irq(&crtc->dev->event_lock);
454 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
455 		crtc->state->event = NULL;
456 		spin_unlock_irq(&crtc->dev->event_lock);
457 	}
458 }
459 
460 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
461 				struct cmdq_pkt *cmdq_handle)
462 {
463 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
464 	struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
465 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
466 	unsigned int i;
467 	unsigned int local_layer;
468 
469 	/*
470 	 * TODO: instead of updating the registers here, we should prepare
471 	 * working registers in atomic_commit and let the hardware command
472 	 * queue update module registers on vblank.
473 	 */
474 	if (state->pending_config) {
475 		mtk_ddp_comp_config(comp, state->pending_width,
476 				    state->pending_height,
477 				    state->pending_vrefresh, 0,
478 				    cmdq_handle);
479 
480 		if (!cmdq_handle)
481 			state->pending_config = false;
482 	}
483 
484 	if (mtk_crtc->pending_planes) {
485 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
486 			struct drm_plane *plane = &mtk_crtc->planes[i];
487 			struct mtk_plane_state *plane_state;
488 
489 			plane_state = to_mtk_plane_state(plane->state);
490 
491 			if (!plane_state->pending.config)
492 				continue;
493 
494 			comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
495 							  &local_layer);
496 
497 			if (comp)
498 				mtk_ddp_comp_layer_config(comp, local_layer,
499 							  plane_state,
500 							  cmdq_handle);
501 			if (!cmdq_handle)
502 				plane_state->pending.config = false;
503 		}
504 
505 		if (!cmdq_handle)
506 			mtk_crtc->pending_planes = false;
507 	}
508 
509 	if (mtk_crtc->pending_async_planes) {
510 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
511 			struct drm_plane *plane = &mtk_crtc->planes[i];
512 			struct mtk_plane_state *plane_state;
513 
514 			plane_state = to_mtk_plane_state(plane->state);
515 
516 			if (!plane_state->pending.async_config)
517 				continue;
518 
519 			comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
520 							  &local_layer);
521 
522 			if (comp)
523 				mtk_ddp_comp_layer_config(comp, local_layer,
524 							  plane_state,
525 							  cmdq_handle);
526 			if (!cmdq_handle)
527 				plane_state->pending.async_config = false;
528 		}
529 
530 		if (!cmdq_handle)
531 			mtk_crtc->pending_async_planes = false;
532 	}
533 }
534 
535 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
536 				       bool needs_vblank)
537 {
538 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
539 	struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
540 #endif
541 	struct drm_crtc *crtc = &mtk_crtc->base;
542 	struct mtk_drm_private *priv = crtc->dev->dev_private;
543 	unsigned int pending_planes = 0, pending_async_planes = 0;
544 	int i;
545 
546 	mutex_lock(&mtk_crtc->hw_lock);
547 	mtk_crtc->config_updating = true;
548 	if (needs_vblank)
549 		mtk_crtc->pending_needs_vblank = true;
550 
551 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
552 		struct drm_plane *plane = &mtk_crtc->planes[i];
553 		struct mtk_plane_state *plane_state;
554 
555 		plane_state = to_mtk_plane_state(plane->state);
556 		if (plane_state->pending.dirty) {
557 			plane_state->pending.config = true;
558 			plane_state->pending.dirty = false;
559 			pending_planes |= BIT(i);
560 		} else if (plane_state->pending.async_dirty) {
561 			plane_state->pending.async_config = true;
562 			plane_state->pending.async_dirty = false;
563 			pending_async_planes |= BIT(i);
564 		}
565 	}
566 	if (pending_planes)
567 		mtk_crtc->pending_planes = true;
568 	if (pending_async_planes)
569 		mtk_crtc->pending_async_planes = true;
570 
571 	if (priv->data->shadow_register) {
572 		mtk_mutex_acquire(mtk_crtc->mutex);
573 		mtk_crtc_ddp_config(crtc, NULL);
574 		mtk_mutex_release(mtk_crtc->mutex);
575 	}
576 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
577 	if (mtk_crtc->cmdq_client.chan) {
578 		mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
579 		cmdq_handle->cmd_buf_size = 0;
580 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
581 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
582 		mtk_crtc_ddp_config(crtc, cmdq_handle);
583 		cmdq_pkt_finalize(cmdq_handle);
584 		dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
585 					   cmdq_handle->pa_base,
586 					   cmdq_handle->cmd_buf_size,
587 					   DMA_TO_DEVICE);
588 		/*
589 		 * CMDQ command should execute in next 3 vblank.
590 		 * One vblank interrupt before send message (occasionally)
591 		 * and one vblank interrupt after cmdq done,
592 		 * so it's timeout after 3 vblank interrupt.
593 		 * If it fail to execute in next 3 vblank, timeout happen.
594 		 */
595 		mtk_crtc->cmdq_vblank_cnt = 3;
596 
597 		mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
598 		mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
599 	}
600 #endif
601 	mtk_crtc->config_updating = false;
602 	mutex_unlock(&mtk_crtc->hw_lock);
603 }
604 
605 static void mtk_crtc_ddp_irq(void *data)
606 {
607 	struct drm_crtc *crtc = data;
608 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
609 	struct mtk_drm_private *priv = crtc->dev->dev_private;
610 
611 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
612 	if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
613 		mtk_crtc_ddp_config(crtc, NULL);
614 	else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
615 		DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
616 			  drm_crtc_index(&mtk_crtc->base));
617 #else
618 	if (!priv->data->shadow_register)
619 		mtk_crtc_ddp_config(crtc, NULL);
620 #endif
621 	mtk_drm_finish_page_flip(mtk_crtc);
622 }
623 
624 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
625 {
626 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
627 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
628 
629 	mtk_ddp_comp_enable_vblank(comp);
630 
631 	return 0;
632 }
633 
634 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
635 {
636 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
637 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
638 
639 	mtk_ddp_comp_disable_vblank(comp);
640 }
641 
642 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
643 			     struct mtk_plane_state *state)
644 {
645 	unsigned int local_layer;
646 	struct mtk_ddp_comp *comp;
647 
648 	comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
649 	if (comp)
650 		return mtk_ddp_comp_layer_check(comp, local_layer, state);
651 	return 0;
652 }
653 
654 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
655 			       struct drm_atomic_state *state)
656 {
657 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
658 
659 	if (!mtk_crtc->enabled)
660 		return;
661 
662 	mtk_drm_crtc_update_config(mtk_crtc, false);
663 }
664 
665 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
666 				       struct drm_atomic_state *state)
667 {
668 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
669 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
670 	int ret;
671 
672 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
673 
674 	ret = pm_runtime_resume_and_get(comp->dev);
675 	if (ret < 0) {
676 		DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
677 		return;
678 	}
679 
680 	ret = mtk_crtc_ddp_hw_init(mtk_crtc);
681 	if (ret) {
682 		pm_runtime_put(comp->dev);
683 		return;
684 	}
685 
686 	drm_crtc_vblank_on(crtc);
687 	mtk_crtc->enabled = true;
688 }
689 
690 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
691 					struct drm_atomic_state *state)
692 {
693 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
694 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
695 	int i, ret;
696 
697 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
698 	if (!mtk_crtc->enabled)
699 		return;
700 
701 	/* Set all pending plane state to disabled */
702 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
703 		struct drm_plane *plane = &mtk_crtc->planes[i];
704 		struct mtk_plane_state *plane_state;
705 
706 		plane_state = to_mtk_plane_state(plane->state);
707 		plane_state->pending.enable = false;
708 		plane_state->pending.config = true;
709 	}
710 	mtk_crtc->pending_planes = true;
711 
712 	mtk_drm_crtc_update_config(mtk_crtc, false);
713 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
714 	/* Wait for planes to be disabled by cmdq */
715 	if (mtk_crtc->cmdq_client.chan)
716 		wait_event_timeout(mtk_crtc->cb_blocking_queue,
717 				   mtk_crtc->cmdq_vblank_cnt == 0,
718 				   msecs_to_jiffies(500));
719 #endif
720 	/* Wait for planes to be disabled */
721 	drm_crtc_wait_one_vblank(crtc);
722 
723 	drm_crtc_vblank_off(crtc);
724 	mtk_crtc_ddp_hw_fini(mtk_crtc);
725 	ret = pm_runtime_put(comp->dev);
726 	if (ret < 0)
727 		DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret);
728 
729 	mtk_crtc->enabled = false;
730 }
731 
732 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
733 				      struct drm_atomic_state *state)
734 {
735 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
736 									  crtc);
737 	struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
738 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
739 
740 	if (mtk_crtc->event && mtk_crtc_state->base.event)
741 		DRM_ERROR("new event while there is still a pending event\n");
742 
743 	if (mtk_crtc_state->base.event) {
744 		mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
745 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
746 		mtk_crtc->event = mtk_crtc_state->base.event;
747 		mtk_crtc_state->base.event = NULL;
748 	}
749 }
750 
751 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
752 				      struct drm_atomic_state *state)
753 {
754 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
755 	int i;
756 
757 	if (crtc->state->color_mgmt_changed)
758 		for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
759 			mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
760 			mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
761 		}
762 	mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
763 }
764 
765 static const struct drm_crtc_funcs mtk_crtc_funcs = {
766 	.set_config		= drm_atomic_helper_set_config,
767 	.page_flip		= drm_atomic_helper_page_flip,
768 	.destroy		= mtk_drm_crtc_destroy,
769 	.reset			= mtk_drm_crtc_reset,
770 	.atomic_duplicate_state	= mtk_drm_crtc_duplicate_state,
771 	.atomic_destroy_state	= mtk_drm_crtc_destroy_state,
772 	.enable_vblank		= mtk_drm_crtc_enable_vblank,
773 	.disable_vblank		= mtk_drm_crtc_disable_vblank,
774 };
775 
776 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
777 	.mode_fixup	= mtk_drm_crtc_mode_fixup,
778 	.mode_set_nofb	= mtk_drm_crtc_mode_set_nofb,
779 	.atomic_begin	= mtk_drm_crtc_atomic_begin,
780 	.atomic_flush	= mtk_drm_crtc_atomic_flush,
781 	.atomic_enable	= mtk_drm_crtc_atomic_enable,
782 	.atomic_disable	= mtk_drm_crtc_atomic_disable,
783 };
784 
785 static int mtk_drm_crtc_init(struct drm_device *drm,
786 			     struct mtk_drm_crtc *mtk_crtc,
787 			     unsigned int pipe)
788 {
789 	struct drm_plane *primary = NULL;
790 	struct drm_plane *cursor = NULL;
791 	int i, ret;
792 
793 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
794 		if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
795 			primary = &mtk_crtc->planes[i];
796 		else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
797 			cursor = &mtk_crtc->planes[i];
798 	}
799 
800 	ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
801 					&mtk_crtc_funcs, NULL);
802 	if (ret)
803 		goto err_cleanup_crtc;
804 
805 	drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
806 
807 	return 0;
808 
809 err_cleanup_crtc:
810 	drm_crtc_cleanup(&mtk_crtc->base);
811 	return ret;
812 }
813 
814 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
815 					int comp_idx)
816 {
817 	struct mtk_ddp_comp *comp;
818 
819 	if (comp_idx > 1)
820 		return 0;
821 
822 	comp = mtk_crtc->ddp_comp[comp_idx];
823 	if (!comp->funcs)
824 		return 0;
825 
826 	if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
827 		return 0;
828 
829 	return mtk_ddp_comp_layer_nr(comp);
830 }
831 
832 static inline
833 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
834 					    unsigned int num_planes)
835 {
836 	if (plane_idx == 0)
837 		return DRM_PLANE_TYPE_PRIMARY;
838 	else if (plane_idx == (num_planes - 1))
839 		return DRM_PLANE_TYPE_CURSOR;
840 	else
841 		return DRM_PLANE_TYPE_OVERLAY;
842 
843 }
844 
845 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
846 					 struct mtk_drm_crtc *mtk_crtc,
847 					 int comp_idx, int pipe)
848 {
849 	int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
850 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
851 	int i, ret;
852 
853 	for (i = 0; i < num_planes; i++) {
854 		ret = mtk_plane_init(drm_dev,
855 				&mtk_crtc->planes[mtk_crtc->layer_nr],
856 				BIT(pipe),
857 				mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
858 							num_planes),
859 				mtk_ddp_comp_supported_rotations(comp));
860 		if (ret)
861 			return ret;
862 
863 		mtk_crtc->layer_nr++;
864 	}
865 	return 0;
866 }
867 
868 int mtk_drm_crtc_create(struct drm_device *drm_dev,
869 			const enum mtk_ddp_comp_id *path, unsigned int path_len)
870 {
871 	struct mtk_drm_private *priv = drm_dev->dev_private;
872 	struct device *dev = drm_dev->dev;
873 	struct mtk_drm_crtc *mtk_crtc;
874 	unsigned int num_comp_planes = 0;
875 	int pipe = priv->num_pipes;
876 	int ret;
877 	int i;
878 	bool has_ctm = false;
879 	uint gamma_lut_size = 0;
880 
881 	if (!path)
882 		return 0;
883 
884 	for (i = 0; i < path_len; i++) {
885 		enum mtk_ddp_comp_id comp_id = path[i];
886 		struct device_node *node;
887 		struct mtk_ddp_comp *comp;
888 
889 		node = priv->comp_node[comp_id];
890 		comp = &priv->ddp_comp[comp_id];
891 
892 		if (!node) {
893 			dev_info(dev,
894 				 "Not creating crtc %d because component %d is disabled or missing\n",
895 				 pipe, comp_id);
896 			return 0;
897 		}
898 
899 		if (!comp->dev) {
900 			dev_err(dev, "Component %pOF not initialized\n", node);
901 			return -ENODEV;
902 		}
903 	}
904 
905 	mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
906 	if (!mtk_crtc)
907 		return -ENOMEM;
908 
909 	mtk_crtc->mmsys_dev = priv->mmsys_dev;
910 	mtk_crtc->ddp_comp_nr = path_len;
911 	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
912 						sizeof(*mtk_crtc->ddp_comp),
913 						GFP_KERNEL);
914 	if (!mtk_crtc->ddp_comp)
915 		return -ENOMEM;
916 
917 	mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
918 	if (IS_ERR(mtk_crtc->mutex)) {
919 		ret = PTR_ERR(mtk_crtc->mutex);
920 		dev_err(dev, "Failed to get mutex: %d\n", ret);
921 		return ret;
922 	}
923 
924 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
925 		enum mtk_ddp_comp_id comp_id = path[i];
926 		struct mtk_ddp_comp *comp;
927 
928 		comp = &priv->ddp_comp[comp_id];
929 		mtk_crtc->ddp_comp[i] = comp;
930 
931 		if (comp->funcs) {
932 			if (comp->funcs->gamma_set)
933 				gamma_lut_size = MTK_LUT_SIZE;
934 
935 			if (comp->funcs->ctm_set)
936 				has_ctm = true;
937 		}
938 
939 		mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq,
940 						&mtk_crtc->base);
941 	}
942 
943 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
944 		num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
945 
946 	mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
947 					sizeof(struct drm_plane), GFP_KERNEL);
948 
949 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
950 		ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
951 						    pipe);
952 		if (ret)
953 			return ret;
954 	}
955 
956 	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
957 	if (ret < 0)
958 		return ret;
959 
960 	if (gamma_lut_size)
961 		drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
962 	drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
963 	priv->num_pipes++;
964 	mutex_init(&mtk_crtc->hw_lock);
965 
966 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
967 	mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
968 	mtk_crtc->cmdq_client.client.tx_block = false;
969 	mtk_crtc->cmdq_client.client.knows_txdone = true;
970 	mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
971 	mtk_crtc->cmdq_client.chan =
972 			mbox_request_channel(&mtk_crtc->cmdq_client.client,
973 					     drm_crtc_index(&mtk_crtc->base));
974 	if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
975 		dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
976 			drm_crtc_index(&mtk_crtc->base));
977 		mtk_crtc->cmdq_client.chan = NULL;
978 	}
979 
980 	if (mtk_crtc->cmdq_client.chan) {
981 		ret = of_property_read_u32_index(priv->mutex_node,
982 						 "mediatek,gce-events",
983 						 drm_crtc_index(&mtk_crtc->base),
984 						 &mtk_crtc->cmdq_event);
985 		if (ret) {
986 			dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
987 				drm_crtc_index(&mtk_crtc->base));
988 			mbox_free_channel(mtk_crtc->cmdq_client.chan);
989 			mtk_crtc->cmdq_client.chan = NULL;
990 		} else {
991 			ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client,
992 						      &mtk_crtc->cmdq_handle,
993 						      PAGE_SIZE);
994 			if (ret) {
995 				dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
996 					drm_crtc_index(&mtk_crtc->base));
997 				mbox_free_channel(mtk_crtc->cmdq_client.chan);
998 				mtk_crtc->cmdq_client.chan = NULL;
999 			}
1000 		}
1001 
1002 		/* for sending blocking cmd in crtc disable */
1003 		init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
1004 	}
1005 #endif
1006 	return 0;
1007 }
1008