1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <asm/barrier.h> 15 #include <drm/drmP.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_crtc_helper.h> 18 #include <drm/drm_plane_helper.h> 19 #include <linux/clk.h> 20 #include <linux/pm_runtime.h> 21 #include <soc/mediatek/smi.h> 22 23 #include "mtk_drm_drv.h" 24 #include "mtk_drm_crtc.h" 25 #include "mtk_drm_ddp.h" 26 #include "mtk_drm_ddp_comp.h" 27 #include "mtk_drm_gem.h" 28 #include "mtk_drm_plane.h" 29 30 /** 31 * struct mtk_drm_crtc - MediaTek specific crtc structure. 32 * @base: crtc object. 33 * @enabled: records whether crtc_enable succeeded 34 * @planes: array of 4 drm_plane structures, one for each overlay plane 35 * @pending_planes: whether any plane has pending changes to be applied 36 * @config_regs: memory mapped mmsys configuration register space 37 * @mutex: handle to one of the ten disp_mutex streams 38 * @ddp_comp_nr: number of components in ddp_comp 39 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 40 */ 41 struct mtk_drm_crtc { 42 struct drm_crtc base; 43 bool enabled; 44 45 bool pending_needs_vblank; 46 struct drm_pending_vblank_event *event; 47 48 struct drm_plane planes[OVL_LAYER_NR]; 49 bool pending_planes; 50 51 void __iomem *config_regs; 52 struct mtk_disp_mutex *mutex; 53 unsigned int ddp_comp_nr; 54 struct mtk_ddp_comp **ddp_comp; 55 }; 56 57 struct mtk_crtc_state { 58 struct drm_crtc_state base; 59 60 bool pending_config; 61 unsigned int pending_width; 62 unsigned int pending_height; 63 unsigned int pending_vrefresh; 64 }; 65 66 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 67 { 68 return container_of(c, struct mtk_drm_crtc, base); 69 } 70 71 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 72 { 73 return container_of(s, struct mtk_crtc_state, base); 74 } 75 76 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 77 { 78 struct drm_crtc *crtc = &mtk_crtc->base; 79 unsigned long flags; 80 81 spin_lock_irqsave(&crtc->dev->event_lock, flags); 82 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 83 drm_crtc_vblank_put(crtc); 84 mtk_crtc->event = NULL; 85 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 86 } 87 88 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 89 { 90 drm_crtc_handle_vblank(&mtk_crtc->base); 91 if (mtk_crtc->pending_needs_vblank) { 92 mtk_drm_crtc_finish_page_flip(mtk_crtc); 93 mtk_crtc->pending_needs_vblank = false; 94 } 95 } 96 97 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 98 { 99 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 100 int i; 101 102 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 103 clk_unprepare(mtk_crtc->ddp_comp[i]->clk); 104 105 mtk_disp_mutex_put(mtk_crtc->mutex); 106 107 drm_crtc_cleanup(crtc); 108 } 109 110 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 111 { 112 struct mtk_crtc_state *state; 113 114 if (crtc->state) { 115 __drm_atomic_helper_crtc_destroy_state(crtc->state); 116 117 state = to_mtk_crtc_state(crtc->state); 118 memset(state, 0, sizeof(*state)); 119 } else { 120 state = kzalloc(sizeof(*state), GFP_KERNEL); 121 if (!state) 122 return; 123 crtc->state = &state->base; 124 } 125 126 state->base.crtc = crtc; 127 } 128 129 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 130 { 131 struct mtk_crtc_state *state; 132 133 state = kzalloc(sizeof(*state), GFP_KERNEL); 134 if (!state) 135 return NULL; 136 137 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 138 139 WARN_ON(state->base.crtc != crtc); 140 state->base.crtc = crtc; 141 142 return &state->base; 143 } 144 145 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 146 struct drm_crtc_state *state) 147 { 148 __drm_atomic_helper_crtc_destroy_state(state); 149 kfree(to_mtk_crtc_state(state)); 150 } 151 152 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 153 const struct drm_display_mode *mode, 154 struct drm_display_mode *adjusted_mode) 155 { 156 /* Nothing to do here, but this callback is mandatory. */ 157 return true; 158 } 159 160 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 161 { 162 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 163 164 state->pending_width = crtc->mode.hdisplay; 165 state->pending_height = crtc->mode.vdisplay; 166 state->pending_vrefresh = crtc->mode.vrefresh; 167 wmb(); /* Make sure the above parameters are set before update */ 168 state->pending_config = true; 169 } 170 171 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 172 { 173 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 174 struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 175 176 mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base); 177 178 return 0; 179 } 180 181 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 182 { 183 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 184 struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 185 186 mtk_ddp_comp_disable_vblank(ovl); 187 } 188 189 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 190 { 191 int ret; 192 int i; 193 194 DRM_DEBUG_DRIVER("%s\n", __func__); 195 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 196 ret = clk_enable(mtk_crtc->ddp_comp[i]->clk); 197 if (ret) { 198 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 199 goto err; 200 } 201 } 202 203 return 0; 204 err: 205 while (--i >= 0) 206 clk_disable(mtk_crtc->ddp_comp[i]->clk); 207 return ret; 208 } 209 210 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 211 { 212 int i; 213 214 DRM_DEBUG_DRIVER("%s\n", __func__); 215 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 216 clk_disable(mtk_crtc->ddp_comp[i]->clk); 217 } 218 219 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 220 { 221 struct drm_crtc *crtc = &mtk_crtc->base; 222 struct drm_connector *connector; 223 struct drm_encoder *encoder; 224 struct drm_connector_list_iter conn_iter; 225 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 226 int ret; 227 int i; 228 229 DRM_DEBUG_DRIVER("%s\n", __func__); 230 if (WARN_ON(!crtc->state)) 231 return -EINVAL; 232 233 width = crtc->state->adjusted_mode.hdisplay; 234 height = crtc->state->adjusted_mode.vdisplay; 235 vrefresh = crtc->state->adjusted_mode.vrefresh; 236 237 drm_for_each_encoder(encoder, crtc->dev) { 238 if (encoder->crtc != crtc) 239 continue; 240 241 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 242 drm_for_each_connector_iter(connector, &conn_iter) { 243 if (connector->encoder != encoder) 244 continue; 245 if (connector->display_info.bpc != 0 && 246 bpc > connector->display_info.bpc) 247 bpc = connector->display_info.bpc; 248 } 249 drm_connector_list_iter_end(&conn_iter); 250 } 251 252 ret = pm_runtime_get_sync(crtc->dev->dev); 253 if (ret < 0) { 254 DRM_ERROR("Failed to enable power domain: %d\n", ret); 255 return ret; 256 } 257 258 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 259 if (ret < 0) { 260 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 261 goto err_pm_runtime_put; 262 } 263 264 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 265 if (ret < 0) { 266 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 267 goto err_mutex_unprepare; 268 } 269 270 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 271 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 272 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 273 mtk_crtc->ddp_comp[i]->id, 274 mtk_crtc->ddp_comp[i + 1]->id); 275 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 276 mtk_crtc->ddp_comp[i]->id); 277 } 278 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 279 mtk_disp_mutex_enable(mtk_crtc->mutex); 280 281 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 282 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 283 284 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); 285 mtk_ddp_comp_start(comp); 286 } 287 288 /* Initially configure all planes */ 289 for (i = 0; i < OVL_LAYER_NR; i++) { 290 struct drm_plane *plane = &mtk_crtc->planes[i]; 291 struct mtk_plane_state *plane_state; 292 293 plane_state = to_mtk_plane_state(plane->state); 294 mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i, 295 plane_state); 296 } 297 298 return 0; 299 300 err_mutex_unprepare: 301 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 302 err_pm_runtime_put: 303 pm_runtime_put(crtc->dev->dev); 304 return ret; 305 } 306 307 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 308 { 309 struct drm_device *drm = mtk_crtc->base.dev; 310 int i; 311 312 DRM_DEBUG_DRIVER("%s\n", __func__); 313 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 314 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 315 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 316 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 317 mtk_crtc->ddp_comp[i]->id); 318 mtk_disp_mutex_disable(mtk_crtc->mutex); 319 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 320 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 321 mtk_crtc->ddp_comp[i]->id, 322 mtk_crtc->ddp_comp[i + 1]->id); 323 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 324 mtk_crtc->ddp_comp[i]->id); 325 } 326 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 327 mtk_crtc_ddp_clk_disable(mtk_crtc); 328 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 329 330 pm_runtime_put(drm->dev); 331 } 332 333 static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 334 { 335 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 336 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 337 struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 338 unsigned int i; 339 340 /* 341 * TODO: instead of updating the registers here, we should prepare 342 * working registers in atomic_commit and let the hardware command 343 * queue update module registers on vblank. 344 */ 345 if (state->pending_config) { 346 mtk_ddp_comp_config(ovl, state->pending_width, 347 state->pending_height, 348 state->pending_vrefresh, 0); 349 350 state->pending_config = false; 351 } 352 353 if (mtk_crtc->pending_planes) { 354 for (i = 0; i < OVL_LAYER_NR; i++) { 355 struct drm_plane *plane = &mtk_crtc->planes[i]; 356 struct mtk_plane_state *plane_state; 357 358 plane_state = to_mtk_plane_state(plane->state); 359 360 if (plane_state->pending.config) { 361 mtk_ddp_comp_layer_config(ovl, i, plane_state); 362 plane_state->pending.config = false; 363 } 364 } 365 mtk_crtc->pending_planes = false; 366 } 367 } 368 369 static void mtk_drm_crtc_enable(struct drm_crtc *crtc) 370 { 371 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 372 struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 373 int ret; 374 375 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 376 377 ret = mtk_smi_larb_get(ovl->larb_dev); 378 if (ret) { 379 DRM_ERROR("Failed to get larb: %d\n", ret); 380 return; 381 } 382 383 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 384 if (ret) { 385 mtk_smi_larb_put(ovl->larb_dev); 386 return; 387 } 388 389 drm_crtc_vblank_on(crtc); 390 mtk_crtc->enabled = true; 391 } 392 393 static void mtk_drm_crtc_disable(struct drm_crtc *crtc) 394 { 395 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 396 struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0]; 397 int i; 398 399 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 400 if (!mtk_crtc->enabled) 401 return; 402 403 /* Set all pending plane state to disabled */ 404 for (i = 0; i < OVL_LAYER_NR; i++) { 405 struct drm_plane *plane = &mtk_crtc->planes[i]; 406 struct mtk_plane_state *plane_state; 407 408 plane_state = to_mtk_plane_state(plane->state); 409 plane_state->pending.enable = false; 410 plane_state->pending.config = true; 411 } 412 mtk_crtc->pending_planes = true; 413 414 /* Wait for planes to be disabled */ 415 drm_crtc_wait_one_vblank(crtc); 416 417 drm_crtc_vblank_off(crtc); 418 mtk_crtc_ddp_hw_fini(mtk_crtc); 419 mtk_smi_larb_put(ovl->larb_dev); 420 421 mtk_crtc->enabled = false; 422 } 423 424 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 425 struct drm_crtc_state *old_crtc_state) 426 { 427 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 428 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 429 430 if (mtk_crtc->event && state->base.event) 431 DRM_ERROR("new event while there is still a pending event\n"); 432 433 if (state->base.event) { 434 state->base.event->pipe = drm_crtc_index(crtc); 435 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 436 mtk_crtc->event = state->base.event; 437 state->base.event = NULL; 438 } 439 } 440 441 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 442 struct drm_crtc_state *old_crtc_state) 443 { 444 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 445 struct mtk_drm_private *priv = crtc->dev->dev_private; 446 unsigned int pending_planes = 0; 447 int i; 448 449 if (mtk_crtc->event) 450 mtk_crtc->pending_needs_vblank = true; 451 for (i = 0; i < OVL_LAYER_NR; i++) { 452 struct drm_plane *plane = &mtk_crtc->planes[i]; 453 struct mtk_plane_state *plane_state; 454 455 plane_state = to_mtk_plane_state(plane->state); 456 if (plane_state->pending.dirty) { 457 plane_state->pending.config = true; 458 plane_state->pending.dirty = false; 459 pending_planes |= BIT(i); 460 } 461 } 462 if (pending_planes) 463 mtk_crtc->pending_planes = true; 464 if (crtc->state->color_mgmt_changed) 465 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 466 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 467 468 if (priv->data->shadow_register) { 469 mtk_disp_mutex_acquire(mtk_crtc->mutex); 470 mtk_crtc_ddp_config(crtc); 471 mtk_disp_mutex_release(mtk_crtc->mutex); 472 } 473 } 474 475 static const struct drm_crtc_funcs mtk_crtc_funcs = { 476 .set_config = drm_atomic_helper_set_config, 477 .page_flip = drm_atomic_helper_page_flip, 478 .destroy = mtk_drm_crtc_destroy, 479 .reset = mtk_drm_crtc_reset, 480 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 481 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 482 .gamma_set = drm_atomic_helper_legacy_gamma_set, 483 .enable_vblank = mtk_drm_crtc_enable_vblank, 484 .disable_vblank = mtk_drm_crtc_disable_vblank, 485 }; 486 487 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 488 .mode_fixup = mtk_drm_crtc_mode_fixup, 489 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 490 .enable = mtk_drm_crtc_enable, 491 .disable = mtk_drm_crtc_disable, 492 .atomic_begin = mtk_drm_crtc_atomic_begin, 493 .atomic_flush = mtk_drm_crtc_atomic_flush, 494 }; 495 496 static int mtk_drm_crtc_init(struct drm_device *drm, 497 struct mtk_drm_crtc *mtk_crtc, 498 struct drm_plane *primary, 499 struct drm_plane *cursor, unsigned int pipe) 500 { 501 int ret; 502 503 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 504 &mtk_crtc_funcs, NULL); 505 if (ret) 506 goto err_cleanup_crtc; 507 508 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 509 510 return 0; 511 512 err_cleanup_crtc: 513 drm_crtc_cleanup(&mtk_crtc->base); 514 return ret; 515 } 516 517 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl) 518 { 519 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 520 struct mtk_drm_private *priv = crtc->dev->dev_private; 521 522 if (!priv->data->shadow_register) 523 mtk_crtc_ddp_config(crtc); 524 525 mtk_drm_finish_page_flip(mtk_crtc); 526 } 527 528 int mtk_drm_crtc_create(struct drm_device *drm_dev, 529 const enum mtk_ddp_comp_id *path, unsigned int path_len) 530 { 531 struct mtk_drm_private *priv = drm_dev->dev_private; 532 struct device *dev = drm_dev->dev; 533 struct mtk_drm_crtc *mtk_crtc; 534 enum drm_plane_type type; 535 unsigned int zpos; 536 int pipe = priv->num_pipes; 537 int ret; 538 int i; 539 540 for (i = 0; i < path_len; i++) { 541 enum mtk_ddp_comp_id comp_id = path[i]; 542 struct device_node *node; 543 544 node = priv->comp_node[comp_id]; 545 if (!node) { 546 dev_info(dev, 547 "Not creating crtc %d because component %d is disabled or missing\n", 548 pipe, comp_id); 549 return 0; 550 } 551 } 552 553 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 554 if (!mtk_crtc) 555 return -ENOMEM; 556 557 mtk_crtc->config_regs = priv->config_regs; 558 mtk_crtc->ddp_comp_nr = path_len; 559 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 560 sizeof(*mtk_crtc->ddp_comp), 561 GFP_KERNEL); 562 if (!mtk_crtc->ddp_comp) 563 return -ENOMEM; 564 565 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 566 if (IS_ERR(mtk_crtc->mutex)) { 567 ret = PTR_ERR(mtk_crtc->mutex); 568 dev_err(dev, "Failed to get mutex: %d\n", ret); 569 return ret; 570 } 571 572 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 573 enum mtk_ddp_comp_id comp_id = path[i]; 574 struct mtk_ddp_comp *comp; 575 struct device_node *node; 576 577 node = priv->comp_node[comp_id]; 578 comp = priv->ddp_comp[comp_id]; 579 if (!comp) { 580 dev_err(dev, "Component %s not initialized\n", 581 node->full_name); 582 ret = -ENODEV; 583 goto unprepare; 584 } 585 586 ret = clk_prepare(comp->clk); 587 if (ret) { 588 dev_err(dev, 589 "Failed to prepare clock for component %s: %d\n", 590 node->full_name, ret); 591 goto unprepare; 592 } 593 594 mtk_crtc->ddp_comp[i] = comp; 595 } 596 597 for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) { 598 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY : 599 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR : 600 DRM_PLANE_TYPE_OVERLAY; 601 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos], 602 BIT(pipe), type); 603 if (ret) 604 goto unprepare; 605 } 606 607 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 608 &mtk_crtc->planes[1], pipe); 609 if (ret < 0) 610 goto unprepare; 611 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); 612 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); 613 priv->num_pipes++; 614 615 return 0; 616 617 unprepare: 618 while (--i >= 0) 619 clk_unprepare(mtk_crtc->ddp_comp[i]->clk); 620 621 return ret; 622 } 623