1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 #include <linux/soc/mediatek/mtk-cmdq.h> 9 #include <linux/soc/mediatek/mtk-mmsys.h> 10 11 #include <asm/barrier.h> 12 #include <soc/mediatek/smi.h> 13 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_plane_helper.h> 17 #include <drm/drm_probe_helper.h> 18 #include <drm/drm_vblank.h> 19 20 #include "mtk_drm_drv.h" 21 #include "mtk_drm_crtc.h" 22 #include "mtk_drm_ddp.h" 23 #include "mtk_drm_ddp_comp.h" 24 #include "mtk_drm_gem.h" 25 #include "mtk_drm_plane.h" 26 27 /* 28 * struct mtk_drm_crtc - MediaTek specific crtc structure. 29 * @base: crtc object. 30 * @enabled: records whether crtc_enable succeeded 31 * @planes: array of 4 drm_plane structures, one for each overlay plane 32 * @pending_planes: whether any plane has pending changes to be applied 33 * @mmsys_dev: pointer to the mmsys device for configuration registers 34 * @mutex: handle to one of the ten disp_mutex streams 35 * @ddp_comp_nr: number of components in ddp_comp 36 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 37 * 38 * TODO: Needs update: this header is missing a bunch of member descriptions. 39 */ 40 struct mtk_drm_crtc { 41 struct drm_crtc base; 42 bool enabled; 43 44 bool pending_needs_vblank; 45 struct drm_pending_vblank_event *event; 46 47 struct drm_plane *planes; 48 unsigned int layer_nr; 49 bool pending_planes; 50 bool pending_async_planes; 51 52 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 53 struct cmdq_client *cmdq_client; 54 u32 cmdq_event; 55 #endif 56 57 struct device *mmsys_dev; 58 struct mtk_disp_mutex *mutex; 59 unsigned int ddp_comp_nr; 60 struct mtk_ddp_comp **ddp_comp; 61 62 /* lock for display hardware access */ 63 struct mutex hw_lock; 64 }; 65 66 struct mtk_crtc_state { 67 struct drm_crtc_state base; 68 69 bool pending_config; 70 unsigned int pending_width; 71 unsigned int pending_height; 72 unsigned int pending_vrefresh; 73 }; 74 75 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 76 { 77 return container_of(c, struct mtk_drm_crtc, base); 78 } 79 80 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 81 { 82 return container_of(s, struct mtk_crtc_state, base); 83 } 84 85 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 86 { 87 struct drm_crtc *crtc = &mtk_crtc->base; 88 unsigned long flags; 89 90 spin_lock_irqsave(&crtc->dev->event_lock, flags); 91 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 92 drm_crtc_vblank_put(crtc); 93 mtk_crtc->event = NULL; 94 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 95 } 96 97 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 98 { 99 drm_crtc_handle_vblank(&mtk_crtc->base); 100 if (mtk_crtc->pending_needs_vblank) { 101 mtk_drm_crtc_finish_page_flip(mtk_crtc); 102 mtk_crtc->pending_needs_vblank = false; 103 } 104 } 105 106 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 107 { 108 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 109 110 mtk_disp_mutex_put(mtk_crtc->mutex); 111 112 drm_crtc_cleanup(crtc); 113 } 114 115 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 116 { 117 struct mtk_crtc_state *state; 118 119 if (crtc->state) 120 __drm_atomic_helper_crtc_destroy_state(crtc->state); 121 122 kfree(to_mtk_crtc_state(crtc->state)); 123 crtc->state = NULL; 124 125 state = kzalloc(sizeof(*state), GFP_KERNEL); 126 if (state) 127 __drm_atomic_helper_crtc_reset(crtc, &state->base); 128 } 129 130 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 131 { 132 struct mtk_crtc_state *state; 133 134 state = kzalloc(sizeof(*state), GFP_KERNEL); 135 if (!state) 136 return NULL; 137 138 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 139 140 WARN_ON(state->base.crtc != crtc); 141 state->base.crtc = crtc; 142 143 return &state->base; 144 } 145 146 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 147 struct drm_crtc_state *state) 148 { 149 __drm_atomic_helper_crtc_destroy_state(state); 150 kfree(to_mtk_crtc_state(state)); 151 } 152 153 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 154 const struct drm_display_mode *mode, 155 struct drm_display_mode *adjusted_mode) 156 { 157 /* Nothing to do here, but this callback is mandatory. */ 158 return true; 159 } 160 161 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 162 { 163 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 164 165 state->pending_width = crtc->mode.hdisplay; 166 state->pending_height = crtc->mode.vdisplay; 167 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 168 wmb(); /* Make sure the above parameters are set before update */ 169 state->pending_config = true; 170 } 171 172 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 178 179 return 0; 180 } 181 182 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 183 { 184 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 185 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 186 187 mtk_ddp_comp_disable_vblank(comp); 188 } 189 190 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 191 { 192 int ret; 193 int i; 194 195 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 196 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 197 if (ret) { 198 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 199 goto err; 200 } 201 } 202 203 return 0; 204 err: 205 while (--i >= 0) 206 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 207 return ret; 208 } 209 210 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 211 { 212 int i; 213 214 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 215 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 216 } 217 218 static 219 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 220 struct drm_plane *plane, 221 unsigned int *local_layer) 222 { 223 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 224 struct mtk_ddp_comp *comp; 225 int i, count = 0; 226 unsigned int local_index = plane - mtk_crtc->planes; 227 228 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 229 comp = mtk_crtc->ddp_comp[i]; 230 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 231 *local_layer = local_index - count; 232 return comp; 233 } 234 count += mtk_ddp_comp_layer_nr(comp); 235 } 236 237 WARN(1, "Failed to find component for plane %d\n", plane->index); 238 return NULL; 239 } 240 241 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 242 static void ddp_cmdq_cb(struct cmdq_cb_data data) 243 { 244 cmdq_pkt_destroy(data.data); 245 } 246 #endif 247 248 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 249 { 250 struct drm_crtc *crtc = &mtk_crtc->base; 251 struct drm_connector *connector; 252 struct drm_encoder *encoder; 253 struct drm_connector_list_iter conn_iter; 254 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 255 int ret; 256 int i; 257 258 if (WARN_ON(!crtc->state)) 259 return -EINVAL; 260 261 width = crtc->state->adjusted_mode.hdisplay; 262 height = crtc->state->adjusted_mode.vdisplay; 263 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 264 265 drm_for_each_encoder(encoder, crtc->dev) { 266 if (encoder->crtc != crtc) 267 continue; 268 269 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 270 drm_for_each_connector_iter(connector, &conn_iter) { 271 if (connector->encoder != encoder) 272 continue; 273 if (connector->display_info.bpc != 0 && 274 bpc > connector->display_info.bpc) 275 bpc = connector->display_info.bpc; 276 } 277 drm_connector_list_iter_end(&conn_iter); 278 } 279 280 ret = pm_runtime_get_sync(crtc->dev->dev); 281 if (ret < 0) { 282 DRM_ERROR("Failed to enable power domain: %d\n", ret); 283 return ret; 284 } 285 286 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 287 if (ret < 0) { 288 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 289 goto err_pm_runtime_put; 290 } 291 292 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 293 if (ret < 0) { 294 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 295 goto err_mutex_unprepare; 296 } 297 298 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 299 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 300 mtk_crtc->ddp_comp[i]->id, 301 mtk_crtc->ddp_comp[i + 1]->id); 302 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 303 mtk_crtc->ddp_comp[i]->id); 304 } 305 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 306 mtk_disp_mutex_enable(mtk_crtc->mutex); 307 308 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 309 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 310 311 if (i == 1) 312 mtk_ddp_comp_bgclr_in_on(comp); 313 314 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 315 mtk_ddp_comp_start(comp); 316 } 317 318 /* Initially configure all planes */ 319 for (i = 0; i < mtk_crtc->layer_nr; i++) { 320 struct drm_plane *plane = &mtk_crtc->planes[i]; 321 struct mtk_plane_state *plane_state; 322 struct mtk_ddp_comp *comp; 323 unsigned int local_layer; 324 325 plane_state = to_mtk_plane_state(plane->state); 326 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 327 if (comp) 328 mtk_ddp_comp_layer_config(comp, local_layer, 329 plane_state, NULL); 330 } 331 332 return 0; 333 334 err_mutex_unprepare: 335 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 336 err_pm_runtime_put: 337 pm_runtime_put(crtc->dev->dev); 338 return ret; 339 } 340 341 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 342 { 343 struct drm_device *drm = mtk_crtc->base.dev; 344 struct drm_crtc *crtc = &mtk_crtc->base; 345 int i; 346 347 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 348 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 349 if (i == 1) 350 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 351 } 352 353 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 354 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 355 mtk_crtc->ddp_comp[i]->id); 356 mtk_disp_mutex_disable(mtk_crtc->mutex); 357 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 358 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 359 mtk_crtc->ddp_comp[i]->id, 360 mtk_crtc->ddp_comp[i + 1]->id); 361 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 362 mtk_crtc->ddp_comp[i]->id); 363 } 364 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 365 mtk_crtc_ddp_clk_disable(mtk_crtc); 366 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 367 368 pm_runtime_put(drm->dev); 369 370 if (crtc->state->event && !crtc->state->active) { 371 spin_lock_irq(&crtc->dev->event_lock); 372 drm_crtc_send_vblank_event(crtc, crtc->state->event); 373 crtc->state->event = NULL; 374 spin_unlock_irq(&crtc->dev->event_lock); 375 } 376 } 377 378 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 379 struct cmdq_pkt *cmdq_handle) 380 { 381 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 382 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 383 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 384 unsigned int i; 385 unsigned int local_layer; 386 387 /* 388 * TODO: instead of updating the registers here, we should prepare 389 * working registers in atomic_commit and let the hardware command 390 * queue update module registers on vblank. 391 */ 392 if (state->pending_config) { 393 mtk_ddp_comp_config(comp, state->pending_width, 394 state->pending_height, 395 state->pending_vrefresh, 0, 396 cmdq_handle); 397 398 state->pending_config = false; 399 } 400 401 if (mtk_crtc->pending_planes) { 402 for (i = 0; i < mtk_crtc->layer_nr; i++) { 403 struct drm_plane *plane = &mtk_crtc->planes[i]; 404 struct mtk_plane_state *plane_state; 405 406 plane_state = to_mtk_plane_state(plane->state); 407 408 if (!plane_state->pending.config) 409 continue; 410 411 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 412 &local_layer); 413 414 if (comp) 415 mtk_ddp_comp_layer_config(comp, local_layer, 416 plane_state, 417 cmdq_handle); 418 plane_state->pending.config = false; 419 } 420 mtk_crtc->pending_planes = false; 421 } 422 423 if (mtk_crtc->pending_async_planes) { 424 for (i = 0; i < mtk_crtc->layer_nr; i++) { 425 struct drm_plane *plane = &mtk_crtc->planes[i]; 426 struct mtk_plane_state *plane_state; 427 428 plane_state = to_mtk_plane_state(plane->state); 429 430 if (!plane_state->pending.async_config) 431 continue; 432 433 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 434 &local_layer); 435 436 if (comp) 437 mtk_ddp_comp_layer_config(comp, local_layer, 438 plane_state, 439 cmdq_handle); 440 plane_state->pending.async_config = false; 441 } 442 mtk_crtc->pending_async_planes = false; 443 } 444 } 445 446 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) 447 { 448 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 449 struct cmdq_pkt *cmdq_handle; 450 #endif 451 struct drm_crtc *crtc = &mtk_crtc->base; 452 struct mtk_drm_private *priv = crtc->dev->dev_private; 453 unsigned int pending_planes = 0, pending_async_planes = 0; 454 int i; 455 456 mutex_lock(&mtk_crtc->hw_lock); 457 for (i = 0; i < mtk_crtc->layer_nr; i++) { 458 struct drm_plane *plane = &mtk_crtc->planes[i]; 459 struct mtk_plane_state *plane_state; 460 461 plane_state = to_mtk_plane_state(plane->state); 462 if (plane_state->pending.dirty) { 463 plane_state->pending.config = true; 464 plane_state->pending.dirty = false; 465 pending_planes |= BIT(i); 466 } else if (plane_state->pending.async_dirty) { 467 plane_state->pending.async_config = true; 468 plane_state->pending.async_dirty = false; 469 pending_async_planes |= BIT(i); 470 } 471 } 472 if (pending_planes) 473 mtk_crtc->pending_planes = true; 474 if (pending_async_planes) 475 mtk_crtc->pending_async_planes = true; 476 477 if (priv->data->shadow_register) { 478 mtk_disp_mutex_acquire(mtk_crtc->mutex); 479 mtk_crtc_ddp_config(crtc, NULL); 480 mtk_disp_mutex_release(mtk_crtc->mutex); 481 } 482 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 483 if (mtk_crtc->cmdq_client) { 484 mbox_flush(mtk_crtc->cmdq_client->chan, 2000); 485 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 486 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 487 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 488 mtk_crtc_ddp_config(crtc, cmdq_handle); 489 cmdq_pkt_finalize(cmdq_handle); 490 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 491 } 492 #endif 493 mutex_unlock(&mtk_crtc->hw_lock); 494 } 495 496 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 497 struct mtk_plane_state *state) 498 { 499 unsigned int local_layer; 500 struct mtk_ddp_comp *comp; 501 502 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 503 if (comp) 504 return mtk_ddp_comp_layer_check(comp, local_layer, state); 505 return 0; 506 } 507 508 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 509 struct drm_plane_state *new_state) 510 { 511 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 512 const struct drm_plane_helper_funcs *plane_helper_funcs = 513 plane->helper_private; 514 515 if (!mtk_crtc->enabled) 516 return; 517 518 plane_helper_funcs->atomic_update(plane, new_state); 519 mtk_drm_crtc_hw_config(mtk_crtc); 520 } 521 522 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 523 struct drm_atomic_state *state) 524 { 525 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 526 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 527 int ret; 528 529 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 530 531 ret = mtk_smi_larb_get(comp->larb_dev); 532 if (ret) { 533 DRM_ERROR("Failed to get larb: %d\n", ret); 534 return; 535 } 536 537 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 538 if (ret) { 539 mtk_smi_larb_put(comp->larb_dev); 540 return; 541 } 542 543 drm_crtc_vblank_on(crtc); 544 mtk_crtc->enabled = true; 545 } 546 547 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 548 struct drm_atomic_state *state) 549 { 550 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 551 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 552 int i; 553 554 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 555 if (!mtk_crtc->enabled) 556 return; 557 558 /* Set all pending plane state to disabled */ 559 for (i = 0; i < mtk_crtc->layer_nr; i++) { 560 struct drm_plane *plane = &mtk_crtc->planes[i]; 561 struct mtk_plane_state *plane_state; 562 563 plane_state = to_mtk_plane_state(plane->state); 564 plane_state->pending.enable = false; 565 plane_state->pending.config = true; 566 } 567 mtk_crtc->pending_planes = true; 568 569 mtk_drm_crtc_hw_config(mtk_crtc); 570 /* Wait for planes to be disabled */ 571 drm_crtc_wait_one_vblank(crtc); 572 573 drm_crtc_vblank_off(crtc); 574 mtk_crtc_ddp_hw_fini(mtk_crtc); 575 mtk_smi_larb_put(comp->larb_dev); 576 577 mtk_crtc->enabled = false; 578 } 579 580 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 581 struct drm_atomic_state *state) 582 { 583 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 584 crtc); 585 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 586 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 587 588 if (mtk_crtc->event && mtk_crtc_state->base.event) 589 DRM_ERROR("new event while there is still a pending event\n"); 590 591 if (mtk_crtc_state->base.event) { 592 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 593 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 594 mtk_crtc->event = mtk_crtc_state->base.event; 595 mtk_crtc_state->base.event = NULL; 596 } 597 } 598 599 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 600 struct drm_atomic_state *state) 601 { 602 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 603 int i; 604 605 if (mtk_crtc->event) 606 mtk_crtc->pending_needs_vblank = true; 607 if (crtc->state->color_mgmt_changed) 608 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 609 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 610 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 611 } 612 mtk_drm_crtc_hw_config(mtk_crtc); 613 } 614 615 static const struct drm_crtc_funcs mtk_crtc_funcs = { 616 .set_config = drm_atomic_helper_set_config, 617 .page_flip = drm_atomic_helper_page_flip, 618 .destroy = mtk_drm_crtc_destroy, 619 .reset = mtk_drm_crtc_reset, 620 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 621 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 622 .gamma_set = drm_atomic_helper_legacy_gamma_set, 623 .enable_vblank = mtk_drm_crtc_enable_vblank, 624 .disable_vblank = mtk_drm_crtc_disable_vblank, 625 }; 626 627 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 628 .mode_fixup = mtk_drm_crtc_mode_fixup, 629 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 630 .atomic_begin = mtk_drm_crtc_atomic_begin, 631 .atomic_flush = mtk_drm_crtc_atomic_flush, 632 .atomic_enable = mtk_drm_crtc_atomic_enable, 633 .atomic_disable = mtk_drm_crtc_atomic_disable, 634 }; 635 636 static int mtk_drm_crtc_init(struct drm_device *drm, 637 struct mtk_drm_crtc *mtk_crtc, 638 unsigned int pipe) 639 { 640 struct drm_plane *primary = NULL; 641 struct drm_plane *cursor = NULL; 642 int i, ret; 643 644 for (i = 0; i < mtk_crtc->layer_nr; i++) { 645 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 646 primary = &mtk_crtc->planes[i]; 647 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 648 cursor = &mtk_crtc->planes[i]; 649 } 650 651 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 652 &mtk_crtc_funcs, NULL); 653 if (ret) 654 goto err_cleanup_crtc; 655 656 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 657 658 return 0; 659 660 err_cleanup_crtc: 661 drm_crtc_cleanup(&mtk_crtc->base); 662 return ret; 663 } 664 665 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 666 { 667 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 668 struct mtk_drm_private *priv = crtc->dev->dev_private; 669 670 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 671 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 672 #else 673 if (!priv->data->shadow_register) 674 #endif 675 mtk_crtc_ddp_config(crtc, NULL); 676 677 mtk_drm_finish_page_flip(mtk_crtc); 678 } 679 680 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 681 int comp_idx) 682 { 683 struct mtk_ddp_comp *comp; 684 685 if (comp_idx > 1) 686 return 0; 687 688 comp = mtk_crtc->ddp_comp[comp_idx]; 689 if (!comp->funcs) 690 return 0; 691 692 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 693 return 0; 694 695 return mtk_ddp_comp_layer_nr(comp); 696 } 697 698 static inline 699 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 700 unsigned int num_planes) 701 { 702 if (plane_idx == 0) 703 return DRM_PLANE_TYPE_PRIMARY; 704 else if (plane_idx == (num_planes - 1)) 705 return DRM_PLANE_TYPE_CURSOR; 706 else 707 return DRM_PLANE_TYPE_OVERLAY; 708 709 } 710 711 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 712 struct mtk_drm_crtc *mtk_crtc, 713 int comp_idx, int pipe) 714 { 715 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 716 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 717 int i, ret; 718 719 for (i = 0; i < num_planes; i++) { 720 ret = mtk_plane_init(drm_dev, 721 &mtk_crtc->planes[mtk_crtc->layer_nr], 722 BIT(pipe), 723 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 724 num_planes), 725 mtk_ddp_comp_supported_rotations(comp)); 726 if (ret) 727 return ret; 728 729 mtk_crtc->layer_nr++; 730 } 731 return 0; 732 } 733 734 int mtk_drm_crtc_create(struct drm_device *drm_dev, 735 const enum mtk_ddp_comp_id *path, unsigned int path_len) 736 { 737 struct mtk_drm_private *priv = drm_dev->dev_private; 738 struct device *dev = drm_dev->dev; 739 struct mtk_drm_crtc *mtk_crtc; 740 unsigned int num_comp_planes = 0; 741 int pipe = priv->num_pipes; 742 int ret; 743 int i; 744 bool has_ctm = false; 745 uint gamma_lut_size = 0; 746 747 if (!path) 748 return 0; 749 750 for (i = 0; i < path_len; i++) { 751 enum mtk_ddp_comp_id comp_id = path[i]; 752 struct device_node *node; 753 754 node = priv->comp_node[comp_id]; 755 if (!node) { 756 dev_info(dev, 757 "Not creating crtc %d because component %d is disabled or missing\n", 758 pipe, comp_id); 759 return 0; 760 } 761 } 762 763 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 764 if (!mtk_crtc) 765 return -ENOMEM; 766 767 mtk_crtc->mmsys_dev = priv->mmsys_dev; 768 mtk_crtc->ddp_comp_nr = path_len; 769 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 770 sizeof(*mtk_crtc->ddp_comp), 771 GFP_KERNEL); 772 if (!mtk_crtc->ddp_comp) 773 return -ENOMEM; 774 775 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 776 if (IS_ERR(mtk_crtc->mutex)) { 777 ret = PTR_ERR(mtk_crtc->mutex); 778 dev_err(dev, "Failed to get mutex: %d\n", ret); 779 return ret; 780 } 781 782 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 783 enum mtk_ddp_comp_id comp_id = path[i]; 784 struct mtk_ddp_comp *comp; 785 struct device_node *node; 786 787 node = priv->comp_node[comp_id]; 788 comp = priv->ddp_comp[comp_id]; 789 if (!comp) { 790 dev_err(dev, "Component %pOF not initialized\n", node); 791 ret = -ENODEV; 792 return ret; 793 } 794 795 mtk_crtc->ddp_comp[i] = comp; 796 797 if (comp->funcs) { 798 if (comp->funcs->gamma_set) 799 gamma_lut_size = MTK_LUT_SIZE; 800 801 if (comp->funcs->ctm_set) 802 has_ctm = true; 803 } 804 } 805 806 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 807 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 808 809 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 810 sizeof(struct drm_plane), GFP_KERNEL); 811 812 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 813 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 814 pipe); 815 if (ret) 816 return ret; 817 } 818 819 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); 820 if (ret < 0) 821 return ret; 822 823 if (gamma_lut_size) 824 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 825 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 826 priv->num_pipes++; 827 mutex_init(&mtk_crtc->hw_lock); 828 829 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 830 mtk_crtc->cmdq_client = 831 cmdq_mbox_create(mtk_crtc->mmsys_dev, 832 drm_crtc_index(&mtk_crtc->base)); 833 if (IS_ERR(mtk_crtc->cmdq_client)) { 834 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 835 drm_crtc_index(&mtk_crtc->base)); 836 mtk_crtc->cmdq_client = NULL; 837 } 838 839 if (mtk_crtc->cmdq_client) { 840 ret = of_property_read_u32_index(priv->mutex_node, 841 "mediatek,gce-events", 842 drm_crtc_index(&mtk_crtc->base), 843 &mtk_crtc->cmdq_event); 844 if (ret) { 845 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 846 drm_crtc_index(&mtk_crtc->base)); 847 cmdq_mbox_destroy(mtk_crtc->cmdq_client); 848 mtk_crtc->cmdq_client = NULL; 849 } 850 } 851 #endif 852 return 0; 853 } 854