1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/mailbox_controller.h> 9 #include <linux/of.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/soc/mediatek/mtk-cmdq.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 15 #include <asm/barrier.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_probe_helper.h> 20 #include <drm/drm_vblank.h> 21 22 #include "mtk_drm_drv.h" 23 #include "mtk_drm_crtc.h" 24 #include "mtk_drm_ddp_comp.h" 25 #include "mtk_drm_gem.h" 26 #include "mtk_drm_plane.h" 27 28 /* 29 * struct mtk_drm_crtc - MediaTek specific crtc structure. 30 * @base: crtc object. 31 * @enabled: records whether crtc_enable succeeded 32 * @planes: array of 4 drm_plane structures, one for each overlay plane 33 * @pending_planes: whether any plane has pending changes to be applied 34 * @mmsys_dev: pointer to the mmsys device for configuration registers 35 * @mutex: handle to one of the ten disp_mutex streams 36 * @ddp_comp_nr: number of components in ddp_comp 37 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 38 * 39 * TODO: Needs update: this header is missing a bunch of member descriptions. 40 */ 41 struct mtk_drm_crtc { 42 struct drm_crtc base; 43 bool enabled; 44 45 bool pending_needs_vblank; 46 struct drm_pending_vblank_event *event; 47 48 struct drm_plane *planes; 49 unsigned int layer_nr; 50 bool pending_planes; 51 bool pending_async_planes; 52 53 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 54 struct cmdq_client cmdq_client; 55 struct cmdq_pkt cmdq_handle; 56 u32 cmdq_event; 57 u32 cmdq_vblank_cnt; 58 wait_queue_head_t cb_blocking_queue; 59 #endif 60 61 struct device *mmsys_dev; 62 struct device *dma_dev; 63 struct mtk_mutex *mutex; 64 unsigned int ddp_comp_nr; 65 struct mtk_ddp_comp **ddp_comp; 66 67 /* lock for display hardware access */ 68 struct mutex hw_lock; 69 bool config_updating; 70 }; 71 72 struct mtk_crtc_state { 73 struct drm_crtc_state base; 74 75 bool pending_config; 76 unsigned int pending_width; 77 unsigned int pending_height; 78 unsigned int pending_vrefresh; 79 }; 80 81 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 82 { 83 return container_of(c, struct mtk_drm_crtc, base); 84 } 85 86 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 87 { 88 return container_of(s, struct mtk_crtc_state, base); 89 } 90 91 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 92 { 93 struct drm_crtc *crtc = &mtk_crtc->base; 94 unsigned long flags; 95 96 spin_lock_irqsave(&crtc->dev->event_lock, flags); 97 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 98 drm_crtc_vblank_put(crtc); 99 mtk_crtc->event = NULL; 100 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 101 } 102 103 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 104 { 105 drm_crtc_handle_vblank(&mtk_crtc->base); 106 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) { 107 mtk_drm_crtc_finish_page_flip(mtk_crtc); 108 mtk_crtc->pending_needs_vblank = false; 109 } 110 } 111 112 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 113 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, 114 size_t size) 115 { 116 struct device *dev; 117 dma_addr_t dma_addr; 118 119 pkt->va_base = kzalloc(size, GFP_KERNEL); 120 if (!pkt->va_base) 121 return -ENOMEM; 122 123 pkt->buf_size = size; 124 pkt->cl = (void *)client; 125 126 dev = client->chan->mbox->dev; 127 dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, 128 DMA_TO_DEVICE); 129 if (dma_mapping_error(dev, dma_addr)) { 130 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); 131 kfree(pkt->va_base); 132 return -ENOMEM; 133 } 134 135 pkt->pa_base = dma_addr; 136 137 return 0; 138 } 139 140 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt) 141 { 142 struct cmdq_client *client = (struct cmdq_client *)pkt->cl; 143 144 dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, 145 DMA_TO_DEVICE); 146 kfree(pkt->va_base); 147 } 148 #endif 149 150 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 151 { 152 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 153 int i; 154 155 mtk_mutex_put(mtk_crtc->mutex); 156 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 157 mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle); 158 159 if (mtk_crtc->cmdq_client.chan) { 160 mbox_free_channel(mtk_crtc->cmdq_client.chan); 161 mtk_crtc->cmdq_client.chan = NULL; 162 } 163 #endif 164 165 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 166 struct mtk_ddp_comp *comp; 167 168 comp = mtk_crtc->ddp_comp[i]; 169 mtk_ddp_comp_unregister_vblank_cb(comp); 170 } 171 172 drm_crtc_cleanup(crtc); 173 } 174 175 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 176 { 177 struct mtk_crtc_state *state; 178 179 if (crtc->state) 180 __drm_atomic_helper_crtc_destroy_state(crtc->state); 181 182 kfree(to_mtk_crtc_state(crtc->state)); 183 crtc->state = NULL; 184 185 state = kzalloc(sizeof(*state), GFP_KERNEL); 186 if (state) 187 __drm_atomic_helper_crtc_reset(crtc, &state->base); 188 } 189 190 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 191 { 192 struct mtk_crtc_state *state; 193 194 state = kmalloc(sizeof(*state), GFP_KERNEL); 195 if (!state) 196 return NULL; 197 198 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 199 200 WARN_ON(state->base.crtc != crtc); 201 state->base.crtc = crtc; 202 state->pending_config = false; 203 204 return &state->base; 205 } 206 207 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 208 struct drm_crtc_state *state) 209 { 210 __drm_atomic_helper_crtc_destroy_state(state); 211 kfree(to_mtk_crtc_state(state)); 212 } 213 214 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 215 const struct drm_display_mode *mode, 216 struct drm_display_mode *adjusted_mode) 217 { 218 /* Nothing to do here, but this callback is mandatory. */ 219 return true; 220 } 221 222 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 223 { 224 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 225 226 state->pending_width = crtc->mode.hdisplay; 227 state->pending_height = crtc->mode.vdisplay; 228 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 229 wmb(); /* Make sure the above parameters are set before update */ 230 state->pending_config = true; 231 } 232 233 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 234 { 235 int ret; 236 int i; 237 238 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 239 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 240 if (ret) { 241 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 242 goto err; 243 } 244 } 245 246 return 0; 247 err: 248 while (--i >= 0) 249 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 250 return ret; 251 } 252 253 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 254 { 255 int i; 256 257 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 258 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 259 } 260 261 static 262 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 263 struct drm_plane *plane, 264 unsigned int *local_layer) 265 { 266 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 267 struct mtk_ddp_comp *comp; 268 int i, count = 0; 269 unsigned int local_index = plane - mtk_crtc->planes; 270 271 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 272 comp = mtk_crtc->ddp_comp[i]; 273 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 274 *local_layer = local_index - count; 275 return comp; 276 } 277 count += mtk_ddp_comp_layer_nr(comp); 278 } 279 280 WARN(1, "Failed to find component for plane %d\n", plane->index); 281 return NULL; 282 } 283 284 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 285 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) 286 { 287 struct cmdq_cb_data *data = mssg; 288 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); 289 struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); 290 struct mtk_crtc_state *state; 291 unsigned int i; 292 293 if (data->sta < 0) 294 return; 295 296 state = to_mtk_crtc_state(mtk_crtc->base.state); 297 298 state->pending_config = false; 299 300 if (mtk_crtc->pending_planes) { 301 for (i = 0; i < mtk_crtc->layer_nr; i++) { 302 struct drm_plane *plane = &mtk_crtc->planes[i]; 303 struct mtk_plane_state *plane_state; 304 305 plane_state = to_mtk_plane_state(plane->state); 306 307 plane_state->pending.config = false; 308 } 309 mtk_crtc->pending_planes = false; 310 } 311 312 if (mtk_crtc->pending_async_planes) { 313 for (i = 0; i < mtk_crtc->layer_nr; i++) { 314 struct drm_plane *plane = &mtk_crtc->planes[i]; 315 struct mtk_plane_state *plane_state; 316 317 plane_state = to_mtk_plane_state(plane->state); 318 319 plane_state->pending.async_config = false; 320 } 321 mtk_crtc->pending_async_planes = false; 322 } 323 324 mtk_crtc->cmdq_vblank_cnt = 0; 325 wake_up(&mtk_crtc->cb_blocking_queue); 326 } 327 #endif 328 329 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 330 { 331 struct drm_crtc *crtc = &mtk_crtc->base; 332 struct drm_connector *connector; 333 struct drm_encoder *encoder; 334 struct drm_connector_list_iter conn_iter; 335 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 336 int ret; 337 int i; 338 339 if (WARN_ON(!crtc->state)) 340 return -EINVAL; 341 342 width = crtc->state->adjusted_mode.hdisplay; 343 height = crtc->state->adjusted_mode.vdisplay; 344 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 345 346 drm_for_each_encoder(encoder, crtc->dev) { 347 if (encoder->crtc != crtc) 348 continue; 349 350 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 351 drm_for_each_connector_iter(connector, &conn_iter) { 352 if (connector->encoder != encoder) 353 continue; 354 if (connector->display_info.bpc != 0 && 355 bpc > connector->display_info.bpc) 356 bpc = connector->display_info.bpc; 357 } 358 drm_connector_list_iter_end(&conn_iter); 359 } 360 361 ret = pm_runtime_resume_and_get(crtc->dev->dev); 362 if (ret < 0) { 363 DRM_ERROR("Failed to enable power domain: %d\n", ret); 364 return ret; 365 } 366 367 ret = mtk_mutex_prepare(mtk_crtc->mutex); 368 if (ret < 0) { 369 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 370 goto err_pm_runtime_put; 371 } 372 373 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 374 if (ret < 0) { 375 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 376 goto err_mutex_unprepare; 377 } 378 379 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 380 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 381 mtk_crtc->ddp_comp[i + 1]->id)) 382 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 383 mtk_crtc->ddp_comp[i]->id, 384 mtk_crtc->ddp_comp[i + 1]->id); 385 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 386 mtk_mutex_add_comp(mtk_crtc->mutex, 387 mtk_crtc->ddp_comp[i]->id); 388 } 389 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 390 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 391 mtk_mutex_enable(mtk_crtc->mutex); 392 393 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 394 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 395 396 if (i == 1) 397 mtk_ddp_comp_bgclr_in_on(comp); 398 399 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 400 mtk_ddp_comp_start(comp); 401 } 402 403 /* Initially configure all planes */ 404 for (i = 0; i < mtk_crtc->layer_nr; i++) { 405 struct drm_plane *plane = &mtk_crtc->planes[i]; 406 struct mtk_plane_state *plane_state; 407 struct mtk_ddp_comp *comp; 408 unsigned int local_layer; 409 410 plane_state = to_mtk_plane_state(plane->state); 411 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 412 if (comp) 413 mtk_ddp_comp_layer_config(comp, local_layer, 414 plane_state, NULL); 415 } 416 417 return 0; 418 419 err_mutex_unprepare: 420 mtk_mutex_unprepare(mtk_crtc->mutex); 421 err_pm_runtime_put: 422 pm_runtime_put(crtc->dev->dev); 423 return ret; 424 } 425 426 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 427 { 428 struct drm_device *drm = mtk_crtc->base.dev; 429 struct drm_crtc *crtc = &mtk_crtc->base; 430 int i; 431 432 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 433 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 434 if (i == 1) 435 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 436 } 437 438 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 439 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 440 mtk_mutex_remove_comp(mtk_crtc->mutex, 441 mtk_crtc->ddp_comp[i]->id); 442 mtk_mutex_disable(mtk_crtc->mutex); 443 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 444 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 445 mtk_crtc->ddp_comp[i + 1]->id)) 446 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 447 mtk_crtc->ddp_comp[i]->id, 448 mtk_crtc->ddp_comp[i + 1]->id); 449 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 450 mtk_mutex_remove_comp(mtk_crtc->mutex, 451 mtk_crtc->ddp_comp[i]->id); 452 } 453 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 454 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 455 mtk_crtc_ddp_clk_disable(mtk_crtc); 456 mtk_mutex_unprepare(mtk_crtc->mutex); 457 458 pm_runtime_put(drm->dev); 459 460 if (crtc->state->event && !crtc->state->active) { 461 spin_lock_irq(&crtc->dev->event_lock); 462 drm_crtc_send_vblank_event(crtc, crtc->state->event); 463 crtc->state->event = NULL; 464 spin_unlock_irq(&crtc->dev->event_lock); 465 } 466 } 467 468 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 469 struct cmdq_pkt *cmdq_handle) 470 { 471 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 472 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 473 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 474 unsigned int i; 475 unsigned int local_layer; 476 477 /* 478 * TODO: instead of updating the registers here, we should prepare 479 * working registers in atomic_commit and let the hardware command 480 * queue update module registers on vblank. 481 */ 482 if (state->pending_config) { 483 mtk_ddp_comp_config(comp, state->pending_width, 484 state->pending_height, 485 state->pending_vrefresh, 0, 486 cmdq_handle); 487 488 if (!cmdq_handle) 489 state->pending_config = false; 490 } 491 492 if (mtk_crtc->pending_planes) { 493 for (i = 0; i < mtk_crtc->layer_nr; i++) { 494 struct drm_plane *plane = &mtk_crtc->planes[i]; 495 struct mtk_plane_state *plane_state; 496 497 plane_state = to_mtk_plane_state(plane->state); 498 499 if (!plane_state->pending.config) 500 continue; 501 502 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 503 &local_layer); 504 505 if (comp) 506 mtk_ddp_comp_layer_config(comp, local_layer, 507 plane_state, 508 cmdq_handle); 509 if (!cmdq_handle) 510 plane_state->pending.config = false; 511 } 512 513 if (!cmdq_handle) 514 mtk_crtc->pending_planes = false; 515 } 516 517 if (mtk_crtc->pending_async_planes) { 518 for (i = 0; i < mtk_crtc->layer_nr; i++) { 519 struct drm_plane *plane = &mtk_crtc->planes[i]; 520 struct mtk_plane_state *plane_state; 521 522 plane_state = to_mtk_plane_state(plane->state); 523 524 if (!plane_state->pending.async_config) 525 continue; 526 527 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 528 &local_layer); 529 530 if (comp) 531 mtk_ddp_comp_layer_config(comp, local_layer, 532 plane_state, 533 cmdq_handle); 534 if (!cmdq_handle) 535 plane_state->pending.async_config = false; 536 } 537 538 if (!cmdq_handle) 539 mtk_crtc->pending_async_planes = false; 540 } 541 } 542 543 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 544 bool needs_vblank) 545 { 546 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 547 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle; 548 #endif 549 struct drm_crtc *crtc = &mtk_crtc->base; 550 struct mtk_drm_private *priv = crtc->dev->dev_private; 551 unsigned int pending_planes = 0, pending_async_planes = 0; 552 int i; 553 554 mutex_lock(&mtk_crtc->hw_lock); 555 mtk_crtc->config_updating = true; 556 if (needs_vblank) 557 mtk_crtc->pending_needs_vblank = true; 558 559 for (i = 0; i < mtk_crtc->layer_nr; i++) { 560 struct drm_plane *plane = &mtk_crtc->planes[i]; 561 struct mtk_plane_state *plane_state; 562 563 plane_state = to_mtk_plane_state(plane->state); 564 if (plane_state->pending.dirty) { 565 plane_state->pending.config = true; 566 plane_state->pending.dirty = false; 567 pending_planes |= BIT(i); 568 } else if (plane_state->pending.async_dirty) { 569 plane_state->pending.async_config = true; 570 plane_state->pending.async_dirty = false; 571 pending_async_planes |= BIT(i); 572 } 573 } 574 if (pending_planes) 575 mtk_crtc->pending_planes = true; 576 if (pending_async_planes) 577 mtk_crtc->pending_async_planes = true; 578 579 if (priv->data->shadow_register) { 580 mtk_mutex_acquire(mtk_crtc->mutex); 581 mtk_crtc_ddp_config(crtc, NULL); 582 mtk_mutex_release(mtk_crtc->mutex); 583 } 584 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 585 if (mtk_crtc->cmdq_client.chan) { 586 mbox_flush(mtk_crtc->cmdq_client.chan, 2000); 587 cmdq_handle->cmd_buf_size = 0; 588 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 589 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 590 mtk_crtc_ddp_config(crtc, cmdq_handle); 591 cmdq_pkt_finalize(cmdq_handle); 592 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev, 593 cmdq_handle->pa_base, 594 cmdq_handle->cmd_buf_size, 595 DMA_TO_DEVICE); 596 /* 597 * CMDQ command should execute in next 3 vblank. 598 * One vblank interrupt before send message (occasionally) 599 * and one vblank interrupt after cmdq done, 600 * so it's timeout after 3 vblank interrupt. 601 * If it fail to execute in next 3 vblank, timeout happen. 602 */ 603 mtk_crtc->cmdq_vblank_cnt = 3; 604 605 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); 606 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); 607 } 608 #endif 609 mtk_crtc->config_updating = false; 610 mutex_unlock(&mtk_crtc->hw_lock); 611 } 612 613 static void mtk_crtc_ddp_irq(void *data) 614 { 615 struct drm_crtc *crtc = data; 616 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 617 struct mtk_drm_private *priv = crtc->dev->dev_private; 618 619 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 620 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) 621 mtk_crtc_ddp_config(crtc, NULL); 622 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) 623 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", 624 drm_crtc_index(&mtk_crtc->base)); 625 #else 626 if (!priv->data->shadow_register) 627 mtk_crtc_ddp_config(crtc, NULL); 628 #endif 629 mtk_drm_finish_page_flip(mtk_crtc); 630 } 631 632 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 633 { 634 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 635 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 636 637 mtk_ddp_comp_enable_vblank(comp); 638 639 return 0; 640 } 641 642 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 643 { 644 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 645 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 646 647 mtk_ddp_comp_disable_vblank(comp); 648 } 649 650 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 651 struct mtk_plane_state *state) 652 { 653 unsigned int local_layer; 654 struct mtk_ddp_comp *comp; 655 656 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 657 if (comp) 658 return mtk_ddp_comp_layer_check(comp, local_layer, state); 659 return 0; 660 } 661 662 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 663 struct drm_atomic_state *state) 664 { 665 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 666 667 if (!mtk_crtc->enabled) 668 return; 669 670 mtk_drm_crtc_update_config(mtk_crtc, false); 671 } 672 673 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 674 struct drm_atomic_state *state) 675 { 676 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 677 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 678 int ret; 679 680 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 681 682 ret = pm_runtime_resume_and_get(comp->dev); 683 if (ret < 0) { 684 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret); 685 return; 686 } 687 688 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 689 if (ret) { 690 pm_runtime_put(comp->dev); 691 return; 692 } 693 694 drm_crtc_vblank_on(crtc); 695 mtk_crtc->enabled = true; 696 } 697 698 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 699 struct drm_atomic_state *state) 700 { 701 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 702 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 703 int i, ret; 704 705 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 706 if (!mtk_crtc->enabled) 707 return; 708 709 /* Set all pending plane state to disabled */ 710 for (i = 0; i < mtk_crtc->layer_nr; i++) { 711 struct drm_plane *plane = &mtk_crtc->planes[i]; 712 struct mtk_plane_state *plane_state; 713 714 plane_state = to_mtk_plane_state(plane->state); 715 plane_state->pending.enable = false; 716 plane_state->pending.config = true; 717 } 718 mtk_crtc->pending_planes = true; 719 720 mtk_drm_crtc_update_config(mtk_crtc, false); 721 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 722 /* Wait for planes to be disabled by cmdq */ 723 if (mtk_crtc->cmdq_client.chan) 724 wait_event_timeout(mtk_crtc->cb_blocking_queue, 725 mtk_crtc->cmdq_vblank_cnt == 0, 726 msecs_to_jiffies(500)); 727 #endif 728 /* Wait for planes to be disabled */ 729 drm_crtc_wait_one_vblank(crtc); 730 731 drm_crtc_vblank_off(crtc); 732 mtk_crtc_ddp_hw_fini(mtk_crtc); 733 ret = pm_runtime_put(comp->dev); 734 if (ret < 0) 735 DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret); 736 737 mtk_crtc->enabled = false; 738 } 739 740 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 741 struct drm_atomic_state *state) 742 { 743 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 744 crtc); 745 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 746 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 747 748 if (mtk_crtc->event && mtk_crtc_state->base.event) 749 DRM_ERROR("new event while there is still a pending event\n"); 750 751 if (mtk_crtc_state->base.event) { 752 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 753 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 754 mtk_crtc->event = mtk_crtc_state->base.event; 755 mtk_crtc_state->base.event = NULL; 756 } 757 } 758 759 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 760 struct drm_atomic_state *state) 761 { 762 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 763 int i; 764 765 if (crtc->state->color_mgmt_changed) 766 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 767 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 768 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 769 } 770 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event); 771 } 772 773 static const struct drm_crtc_funcs mtk_crtc_funcs = { 774 .set_config = drm_atomic_helper_set_config, 775 .page_flip = drm_atomic_helper_page_flip, 776 .destroy = mtk_drm_crtc_destroy, 777 .reset = mtk_drm_crtc_reset, 778 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 779 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 780 .enable_vblank = mtk_drm_crtc_enable_vblank, 781 .disable_vblank = mtk_drm_crtc_disable_vblank, 782 }; 783 784 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 785 .mode_fixup = mtk_drm_crtc_mode_fixup, 786 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 787 .atomic_begin = mtk_drm_crtc_atomic_begin, 788 .atomic_flush = mtk_drm_crtc_atomic_flush, 789 .atomic_enable = mtk_drm_crtc_atomic_enable, 790 .atomic_disable = mtk_drm_crtc_atomic_disable, 791 }; 792 793 static int mtk_drm_crtc_init(struct drm_device *drm, 794 struct mtk_drm_crtc *mtk_crtc, 795 unsigned int pipe) 796 { 797 struct drm_plane *primary = NULL; 798 struct drm_plane *cursor = NULL; 799 int i, ret; 800 801 for (i = 0; i < mtk_crtc->layer_nr; i++) { 802 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 803 primary = &mtk_crtc->planes[i]; 804 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 805 cursor = &mtk_crtc->planes[i]; 806 } 807 808 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 809 &mtk_crtc_funcs, NULL); 810 if (ret) 811 goto err_cleanup_crtc; 812 813 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 814 815 return 0; 816 817 err_cleanup_crtc: 818 drm_crtc_cleanup(&mtk_crtc->base); 819 return ret; 820 } 821 822 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 823 int comp_idx) 824 { 825 struct mtk_ddp_comp *comp; 826 827 if (comp_idx > 1) 828 return 0; 829 830 comp = mtk_crtc->ddp_comp[comp_idx]; 831 if (!comp->funcs) 832 return 0; 833 834 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 835 return 0; 836 837 return mtk_ddp_comp_layer_nr(comp); 838 } 839 840 static inline 841 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 842 unsigned int num_planes) 843 { 844 if (plane_idx == 0) 845 return DRM_PLANE_TYPE_PRIMARY; 846 else if (plane_idx == (num_planes - 1)) 847 return DRM_PLANE_TYPE_CURSOR; 848 else 849 return DRM_PLANE_TYPE_OVERLAY; 850 851 } 852 853 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 854 struct mtk_drm_crtc *mtk_crtc, 855 int comp_idx, int pipe) 856 { 857 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 858 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 859 int i, ret; 860 861 for (i = 0; i < num_planes; i++) { 862 ret = mtk_plane_init(drm_dev, 863 &mtk_crtc->planes[mtk_crtc->layer_nr], 864 BIT(pipe), 865 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 866 num_planes), 867 mtk_ddp_comp_supported_rotations(comp), 868 mtk_ddp_comp_get_formats(comp), 869 mtk_ddp_comp_get_num_formats(comp)); 870 if (ret) 871 return ret; 872 873 mtk_crtc->layer_nr++; 874 } 875 return 0; 876 } 877 878 struct device *mtk_drm_crtc_dma_dev_get(struct drm_crtc *crtc) 879 { 880 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 881 882 return mtk_crtc->dma_dev; 883 } 884 885 int mtk_drm_crtc_create(struct drm_device *drm_dev, 886 const unsigned int *path, unsigned int path_len, 887 int priv_data_index) 888 { 889 struct mtk_drm_private *priv = drm_dev->dev_private; 890 struct device *dev = drm_dev->dev; 891 struct mtk_drm_crtc *mtk_crtc; 892 unsigned int num_comp_planes = 0; 893 int ret; 894 int i; 895 bool has_ctm = false; 896 uint gamma_lut_size = 0; 897 struct drm_crtc *tmp; 898 int crtc_i = 0; 899 900 if (!path) 901 return 0; 902 903 priv = priv->all_drm_private[priv_data_index]; 904 905 drm_for_each_crtc(tmp, drm_dev) 906 crtc_i++; 907 908 for (i = 0; i < path_len; i++) { 909 enum mtk_ddp_comp_id comp_id = path[i]; 910 struct device_node *node; 911 struct mtk_ddp_comp *comp; 912 913 node = priv->comp_node[comp_id]; 914 comp = &priv->ddp_comp[comp_id]; 915 916 /* Not all drm components have a DTS device node, such as ovl_adaptor, 917 * which is the drm bring up sub driver 918 */ 919 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) { 920 dev_info(dev, 921 "Not creating crtc %d because component %d is disabled or missing\n", 922 crtc_i, comp_id); 923 return 0; 924 } 925 926 if (!comp->dev) { 927 dev_err(dev, "Component %pOF not initialized\n", node); 928 return -ENODEV; 929 } 930 } 931 932 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 933 if (!mtk_crtc) 934 return -ENOMEM; 935 936 mtk_crtc->mmsys_dev = priv->mmsys_dev; 937 mtk_crtc->ddp_comp_nr = path_len; 938 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 939 sizeof(*mtk_crtc->ddp_comp), 940 GFP_KERNEL); 941 if (!mtk_crtc->ddp_comp) 942 return -ENOMEM; 943 944 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); 945 if (IS_ERR(mtk_crtc->mutex)) { 946 ret = PTR_ERR(mtk_crtc->mutex); 947 dev_err(dev, "Failed to get mutex: %d\n", ret); 948 return ret; 949 } 950 951 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 952 unsigned int comp_id = path[i]; 953 struct mtk_ddp_comp *comp; 954 955 comp = &priv->ddp_comp[comp_id]; 956 mtk_crtc->ddp_comp[i] = comp; 957 958 if (comp->funcs) { 959 if (comp->funcs->gamma_set) 960 gamma_lut_size = MTK_LUT_SIZE; 961 962 if (comp->funcs->ctm_set) 963 has_ctm = true; 964 } 965 966 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, 967 &mtk_crtc->base); 968 } 969 970 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 971 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 972 973 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 974 sizeof(struct drm_plane), GFP_KERNEL); 975 if (!mtk_crtc->planes) 976 return -ENOMEM; 977 978 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 979 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 980 crtc_i); 981 if (ret) 982 return ret; 983 } 984 985 /* 986 * Default to use the first component as the dma dev. 987 * In the case of ovl_adaptor sub driver, it needs to use the 988 * dma_dev_get function to get representative dma dev. 989 */ 990 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]); 991 992 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i); 993 if (ret < 0) 994 return ret; 995 996 if (gamma_lut_size) 997 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 998 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 999 mutex_init(&mtk_crtc->hw_lock); 1000 1001 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 1002 i = priv->mbox_index++; 1003 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev; 1004 mtk_crtc->cmdq_client.client.tx_block = false; 1005 mtk_crtc->cmdq_client.client.knows_txdone = true; 1006 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb; 1007 mtk_crtc->cmdq_client.chan = 1008 mbox_request_channel(&mtk_crtc->cmdq_client.client, i); 1009 if (IS_ERR(mtk_crtc->cmdq_client.chan)) { 1010 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 1011 drm_crtc_index(&mtk_crtc->base)); 1012 mtk_crtc->cmdq_client.chan = NULL; 1013 } 1014 1015 if (mtk_crtc->cmdq_client.chan) { 1016 ret = of_property_read_u32_index(priv->mutex_node, 1017 "mediatek,gce-events", 1018 i, 1019 &mtk_crtc->cmdq_event); 1020 if (ret) { 1021 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 1022 drm_crtc_index(&mtk_crtc->base)); 1023 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1024 mtk_crtc->cmdq_client.chan = NULL; 1025 } else { 1026 ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client, 1027 &mtk_crtc->cmdq_handle, 1028 PAGE_SIZE); 1029 if (ret) { 1030 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n", 1031 drm_crtc_index(&mtk_crtc->base)); 1032 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1033 mtk_crtc->cmdq_client.chan = NULL; 1034 } 1035 } 1036 1037 /* for sending blocking cmd in crtc disable */ 1038 init_waitqueue_head(&mtk_crtc->cb_blocking_queue); 1039 } 1040 #endif 1041 return 0; 1042 } 1043