1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 9 #include <asm/barrier.h> 10 #include <soc/mediatek/smi.h> 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_plane_helper.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_vblank.h> 16 17 #include "mtk_drm_drv.h" 18 #include "mtk_drm_crtc.h" 19 #include "mtk_drm_ddp.h" 20 #include "mtk_drm_ddp_comp.h" 21 #include "mtk_drm_gem.h" 22 #include "mtk_drm_plane.h" 23 24 /** 25 * struct mtk_drm_crtc - MediaTek specific crtc structure. 26 * @base: crtc object. 27 * @enabled: records whether crtc_enable succeeded 28 * @planes: array of 4 drm_plane structures, one for each overlay plane 29 * @pending_planes: whether any plane has pending changes to be applied 30 * @config_regs: memory mapped mmsys configuration register space 31 * @mutex: handle to one of the ten disp_mutex streams 32 * @ddp_comp_nr: number of components in ddp_comp 33 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 34 */ 35 struct mtk_drm_crtc { 36 struct drm_crtc base; 37 bool enabled; 38 39 bool pending_needs_vblank; 40 struct drm_pending_vblank_event *event; 41 42 struct drm_plane *planes; 43 unsigned int layer_nr; 44 bool pending_planes; 45 46 void __iomem *config_regs; 47 struct mtk_disp_mutex *mutex; 48 unsigned int ddp_comp_nr; 49 struct mtk_ddp_comp **ddp_comp; 50 }; 51 52 struct mtk_crtc_state { 53 struct drm_crtc_state base; 54 55 bool pending_config; 56 unsigned int pending_width; 57 unsigned int pending_height; 58 unsigned int pending_vrefresh; 59 }; 60 61 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 62 { 63 return container_of(c, struct mtk_drm_crtc, base); 64 } 65 66 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 67 { 68 return container_of(s, struct mtk_crtc_state, base); 69 } 70 71 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 72 { 73 struct drm_crtc *crtc = &mtk_crtc->base; 74 unsigned long flags; 75 76 spin_lock_irqsave(&crtc->dev->event_lock, flags); 77 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 78 drm_crtc_vblank_put(crtc); 79 mtk_crtc->event = NULL; 80 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 81 } 82 83 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 84 { 85 drm_crtc_handle_vblank(&mtk_crtc->base); 86 if (mtk_crtc->pending_needs_vblank) { 87 mtk_drm_crtc_finish_page_flip(mtk_crtc); 88 mtk_crtc->pending_needs_vblank = false; 89 } 90 } 91 92 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 93 { 94 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 95 96 mtk_disp_mutex_put(mtk_crtc->mutex); 97 98 drm_crtc_cleanup(crtc); 99 } 100 101 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 102 { 103 struct mtk_crtc_state *state; 104 105 if (crtc->state) { 106 __drm_atomic_helper_crtc_destroy_state(crtc->state); 107 108 state = to_mtk_crtc_state(crtc->state); 109 memset(state, 0, sizeof(*state)); 110 } else { 111 state = kzalloc(sizeof(*state), GFP_KERNEL); 112 if (!state) 113 return; 114 crtc->state = &state->base; 115 } 116 117 state->base.crtc = crtc; 118 } 119 120 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 121 { 122 struct mtk_crtc_state *state; 123 124 state = kzalloc(sizeof(*state), GFP_KERNEL); 125 if (!state) 126 return NULL; 127 128 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 129 130 WARN_ON(state->base.crtc != crtc); 131 state->base.crtc = crtc; 132 133 return &state->base; 134 } 135 136 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 137 struct drm_crtc_state *state) 138 { 139 __drm_atomic_helper_crtc_destroy_state(state); 140 kfree(to_mtk_crtc_state(state)); 141 } 142 143 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 144 const struct drm_display_mode *mode, 145 struct drm_display_mode *adjusted_mode) 146 { 147 /* Nothing to do here, but this callback is mandatory. */ 148 return true; 149 } 150 151 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 152 { 153 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 154 155 state->pending_width = crtc->mode.hdisplay; 156 state->pending_height = crtc->mode.vdisplay; 157 state->pending_vrefresh = crtc->mode.vrefresh; 158 wmb(); /* Make sure the above parameters are set before update */ 159 state->pending_config = true; 160 } 161 162 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 163 { 164 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 165 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 166 167 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 168 169 return 0; 170 } 171 172 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_disable_vblank(comp); 178 } 179 180 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 181 { 182 int ret; 183 int i; 184 185 DRM_DEBUG_DRIVER("%s\n", __func__); 186 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 187 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 188 if (ret) { 189 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 190 goto err; 191 } 192 } 193 194 return 0; 195 err: 196 while (--i >= 0) 197 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 198 return ret; 199 } 200 201 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 202 { 203 int i; 204 205 DRM_DEBUG_DRIVER("%s\n", __func__); 206 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 207 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 208 } 209 210 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 211 { 212 struct drm_crtc *crtc = &mtk_crtc->base; 213 struct drm_connector *connector; 214 struct drm_encoder *encoder; 215 struct drm_connector_list_iter conn_iter; 216 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 217 int ret; 218 int i; 219 220 DRM_DEBUG_DRIVER("%s\n", __func__); 221 if (WARN_ON(!crtc->state)) 222 return -EINVAL; 223 224 width = crtc->state->adjusted_mode.hdisplay; 225 height = crtc->state->adjusted_mode.vdisplay; 226 vrefresh = crtc->state->adjusted_mode.vrefresh; 227 228 drm_for_each_encoder(encoder, crtc->dev) { 229 if (encoder->crtc != crtc) 230 continue; 231 232 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 233 drm_for_each_connector_iter(connector, &conn_iter) { 234 if (connector->encoder != encoder) 235 continue; 236 if (connector->display_info.bpc != 0 && 237 bpc > connector->display_info.bpc) 238 bpc = connector->display_info.bpc; 239 } 240 drm_connector_list_iter_end(&conn_iter); 241 } 242 243 ret = pm_runtime_get_sync(crtc->dev->dev); 244 if (ret < 0) { 245 DRM_ERROR("Failed to enable power domain: %d\n", ret); 246 return ret; 247 } 248 249 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 250 if (ret < 0) { 251 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 252 goto err_pm_runtime_put; 253 } 254 255 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 256 if (ret < 0) { 257 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 258 goto err_mutex_unprepare; 259 } 260 261 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 262 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 263 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 264 mtk_crtc->ddp_comp[i]->id, 265 mtk_crtc->ddp_comp[i + 1]->id); 266 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 267 mtk_crtc->ddp_comp[i]->id); 268 } 269 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 270 mtk_disp_mutex_enable(mtk_crtc->mutex); 271 272 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 273 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 274 275 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); 276 mtk_ddp_comp_start(comp); 277 } 278 279 /* Initially configure all planes */ 280 for (i = 0; i < mtk_crtc->layer_nr; i++) { 281 struct drm_plane *plane = &mtk_crtc->planes[i]; 282 struct mtk_plane_state *plane_state; 283 284 plane_state = to_mtk_plane_state(plane->state); 285 mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i, 286 plane_state); 287 } 288 289 return 0; 290 291 err_mutex_unprepare: 292 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 293 err_pm_runtime_put: 294 pm_runtime_put(crtc->dev->dev); 295 return ret; 296 } 297 298 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 299 { 300 struct drm_device *drm = mtk_crtc->base.dev; 301 int i; 302 303 DRM_DEBUG_DRIVER("%s\n", __func__); 304 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 305 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 306 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 307 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 308 mtk_crtc->ddp_comp[i]->id); 309 mtk_disp_mutex_disable(mtk_crtc->mutex); 310 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 311 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 312 mtk_crtc->ddp_comp[i]->id, 313 mtk_crtc->ddp_comp[i + 1]->id); 314 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 315 mtk_crtc->ddp_comp[i]->id); 316 } 317 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 318 mtk_crtc_ddp_clk_disable(mtk_crtc); 319 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 320 321 pm_runtime_put(drm->dev); 322 } 323 324 static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 325 { 326 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 327 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 328 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 329 unsigned int i; 330 331 /* 332 * TODO: instead of updating the registers here, we should prepare 333 * working registers in atomic_commit and let the hardware command 334 * queue update module registers on vblank. 335 */ 336 if (state->pending_config) { 337 mtk_ddp_comp_config(comp, state->pending_width, 338 state->pending_height, 339 state->pending_vrefresh, 0); 340 341 state->pending_config = false; 342 } 343 344 if (mtk_crtc->pending_planes) { 345 for (i = 0; i < mtk_crtc->layer_nr; i++) { 346 struct drm_plane *plane = &mtk_crtc->planes[i]; 347 struct mtk_plane_state *plane_state; 348 349 plane_state = to_mtk_plane_state(plane->state); 350 351 if (plane_state->pending.config) { 352 mtk_ddp_comp_layer_config(comp, i, plane_state); 353 plane_state->pending.config = false; 354 } 355 } 356 mtk_crtc->pending_planes = false; 357 } 358 } 359 360 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 361 struct drm_crtc_state *old_state) 362 { 363 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 364 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 365 int ret; 366 367 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 368 369 ret = mtk_smi_larb_get(comp->larb_dev); 370 if (ret) { 371 DRM_ERROR("Failed to get larb: %d\n", ret); 372 return; 373 } 374 375 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 376 if (ret) { 377 mtk_smi_larb_put(comp->larb_dev); 378 return; 379 } 380 381 drm_crtc_vblank_on(crtc); 382 mtk_crtc->enabled = true; 383 } 384 385 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 386 struct drm_crtc_state *old_state) 387 { 388 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 389 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 390 int i; 391 392 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 393 if (!mtk_crtc->enabled) 394 return; 395 396 /* Set all pending plane state to disabled */ 397 for (i = 0; i < mtk_crtc->layer_nr; i++) { 398 struct drm_plane *plane = &mtk_crtc->planes[i]; 399 struct mtk_plane_state *plane_state; 400 401 plane_state = to_mtk_plane_state(plane->state); 402 plane_state->pending.enable = false; 403 plane_state->pending.config = true; 404 } 405 mtk_crtc->pending_planes = true; 406 407 /* Wait for planes to be disabled */ 408 drm_crtc_wait_one_vblank(crtc); 409 410 drm_crtc_vblank_off(crtc); 411 mtk_crtc_ddp_hw_fini(mtk_crtc); 412 mtk_smi_larb_put(comp->larb_dev); 413 414 mtk_crtc->enabled = false; 415 } 416 417 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 418 struct drm_crtc_state *old_crtc_state) 419 { 420 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 421 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 422 423 if (mtk_crtc->event && state->base.event) 424 DRM_ERROR("new event while there is still a pending event\n"); 425 426 if (state->base.event) { 427 state->base.event->pipe = drm_crtc_index(crtc); 428 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 429 mtk_crtc->event = state->base.event; 430 state->base.event = NULL; 431 } 432 } 433 434 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 435 struct drm_crtc_state *old_crtc_state) 436 { 437 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 438 struct mtk_drm_private *priv = crtc->dev->dev_private; 439 unsigned int pending_planes = 0; 440 int i; 441 442 if (mtk_crtc->event) 443 mtk_crtc->pending_needs_vblank = true; 444 for (i = 0; i < mtk_crtc->layer_nr; i++) { 445 struct drm_plane *plane = &mtk_crtc->planes[i]; 446 struct mtk_plane_state *plane_state; 447 448 plane_state = to_mtk_plane_state(plane->state); 449 if (plane_state->pending.dirty) { 450 plane_state->pending.config = true; 451 plane_state->pending.dirty = false; 452 pending_planes |= BIT(i); 453 } 454 } 455 if (pending_planes) 456 mtk_crtc->pending_planes = true; 457 if (crtc->state->color_mgmt_changed) 458 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 459 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 460 461 if (priv->data->shadow_register) { 462 mtk_disp_mutex_acquire(mtk_crtc->mutex); 463 mtk_crtc_ddp_config(crtc); 464 mtk_disp_mutex_release(mtk_crtc->mutex); 465 } 466 } 467 468 static const struct drm_crtc_funcs mtk_crtc_funcs = { 469 .set_config = drm_atomic_helper_set_config, 470 .page_flip = drm_atomic_helper_page_flip, 471 .destroy = mtk_drm_crtc_destroy, 472 .reset = mtk_drm_crtc_reset, 473 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 474 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 475 .gamma_set = drm_atomic_helper_legacy_gamma_set, 476 .enable_vblank = mtk_drm_crtc_enable_vblank, 477 .disable_vblank = mtk_drm_crtc_disable_vblank, 478 }; 479 480 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 481 .mode_fixup = mtk_drm_crtc_mode_fixup, 482 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 483 .atomic_begin = mtk_drm_crtc_atomic_begin, 484 .atomic_flush = mtk_drm_crtc_atomic_flush, 485 .atomic_enable = mtk_drm_crtc_atomic_enable, 486 .atomic_disable = mtk_drm_crtc_atomic_disable, 487 }; 488 489 static int mtk_drm_crtc_init(struct drm_device *drm, 490 struct mtk_drm_crtc *mtk_crtc, 491 struct drm_plane *primary, 492 struct drm_plane *cursor, unsigned int pipe) 493 { 494 int ret; 495 496 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 497 &mtk_crtc_funcs, NULL); 498 if (ret) 499 goto err_cleanup_crtc; 500 501 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 502 503 return 0; 504 505 err_cleanup_crtc: 506 drm_crtc_cleanup(&mtk_crtc->base); 507 return ret; 508 } 509 510 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 511 { 512 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 513 struct mtk_drm_private *priv = crtc->dev->dev_private; 514 515 if (!priv->data->shadow_register) 516 mtk_crtc_ddp_config(crtc); 517 518 mtk_drm_finish_page_flip(mtk_crtc); 519 } 520 521 int mtk_drm_crtc_create(struct drm_device *drm_dev, 522 const enum mtk_ddp_comp_id *path, unsigned int path_len) 523 { 524 struct mtk_drm_private *priv = drm_dev->dev_private; 525 struct device *dev = drm_dev->dev; 526 struct mtk_drm_crtc *mtk_crtc; 527 enum drm_plane_type type; 528 unsigned int zpos; 529 int pipe = priv->num_pipes; 530 int ret; 531 int i; 532 533 if (!path) 534 return 0; 535 536 for (i = 0; i < path_len; i++) { 537 enum mtk_ddp_comp_id comp_id = path[i]; 538 struct device_node *node; 539 540 node = priv->comp_node[comp_id]; 541 if (!node) { 542 dev_info(dev, 543 "Not creating crtc %d because component %d is disabled or missing\n", 544 pipe, comp_id); 545 return 0; 546 } 547 } 548 549 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 550 if (!mtk_crtc) 551 return -ENOMEM; 552 553 mtk_crtc->config_regs = priv->config_regs; 554 mtk_crtc->ddp_comp_nr = path_len; 555 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 556 sizeof(*mtk_crtc->ddp_comp), 557 GFP_KERNEL); 558 if (!mtk_crtc->ddp_comp) 559 return -ENOMEM; 560 561 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 562 if (IS_ERR(mtk_crtc->mutex)) { 563 ret = PTR_ERR(mtk_crtc->mutex); 564 dev_err(dev, "Failed to get mutex: %d\n", ret); 565 return ret; 566 } 567 568 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 569 enum mtk_ddp_comp_id comp_id = path[i]; 570 struct mtk_ddp_comp *comp; 571 struct device_node *node; 572 573 node = priv->comp_node[comp_id]; 574 comp = priv->ddp_comp[comp_id]; 575 if (!comp) { 576 dev_err(dev, "Component %pOF not initialized\n", node); 577 ret = -ENODEV; 578 return ret; 579 } 580 581 mtk_crtc->ddp_comp[i] = comp; 582 } 583 584 mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]); 585 mtk_crtc->planes = devm_kcalloc(dev, mtk_crtc->layer_nr, 586 sizeof(struct drm_plane), 587 GFP_KERNEL); 588 589 for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) { 590 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY : 591 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR : 592 DRM_PLANE_TYPE_OVERLAY; 593 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos], 594 BIT(pipe), type); 595 if (ret) 596 return ret; 597 } 598 599 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 600 mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] : 601 NULL, pipe); 602 if (ret < 0) 603 return ret; 604 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); 605 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); 606 priv->num_pipes++; 607 608 return 0; 609 } 610