1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <asm/barrier.h> 15 #include <drm/drmP.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_plane_helper.h> 18 #include <drm/drm_probe_helper.h> 19 #include <linux/clk.h> 20 #include <linux/pm_runtime.h> 21 #include <soc/mediatek/smi.h> 22 23 #include "mtk_drm_drv.h" 24 #include "mtk_drm_crtc.h" 25 #include "mtk_drm_ddp.h" 26 #include "mtk_drm_ddp_comp.h" 27 #include "mtk_drm_gem.h" 28 #include "mtk_drm_plane.h" 29 30 /** 31 * struct mtk_drm_crtc - MediaTek specific crtc structure. 32 * @base: crtc object. 33 * @enabled: records whether crtc_enable succeeded 34 * @planes: array of 4 drm_plane structures, one for each overlay plane 35 * @pending_planes: whether any plane has pending changes to be applied 36 * @config_regs: memory mapped mmsys configuration register space 37 * @mutex: handle to one of the ten disp_mutex streams 38 * @ddp_comp_nr: number of components in ddp_comp 39 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 40 */ 41 struct mtk_drm_crtc { 42 struct drm_crtc base; 43 bool enabled; 44 45 bool pending_needs_vblank; 46 struct drm_pending_vblank_event *event; 47 48 struct drm_plane *planes; 49 unsigned int layer_nr; 50 bool pending_planes; 51 52 void __iomem *config_regs; 53 struct mtk_disp_mutex *mutex; 54 unsigned int ddp_comp_nr; 55 struct mtk_ddp_comp **ddp_comp; 56 }; 57 58 struct mtk_crtc_state { 59 struct drm_crtc_state base; 60 61 bool pending_config; 62 unsigned int pending_width; 63 unsigned int pending_height; 64 unsigned int pending_vrefresh; 65 }; 66 67 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 68 { 69 return container_of(c, struct mtk_drm_crtc, base); 70 } 71 72 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 73 { 74 return container_of(s, struct mtk_crtc_state, base); 75 } 76 77 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 78 { 79 struct drm_crtc *crtc = &mtk_crtc->base; 80 unsigned long flags; 81 82 spin_lock_irqsave(&crtc->dev->event_lock, flags); 83 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 84 drm_crtc_vblank_put(crtc); 85 mtk_crtc->event = NULL; 86 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 87 } 88 89 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 90 { 91 drm_crtc_handle_vblank(&mtk_crtc->base); 92 if (mtk_crtc->pending_needs_vblank) { 93 mtk_drm_crtc_finish_page_flip(mtk_crtc); 94 mtk_crtc->pending_needs_vblank = false; 95 } 96 } 97 98 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 99 { 100 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 101 int i; 102 103 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 104 clk_unprepare(mtk_crtc->ddp_comp[i]->clk); 105 106 mtk_disp_mutex_put(mtk_crtc->mutex); 107 108 drm_crtc_cleanup(crtc); 109 } 110 111 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 112 { 113 struct mtk_crtc_state *state; 114 115 if (crtc->state) { 116 __drm_atomic_helper_crtc_destroy_state(crtc->state); 117 118 state = to_mtk_crtc_state(crtc->state); 119 memset(state, 0, sizeof(*state)); 120 } else { 121 state = kzalloc(sizeof(*state), GFP_KERNEL); 122 if (!state) 123 return; 124 crtc->state = &state->base; 125 } 126 127 state->base.crtc = crtc; 128 } 129 130 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 131 { 132 struct mtk_crtc_state *state; 133 134 state = kzalloc(sizeof(*state), GFP_KERNEL); 135 if (!state) 136 return NULL; 137 138 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 139 140 WARN_ON(state->base.crtc != crtc); 141 state->base.crtc = crtc; 142 143 return &state->base; 144 } 145 146 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 147 struct drm_crtc_state *state) 148 { 149 __drm_atomic_helper_crtc_destroy_state(state); 150 kfree(to_mtk_crtc_state(state)); 151 } 152 153 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 154 const struct drm_display_mode *mode, 155 struct drm_display_mode *adjusted_mode) 156 { 157 /* Nothing to do here, but this callback is mandatory. */ 158 return true; 159 } 160 161 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 162 { 163 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 164 165 state->pending_width = crtc->mode.hdisplay; 166 state->pending_height = crtc->mode.vdisplay; 167 state->pending_vrefresh = crtc->mode.vrefresh; 168 wmb(); /* Make sure the above parameters are set before update */ 169 state->pending_config = true; 170 } 171 172 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 178 179 return 0; 180 } 181 182 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 183 { 184 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 185 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 186 187 mtk_ddp_comp_disable_vblank(comp); 188 } 189 190 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 191 { 192 int ret; 193 int i; 194 195 DRM_DEBUG_DRIVER("%s\n", __func__); 196 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 197 ret = clk_enable(mtk_crtc->ddp_comp[i]->clk); 198 if (ret) { 199 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 200 goto err; 201 } 202 } 203 204 return 0; 205 err: 206 while (--i >= 0) 207 clk_disable(mtk_crtc->ddp_comp[i]->clk); 208 return ret; 209 } 210 211 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 212 { 213 int i; 214 215 DRM_DEBUG_DRIVER("%s\n", __func__); 216 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 217 clk_disable(mtk_crtc->ddp_comp[i]->clk); 218 } 219 220 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 221 { 222 struct drm_crtc *crtc = &mtk_crtc->base; 223 struct drm_connector *connector; 224 struct drm_encoder *encoder; 225 struct drm_connector_list_iter conn_iter; 226 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 227 int ret; 228 int i; 229 230 DRM_DEBUG_DRIVER("%s\n", __func__); 231 if (WARN_ON(!crtc->state)) 232 return -EINVAL; 233 234 width = crtc->state->adjusted_mode.hdisplay; 235 height = crtc->state->adjusted_mode.vdisplay; 236 vrefresh = crtc->state->adjusted_mode.vrefresh; 237 238 drm_for_each_encoder(encoder, crtc->dev) { 239 if (encoder->crtc != crtc) 240 continue; 241 242 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 243 drm_for_each_connector_iter(connector, &conn_iter) { 244 if (connector->encoder != encoder) 245 continue; 246 if (connector->display_info.bpc != 0 && 247 bpc > connector->display_info.bpc) 248 bpc = connector->display_info.bpc; 249 } 250 drm_connector_list_iter_end(&conn_iter); 251 } 252 253 ret = pm_runtime_get_sync(crtc->dev->dev); 254 if (ret < 0) { 255 DRM_ERROR("Failed to enable power domain: %d\n", ret); 256 return ret; 257 } 258 259 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 260 if (ret < 0) { 261 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 262 goto err_pm_runtime_put; 263 } 264 265 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 266 if (ret < 0) { 267 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 268 goto err_mutex_unprepare; 269 } 270 271 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 272 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 273 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 274 mtk_crtc->ddp_comp[i]->id, 275 mtk_crtc->ddp_comp[i + 1]->id); 276 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 277 mtk_crtc->ddp_comp[i]->id); 278 } 279 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 280 mtk_disp_mutex_enable(mtk_crtc->mutex); 281 282 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 283 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 284 285 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); 286 mtk_ddp_comp_start(comp); 287 } 288 289 /* Initially configure all planes */ 290 for (i = 0; i < mtk_crtc->layer_nr; i++) { 291 struct drm_plane *plane = &mtk_crtc->planes[i]; 292 struct mtk_plane_state *plane_state; 293 294 plane_state = to_mtk_plane_state(plane->state); 295 mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[0], i, 296 plane_state); 297 } 298 299 return 0; 300 301 err_mutex_unprepare: 302 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 303 err_pm_runtime_put: 304 pm_runtime_put(crtc->dev->dev); 305 return ret; 306 } 307 308 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 309 { 310 struct drm_device *drm = mtk_crtc->base.dev; 311 int i; 312 313 DRM_DEBUG_DRIVER("%s\n", __func__); 314 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 315 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 316 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 317 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 318 mtk_crtc->ddp_comp[i]->id); 319 mtk_disp_mutex_disable(mtk_crtc->mutex); 320 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 321 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 322 mtk_crtc->ddp_comp[i]->id, 323 mtk_crtc->ddp_comp[i + 1]->id); 324 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 325 mtk_crtc->ddp_comp[i]->id); 326 } 327 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 328 mtk_crtc_ddp_clk_disable(mtk_crtc); 329 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 330 331 pm_runtime_put(drm->dev); 332 } 333 334 static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 335 { 336 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 337 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 338 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 339 unsigned int i; 340 341 /* 342 * TODO: instead of updating the registers here, we should prepare 343 * working registers in atomic_commit and let the hardware command 344 * queue update module registers on vblank. 345 */ 346 if (state->pending_config) { 347 mtk_ddp_comp_config(comp, state->pending_width, 348 state->pending_height, 349 state->pending_vrefresh, 0); 350 351 state->pending_config = false; 352 } 353 354 if (mtk_crtc->pending_planes) { 355 for (i = 0; i < mtk_crtc->layer_nr; i++) { 356 struct drm_plane *plane = &mtk_crtc->planes[i]; 357 struct mtk_plane_state *plane_state; 358 359 plane_state = to_mtk_plane_state(plane->state); 360 361 if (plane_state->pending.config) { 362 mtk_ddp_comp_layer_config(comp, i, plane_state); 363 plane_state->pending.config = false; 364 } 365 } 366 mtk_crtc->pending_planes = false; 367 } 368 } 369 370 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 371 struct drm_crtc_state *old_state) 372 { 373 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 374 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 375 int ret; 376 377 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 378 379 ret = mtk_smi_larb_get(comp->larb_dev); 380 if (ret) { 381 DRM_ERROR("Failed to get larb: %d\n", ret); 382 return; 383 } 384 385 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 386 if (ret) { 387 mtk_smi_larb_put(comp->larb_dev); 388 return; 389 } 390 391 drm_crtc_vblank_on(crtc); 392 mtk_crtc->enabled = true; 393 } 394 395 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 396 struct drm_crtc_state *old_state) 397 { 398 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 399 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 400 int i; 401 402 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 403 if (!mtk_crtc->enabled) 404 return; 405 406 /* Set all pending plane state to disabled */ 407 for (i = 0; i < mtk_crtc->layer_nr; i++) { 408 struct drm_plane *plane = &mtk_crtc->planes[i]; 409 struct mtk_plane_state *plane_state; 410 411 plane_state = to_mtk_plane_state(plane->state); 412 plane_state->pending.enable = false; 413 plane_state->pending.config = true; 414 } 415 mtk_crtc->pending_planes = true; 416 417 /* Wait for planes to be disabled */ 418 drm_crtc_wait_one_vblank(crtc); 419 420 drm_crtc_vblank_off(crtc); 421 mtk_crtc_ddp_hw_fini(mtk_crtc); 422 mtk_smi_larb_put(comp->larb_dev); 423 424 mtk_crtc->enabled = false; 425 } 426 427 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 428 struct drm_crtc_state *old_crtc_state) 429 { 430 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 431 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 432 433 if (mtk_crtc->event && state->base.event) 434 DRM_ERROR("new event while there is still a pending event\n"); 435 436 if (state->base.event) { 437 state->base.event->pipe = drm_crtc_index(crtc); 438 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 439 mtk_crtc->event = state->base.event; 440 state->base.event = NULL; 441 } 442 } 443 444 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 445 struct drm_crtc_state *old_crtc_state) 446 { 447 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 448 struct mtk_drm_private *priv = crtc->dev->dev_private; 449 unsigned int pending_planes = 0; 450 int i; 451 452 if (mtk_crtc->event) 453 mtk_crtc->pending_needs_vblank = true; 454 for (i = 0; i < mtk_crtc->layer_nr; i++) { 455 struct drm_plane *plane = &mtk_crtc->planes[i]; 456 struct mtk_plane_state *plane_state; 457 458 plane_state = to_mtk_plane_state(plane->state); 459 if (plane_state->pending.dirty) { 460 plane_state->pending.config = true; 461 plane_state->pending.dirty = false; 462 pending_planes |= BIT(i); 463 } 464 } 465 if (pending_planes) 466 mtk_crtc->pending_planes = true; 467 if (crtc->state->color_mgmt_changed) 468 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 469 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 470 471 if (priv->data->shadow_register) { 472 mtk_disp_mutex_acquire(mtk_crtc->mutex); 473 mtk_crtc_ddp_config(crtc); 474 mtk_disp_mutex_release(mtk_crtc->mutex); 475 } 476 } 477 478 static const struct drm_crtc_funcs mtk_crtc_funcs = { 479 .set_config = drm_atomic_helper_set_config, 480 .page_flip = drm_atomic_helper_page_flip, 481 .destroy = mtk_drm_crtc_destroy, 482 .reset = mtk_drm_crtc_reset, 483 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 484 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 485 .gamma_set = drm_atomic_helper_legacy_gamma_set, 486 .enable_vblank = mtk_drm_crtc_enable_vblank, 487 .disable_vblank = mtk_drm_crtc_disable_vblank, 488 }; 489 490 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 491 .mode_fixup = mtk_drm_crtc_mode_fixup, 492 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 493 .atomic_begin = mtk_drm_crtc_atomic_begin, 494 .atomic_flush = mtk_drm_crtc_atomic_flush, 495 .atomic_enable = mtk_drm_crtc_atomic_enable, 496 .atomic_disable = mtk_drm_crtc_atomic_disable, 497 }; 498 499 static int mtk_drm_crtc_init(struct drm_device *drm, 500 struct mtk_drm_crtc *mtk_crtc, 501 struct drm_plane *primary, 502 struct drm_plane *cursor, unsigned int pipe) 503 { 504 int ret; 505 506 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 507 &mtk_crtc_funcs, NULL); 508 if (ret) 509 goto err_cleanup_crtc; 510 511 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 512 513 return 0; 514 515 err_cleanup_crtc: 516 drm_crtc_cleanup(&mtk_crtc->base); 517 return ret; 518 } 519 520 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 521 { 522 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 523 struct mtk_drm_private *priv = crtc->dev->dev_private; 524 525 if (!priv->data->shadow_register) 526 mtk_crtc_ddp_config(crtc); 527 528 mtk_drm_finish_page_flip(mtk_crtc); 529 } 530 531 int mtk_drm_crtc_create(struct drm_device *drm_dev, 532 const enum mtk_ddp_comp_id *path, unsigned int path_len) 533 { 534 struct mtk_drm_private *priv = drm_dev->dev_private; 535 struct device *dev = drm_dev->dev; 536 struct mtk_drm_crtc *mtk_crtc; 537 enum drm_plane_type type; 538 unsigned int zpos; 539 int pipe = priv->num_pipes; 540 int ret; 541 int i; 542 543 if (!path) 544 return 0; 545 546 for (i = 0; i < path_len; i++) { 547 enum mtk_ddp_comp_id comp_id = path[i]; 548 struct device_node *node; 549 550 node = priv->comp_node[comp_id]; 551 if (!node) { 552 dev_info(dev, 553 "Not creating crtc %d because component %d is disabled or missing\n", 554 pipe, comp_id); 555 return 0; 556 } 557 } 558 559 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 560 if (!mtk_crtc) 561 return -ENOMEM; 562 563 mtk_crtc->config_regs = priv->config_regs; 564 mtk_crtc->ddp_comp_nr = path_len; 565 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 566 sizeof(*mtk_crtc->ddp_comp), 567 GFP_KERNEL); 568 if (!mtk_crtc->ddp_comp) 569 return -ENOMEM; 570 571 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 572 if (IS_ERR(mtk_crtc->mutex)) { 573 ret = PTR_ERR(mtk_crtc->mutex); 574 dev_err(dev, "Failed to get mutex: %d\n", ret); 575 return ret; 576 } 577 578 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 579 enum mtk_ddp_comp_id comp_id = path[i]; 580 struct mtk_ddp_comp *comp; 581 struct device_node *node; 582 583 node = priv->comp_node[comp_id]; 584 comp = priv->ddp_comp[comp_id]; 585 if (!comp) { 586 dev_err(dev, "Component %pOF not initialized\n", node); 587 ret = -ENODEV; 588 goto unprepare; 589 } 590 591 ret = clk_prepare(comp->clk); 592 if (ret) { 593 dev_err(dev, 594 "Failed to prepare clock for component %pOF: %d\n", 595 node, ret); 596 goto unprepare; 597 } 598 599 mtk_crtc->ddp_comp[i] = comp; 600 } 601 602 mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]); 603 mtk_crtc->planes = devm_kcalloc(dev, mtk_crtc->layer_nr, 604 sizeof(struct drm_plane), 605 GFP_KERNEL); 606 607 for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) { 608 type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY : 609 (zpos == 1) ? DRM_PLANE_TYPE_CURSOR : 610 DRM_PLANE_TYPE_OVERLAY; 611 ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos], 612 BIT(pipe), type); 613 if (ret) 614 goto unprepare; 615 } 616 617 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 618 mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] : 619 NULL, pipe); 620 if (ret < 0) 621 goto unprepare; 622 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); 623 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); 624 priv->num_pipes++; 625 626 return 0; 627 628 unprepare: 629 while (--i >= 0) 630 clk_unprepare(mtk_crtc->ddp_comp[i]->clk); 631 632 return ret; 633 } 634