1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/mailbox_controller.h> 9 #include <linux/of.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/soc/mediatek/mtk-cmdq.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 15 #include <asm/barrier.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_probe_helper.h> 20 #include <drm/drm_vblank.h> 21 22 #include "mtk_drm_drv.h" 23 #include "mtk_drm_crtc.h" 24 #include "mtk_drm_ddp_comp.h" 25 #include "mtk_drm_gem.h" 26 #include "mtk_drm_plane.h" 27 28 /* 29 * struct mtk_drm_crtc - MediaTek specific crtc structure. 30 * @base: crtc object. 31 * @enabled: records whether crtc_enable succeeded 32 * @planes: array of 4 drm_plane structures, one for each overlay plane 33 * @pending_planes: whether any plane has pending changes to be applied 34 * @mmsys_dev: pointer to the mmsys device for configuration registers 35 * @mutex: handle to one of the ten disp_mutex streams 36 * @ddp_comp_nr: number of components in ddp_comp 37 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 38 * 39 * TODO: Needs update: this header is missing a bunch of member descriptions. 40 */ 41 struct mtk_drm_crtc { 42 struct drm_crtc base; 43 bool enabled; 44 45 bool pending_needs_vblank; 46 struct drm_pending_vblank_event *event; 47 48 struct drm_plane *planes; 49 unsigned int layer_nr; 50 bool pending_planes; 51 bool pending_async_planes; 52 53 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 54 struct cmdq_client cmdq_client; 55 struct cmdq_pkt cmdq_handle; 56 u32 cmdq_event; 57 u32 cmdq_vblank_cnt; 58 wait_queue_head_t cb_blocking_queue; 59 #endif 60 61 struct device *mmsys_dev; 62 struct device *dma_dev; 63 struct mtk_mutex *mutex; 64 unsigned int ddp_comp_nr; 65 struct mtk_ddp_comp **ddp_comp; 66 67 /* lock for display hardware access */ 68 struct mutex hw_lock; 69 bool config_updating; 70 /* lock for config_updating to cmd buffer */ 71 spinlock_t config_lock; 72 }; 73 74 struct mtk_crtc_state { 75 struct drm_crtc_state base; 76 77 bool pending_config; 78 unsigned int pending_width; 79 unsigned int pending_height; 80 unsigned int pending_vrefresh; 81 }; 82 83 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 84 { 85 return container_of(c, struct mtk_drm_crtc, base); 86 } 87 88 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 89 { 90 return container_of(s, struct mtk_crtc_state, base); 91 } 92 93 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 94 { 95 struct drm_crtc *crtc = &mtk_crtc->base; 96 unsigned long flags; 97 98 if (mtk_crtc->event) { 99 spin_lock_irqsave(&crtc->dev->event_lock, flags); 100 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 101 drm_crtc_vblank_put(crtc); 102 mtk_crtc->event = NULL; 103 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 104 } 105 } 106 107 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 108 { 109 unsigned long flags; 110 111 drm_crtc_handle_vblank(&mtk_crtc->base); 112 113 spin_lock_irqsave(&mtk_crtc->config_lock, flags); 114 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) { 115 mtk_drm_crtc_finish_page_flip(mtk_crtc); 116 mtk_crtc->pending_needs_vblank = false; 117 } 118 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); 119 } 120 121 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 122 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, 123 size_t size) 124 { 125 struct device *dev; 126 dma_addr_t dma_addr; 127 128 pkt->va_base = kzalloc(size, GFP_KERNEL); 129 if (!pkt->va_base) 130 return -ENOMEM; 131 132 pkt->buf_size = size; 133 pkt->cl = (void *)client; 134 135 dev = client->chan->mbox->dev; 136 dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, 137 DMA_TO_DEVICE); 138 if (dma_mapping_error(dev, dma_addr)) { 139 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); 140 kfree(pkt->va_base); 141 return -ENOMEM; 142 } 143 144 pkt->pa_base = dma_addr; 145 146 return 0; 147 } 148 149 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt) 150 { 151 struct cmdq_client *client = (struct cmdq_client *)pkt->cl; 152 153 dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, 154 DMA_TO_DEVICE); 155 kfree(pkt->va_base); 156 } 157 #endif 158 159 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 160 { 161 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 162 int i; 163 164 mtk_mutex_put(mtk_crtc->mutex); 165 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 166 mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle); 167 168 if (mtk_crtc->cmdq_client.chan) { 169 mbox_free_channel(mtk_crtc->cmdq_client.chan); 170 mtk_crtc->cmdq_client.chan = NULL; 171 } 172 #endif 173 174 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 175 struct mtk_ddp_comp *comp; 176 177 comp = mtk_crtc->ddp_comp[i]; 178 mtk_ddp_comp_unregister_vblank_cb(comp); 179 } 180 181 drm_crtc_cleanup(crtc); 182 } 183 184 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 185 { 186 struct mtk_crtc_state *state; 187 188 if (crtc->state) 189 __drm_atomic_helper_crtc_destroy_state(crtc->state); 190 191 kfree(to_mtk_crtc_state(crtc->state)); 192 crtc->state = NULL; 193 194 state = kzalloc(sizeof(*state), GFP_KERNEL); 195 if (state) 196 __drm_atomic_helper_crtc_reset(crtc, &state->base); 197 } 198 199 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 200 { 201 struct mtk_crtc_state *state; 202 203 state = kmalloc(sizeof(*state), GFP_KERNEL); 204 if (!state) 205 return NULL; 206 207 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 208 209 WARN_ON(state->base.crtc != crtc); 210 state->base.crtc = crtc; 211 state->pending_config = false; 212 213 return &state->base; 214 } 215 216 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 217 struct drm_crtc_state *state) 218 { 219 __drm_atomic_helper_crtc_destroy_state(state); 220 kfree(to_mtk_crtc_state(state)); 221 } 222 223 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 224 const struct drm_display_mode *mode, 225 struct drm_display_mode *adjusted_mode) 226 { 227 /* Nothing to do here, but this callback is mandatory. */ 228 return true; 229 } 230 231 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 232 { 233 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 234 235 state->pending_width = crtc->mode.hdisplay; 236 state->pending_height = crtc->mode.vdisplay; 237 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 238 wmb(); /* Make sure the above parameters are set before update */ 239 state->pending_config = true; 240 } 241 242 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 243 { 244 int ret; 245 int i; 246 247 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 248 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 249 if (ret) { 250 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 251 goto err; 252 } 253 } 254 255 return 0; 256 err: 257 while (--i >= 0) 258 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 259 return ret; 260 } 261 262 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 263 { 264 int i; 265 266 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 267 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 268 } 269 270 static 271 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 272 struct drm_plane *plane, 273 unsigned int *local_layer) 274 { 275 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 276 struct mtk_ddp_comp *comp; 277 int i, count = 0; 278 unsigned int local_index = plane - mtk_crtc->planes; 279 280 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 281 comp = mtk_crtc->ddp_comp[i]; 282 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 283 *local_layer = local_index - count; 284 return comp; 285 } 286 count += mtk_ddp_comp_layer_nr(comp); 287 } 288 289 WARN(1, "Failed to find component for plane %d\n", plane->index); 290 return NULL; 291 } 292 293 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 294 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) 295 { 296 struct cmdq_cb_data *data = mssg; 297 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); 298 struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); 299 struct mtk_crtc_state *state; 300 unsigned int i; 301 unsigned long flags; 302 303 if (data->sta < 0) 304 return; 305 306 state = to_mtk_crtc_state(mtk_crtc->base.state); 307 308 spin_lock_irqsave(&mtk_crtc->config_lock, flags); 309 if (mtk_crtc->config_updating) { 310 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); 311 goto ddp_cmdq_cb_out; 312 } 313 314 state->pending_config = false; 315 316 if (mtk_crtc->pending_planes) { 317 for (i = 0; i < mtk_crtc->layer_nr; i++) { 318 struct drm_plane *plane = &mtk_crtc->planes[i]; 319 struct mtk_plane_state *plane_state; 320 321 plane_state = to_mtk_plane_state(plane->state); 322 323 plane_state->pending.config = false; 324 } 325 mtk_crtc->pending_planes = false; 326 } 327 328 if (mtk_crtc->pending_async_planes) { 329 for (i = 0; i < mtk_crtc->layer_nr; i++) { 330 struct drm_plane *plane = &mtk_crtc->planes[i]; 331 struct mtk_plane_state *plane_state; 332 333 plane_state = to_mtk_plane_state(plane->state); 334 335 plane_state->pending.async_config = false; 336 } 337 mtk_crtc->pending_async_planes = false; 338 } 339 340 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); 341 342 ddp_cmdq_cb_out: 343 344 mtk_crtc->cmdq_vblank_cnt = 0; 345 wake_up(&mtk_crtc->cb_blocking_queue); 346 } 347 #endif 348 349 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 350 { 351 struct drm_crtc *crtc = &mtk_crtc->base; 352 struct drm_connector *connector; 353 struct drm_encoder *encoder; 354 struct drm_connector_list_iter conn_iter; 355 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 356 int ret; 357 int i; 358 359 if (WARN_ON(!crtc->state)) 360 return -EINVAL; 361 362 width = crtc->state->adjusted_mode.hdisplay; 363 height = crtc->state->adjusted_mode.vdisplay; 364 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 365 366 drm_for_each_encoder(encoder, crtc->dev) { 367 if (encoder->crtc != crtc) 368 continue; 369 370 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 371 drm_for_each_connector_iter(connector, &conn_iter) { 372 if (connector->encoder != encoder) 373 continue; 374 if (connector->display_info.bpc != 0 && 375 bpc > connector->display_info.bpc) 376 bpc = connector->display_info.bpc; 377 } 378 drm_connector_list_iter_end(&conn_iter); 379 } 380 381 ret = pm_runtime_resume_and_get(crtc->dev->dev); 382 if (ret < 0) { 383 DRM_ERROR("Failed to enable power domain: %d\n", ret); 384 return ret; 385 } 386 387 ret = mtk_mutex_prepare(mtk_crtc->mutex); 388 if (ret < 0) { 389 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 390 goto err_pm_runtime_put; 391 } 392 393 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 394 if (ret < 0) { 395 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 396 goto err_mutex_unprepare; 397 } 398 399 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 400 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 401 mtk_crtc->ddp_comp[i + 1]->id)) 402 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 403 mtk_crtc->ddp_comp[i]->id, 404 mtk_crtc->ddp_comp[i + 1]->id); 405 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 406 mtk_mutex_add_comp(mtk_crtc->mutex, 407 mtk_crtc->ddp_comp[i]->id); 408 } 409 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 410 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 411 mtk_mutex_enable(mtk_crtc->mutex); 412 413 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 414 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 415 416 if (i == 1) 417 mtk_ddp_comp_bgclr_in_on(comp); 418 419 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 420 mtk_ddp_comp_start(comp); 421 } 422 423 /* Initially configure all planes */ 424 for (i = 0; i < mtk_crtc->layer_nr; i++) { 425 struct drm_plane *plane = &mtk_crtc->planes[i]; 426 struct mtk_plane_state *plane_state; 427 struct mtk_ddp_comp *comp; 428 unsigned int local_layer; 429 430 plane_state = to_mtk_plane_state(plane->state); 431 432 /* should not enable layer before crtc enabled */ 433 plane_state->pending.enable = false; 434 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 435 if (comp) 436 mtk_ddp_comp_layer_config(comp, local_layer, 437 plane_state, NULL); 438 } 439 440 return 0; 441 442 err_mutex_unprepare: 443 mtk_mutex_unprepare(mtk_crtc->mutex); 444 err_pm_runtime_put: 445 pm_runtime_put(crtc->dev->dev); 446 return ret; 447 } 448 449 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 450 { 451 struct drm_device *drm = mtk_crtc->base.dev; 452 struct drm_crtc *crtc = &mtk_crtc->base; 453 unsigned long flags; 454 int i; 455 456 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 457 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 458 if (i == 1) 459 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 460 } 461 462 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 463 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 464 mtk_mutex_remove_comp(mtk_crtc->mutex, 465 mtk_crtc->ddp_comp[i]->id); 466 mtk_mutex_disable(mtk_crtc->mutex); 467 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 468 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 469 mtk_crtc->ddp_comp[i + 1]->id)) 470 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 471 mtk_crtc->ddp_comp[i]->id, 472 mtk_crtc->ddp_comp[i + 1]->id); 473 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 474 mtk_mutex_remove_comp(mtk_crtc->mutex, 475 mtk_crtc->ddp_comp[i]->id); 476 } 477 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 478 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 479 mtk_crtc_ddp_clk_disable(mtk_crtc); 480 mtk_mutex_unprepare(mtk_crtc->mutex); 481 482 pm_runtime_put(drm->dev); 483 484 if (crtc->state->event && !crtc->state->active) { 485 spin_lock_irqsave(&crtc->dev->event_lock, flags); 486 drm_crtc_send_vblank_event(crtc, crtc->state->event); 487 crtc->state->event = NULL; 488 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 489 } 490 } 491 492 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 493 struct cmdq_pkt *cmdq_handle) 494 { 495 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 496 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 497 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 498 unsigned int i; 499 unsigned int local_layer; 500 501 /* 502 * TODO: instead of updating the registers here, we should prepare 503 * working registers in atomic_commit and let the hardware command 504 * queue update module registers on vblank. 505 */ 506 if (state->pending_config) { 507 mtk_ddp_comp_config(comp, state->pending_width, 508 state->pending_height, 509 state->pending_vrefresh, 0, 510 cmdq_handle); 511 512 if (!cmdq_handle) 513 state->pending_config = false; 514 } 515 516 if (mtk_crtc->pending_planes) { 517 for (i = 0; i < mtk_crtc->layer_nr; i++) { 518 struct drm_plane *plane = &mtk_crtc->planes[i]; 519 struct mtk_plane_state *plane_state; 520 521 plane_state = to_mtk_plane_state(plane->state); 522 523 if (!plane_state->pending.config) 524 continue; 525 526 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 527 &local_layer); 528 529 if (comp) 530 mtk_ddp_comp_layer_config(comp, local_layer, 531 plane_state, 532 cmdq_handle); 533 if (!cmdq_handle) 534 plane_state->pending.config = false; 535 } 536 537 if (!cmdq_handle) 538 mtk_crtc->pending_planes = false; 539 } 540 541 if (mtk_crtc->pending_async_planes) { 542 for (i = 0; i < mtk_crtc->layer_nr; i++) { 543 struct drm_plane *plane = &mtk_crtc->planes[i]; 544 struct mtk_plane_state *plane_state; 545 546 plane_state = to_mtk_plane_state(plane->state); 547 548 if (!plane_state->pending.async_config) 549 continue; 550 551 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 552 &local_layer); 553 554 if (comp) 555 mtk_ddp_comp_layer_config(comp, local_layer, 556 plane_state, 557 cmdq_handle); 558 if (!cmdq_handle) 559 plane_state->pending.async_config = false; 560 } 561 562 if (!cmdq_handle) 563 mtk_crtc->pending_async_planes = false; 564 } 565 } 566 567 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 568 bool needs_vblank) 569 { 570 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 571 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle; 572 #endif 573 struct drm_crtc *crtc = &mtk_crtc->base; 574 struct mtk_drm_private *priv = crtc->dev->dev_private; 575 unsigned int pending_planes = 0, pending_async_planes = 0; 576 int i; 577 unsigned long flags; 578 579 mutex_lock(&mtk_crtc->hw_lock); 580 581 spin_lock_irqsave(&mtk_crtc->config_lock, flags); 582 mtk_crtc->config_updating = true; 583 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); 584 585 if (needs_vblank) 586 mtk_crtc->pending_needs_vblank = true; 587 588 for (i = 0; i < mtk_crtc->layer_nr; i++) { 589 struct drm_plane *plane = &mtk_crtc->planes[i]; 590 struct mtk_plane_state *plane_state; 591 592 plane_state = to_mtk_plane_state(plane->state); 593 if (plane_state->pending.dirty) { 594 plane_state->pending.config = true; 595 plane_state->pending.dirty = false; 596 pending_planes |= BIT(i); 597 } else if (plane_state->pending.async_dirty) { 598 plane_state->pending.async_config = true; 599 plane_state->pending.async_dirty = false; 600 pending_async_planes |= BIT(i); 601 } 602 } 603 if (pending_planes) 604 mtk_crtc->pending_planes = true; 605 if (pending_async_planes) 606 mtk_crtc->pending_async_planes = true; 607 608 if (priv->data->shadow_register) { 609 mtk_mutex_acquire(mtk_crtc->mutex); 610 mtk_crtc_ddp_config(crtc, NULL); 611 mtk_mutex_release(mtk_crtc->mutex); 612 } 613 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 614 if (mtk_crtc->cmdq_client.chan) { 615 mbox_flush(mtk_crtc->cmdq_client.chan, 2000); 616 cmdq_handle->cmd_buf_size = 0; 617 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 618 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 619 mtk_crtc_ddp_config(crtc, cmdq_handle); 620 cmdq_pkt_finalize(cmdq_handle); 621 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev, 622 cmdq_handle->pa_base, 623 cmdq_handle->cmd_buf_size, 624 DMA_TO_DEVICE); 625 /* 626 * CMDQ command should execute in next 3 vblank. 627 * One vblank interrupt before send message (occasionally) 628 * and one vblank interrupt after cmdq done, 629 * so it's timeout after 3 vblank interrupt. 630 * If it fail to execute in next 3 vblank, timeout happen. 631 */ 632 mtk_crtc->cmdq_vblank_cnt = 3; 633 634 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); 635 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); 636 } 637 #endif 638 spin_lock_irqsave(&mtk_crtc->config_lock, flags); 639 mtk_crtc->config_updating = false; 640 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); 641 642 mutex_unlock(&mtk_crtc->hw_lock); 643 } 644 645 static void mtk_crtc_ddp_irq(void *data) 646 { 647 struct drm_crtc *crtc = data; 648 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 649 struct mtk_drm_private *priv = crtc->dev->dev_private; 650 651 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 652 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) 653 mtk_crtc_ddp_config(crtc, NULL); 654 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) 655 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", 656 drm_crtc_index(&mtk_crtc->base)); 657 #else 658 if (!priv->data->shadow_register) 659 mtk_crtc_ddp_config(crtc, NULL); 660 #endif 661 mtk_drm_finish_page_flip(mtk_crtc); 662 } 663 664 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 665 { 666 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 667 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 668 669 mtk_ddp_comp_enable_vblank(comp); 670 671 return 0; 672 } 673 674 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 675 { 676 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 677 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 678 679 mtk_ddp_comp_disable_vblank(comp); 680 } 681 682 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 683 struct mtk_plane_state *state) 684 { 685 unsigned int local_layer; 686 struct mtk_ddp_comp *comp; 687 688 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 689 if (comp) 690 return mtk_ddp_comp_layer_check(comp, local_layer, state); 691 return 0; 692 } 693 694 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 695 struct drm_atomic_state *state) 696 { 697 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 698 699 if (!mtk_crtc->enabled) 700 return; 701 702 mtk_drm_crtc_update_config(mtk_crtc, false); 703 } 704 705 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 706 struct drm_atomic_state *state) 707 { 708 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 709 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 710 int ret; 711 712 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 713 714 ret = pm_runtime_resume_and_get(comp->dev); 715 if (ret < 0) { 716 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret); 717 return; 718 } 719 720 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 721 if (ret) { 722 pm_runtime_put(comp->dev); 723 return; 724 } 725 726 drm_crtc_vblank_on(crtc); 727 mtk_crtc->enabled = true; 728 } 729 730 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 731 struct drm_atomic_state *state) 732 { 733 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 734 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 735 int i, ret; 736 737 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 738 if (!mtk_crtc->enabled) 739 return; 740 741 /* Set all pending plane state to disabled */ 742 for (i = 0; i < mtk_crtc->layer_nr; i++) { 743 struct drm_plane *plane = &mtk_crtc->planes[i]; 744 struct mtk_plane_state *plane_state; 745 746 plane_state = to_mtk_plane_state(plane->state); 747 plane_state->pending.enable = false; 748 plane_state->pending.config = true; 749 } 750 mtk_crtc->pending_planes = true; 751 752 mtk_drm_crtc_update_config(mtk_crtc, false); 753 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 754 /* Wait for planes to be disabled by cmdq */ 755 if (mtk_crtc->cmdq_client.chan) 756 wait_event_timeout(mtk_crtc->cb_blocking_queue, 757 mtk_crtc->cmdq_vblank_cnt == 0, 758 msecs_to_jiffies(500)); 759 #endif 760 /* Wait for planes to be disabled */ 761 drm_crtc_wait_one_vblank(crtc); 762 763 drm_crtc_vblank_off(crtc); 764 mtk_crtc_ddp_hw_fini(mtk_crtc); 765 ret = pm_runtime_put(comp->dev); 766 if (ret < 0) 767 DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret); 768 769 mtk_crtc->enabled = false; 770 } 771 772 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 773 struct drm_atomic_state *state) 774 { 775 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 776 crtc); 777 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 778 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 779 unsigned long flags; 780 781 if (mtk_crtc->event && mtk_crtc_state->base.event) 782 DRM_ERROR("new event while there is still a pending event\n"); 783 784 if (mtk_crtc_state->base.event) { 785 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 786 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 787 788 spin_lock_irqsave(&crtc->dev->event_lock, flags); 789 mtk_crtc->event = mtk_crtc_state->base.event; 790 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 791 792 mtk_crtc_state->base.event = NULL; 793 } 794 } 795 796 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 797 struct drm_atomic_state *state) 798 { 799 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 800 int i; 801 802 if (crtc->state->color_mgmt_changed) 803 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 804 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 805 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 806 } 807 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event); 808 } 809 810 static const struct drm_crtc_funcs mtk_crtc_funcs = { 811 .set_config = drm_atomic_helper_set_config, 812 .page_flip = drm_atomic_helper_page_flip, 813 .destroy = mtk_drm_crtc_destroy, 814 .reset = mtk_drm_crtc_reset, 815 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 816 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 817 .enable_vblank = mtk_drm_crtc_enable_vblank, 818 .disable_vblank = mtk_drm_crtc_disable_vblank, 819 }; 820 821 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 822 .mode_fixup = mtk_drm_crtc_mode_fixup, 823 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 824 .atomic_begin = mtk_drm_crtc_atomic_begin, 825 .atomic_flush = mtk_drm_crtc_atomic_flush, 826 .atomic_enable = mtk_drm_crtc_atomic_enable, 827 .atomic_disable = mtk_drm_crtc_atomic_disable, 828 }; 829 830 static int mtk_drm_crtc_init(struct drm_device *drm, 831 struct mtk_drm_crtc *mtk_crtc, 832 unsigned int pipe) 833 { 834 struct drm_plane *primary = NULL; 835 struct drm_plane *cursor = NULL; 836 int i, ret; 837 838 for (i = 0; i < mtk_crtc->layer_nr; i++) { 839 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 840 primary = &mtk_crtc->planes[i]; 841 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 842 cursor = &mtk_crtc->planes[i]; 843 } 844 845 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 846 &mtk_crtc_funcs, NULL); 847 if (ret) 848 goto err_cleanup_crtc; 849 850 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 851 852 return 0; 853 854 err_cleanup_crtc: 855 drm_crtc_cleanup(&mtk_crtc->base); 856 return ret; 857 } 858 859 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 860 int comp_idx) 861 { 862 struct mtk_ddp_comp *comp; 863 864 if (comp_idx > 1) 865 return 0; 866 867 comp = mtk_crtc->ddp_comp[comp_idx]; 868 if (!comp->funcs) 869 return 0; 870 871 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 872 return 0; 873 874 return mtk_ddp_comp_layer_nr(comp); 875 } 876 877 static inline 878 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 879 unsigned int num_planes) 880 { 881 if (plane_idx == 0) 882 return DRM_PLANE_TYPE_PRIMARY; 883 else if (plane_idx == (num_planes - 1)) 884 return DRM_PLANE_TYPE_CURSOR; 885 else 886 return DRM_PLANE_TYPE_OVERLAY; 887 888 } 889 890 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 891 struct mtk_drm_crtc *mtk_crtc, 892 int comp_idx, int pipe) 893 { 894 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 895 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 896 int i, ret; 897 898 for (i = 0; i < num_planes; i++) { 899 ret = mtk_plane_init(drm_dev, 900 &mtk_crtc->planes[mtk_crtc->layer_nr], 901 BIT(pipe), 902 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 903 num_planes), 904 mtk_ddp_comp_supported_rotations(comp), 905 mtk_ddp_comp_get_formats(comp), 906 mtk_ddp_comp_get_num_formats(comp)); 907 if (ret) 908 return ret; 909 910 mtk_crtc->layer_nr++; 911 } 912 return 0; 913 } 914 915 struct device *mtk_drm_crtc_dma_dev_get(struct drm_crtc *crtc) 916 { 917 struct mtk_drm_crtc *mtk_crtc = NULL; 918 919 if (!crtc) 920 return NULL; 921 922 mtk_crtc = to_mtk_crtc(crtc); 923 if (!mtk_crtc) 924 return NULL; 925 926 return mtk_crtc->dma_dev; 927 } 928 929 int mtk_drm_crtc_create(struct drm_device *drm_dev, 930 const unsigned int *path, unsigned int path_len, 931 int priv_data_index) 932 { 933 struct mtk_drm_private *priv = drm_dev->dev_private; 934 struct device *dev = drm_dev->dev; 935 struct mtk_drm_crtc *mtk_crtc; 936 unsigned int num_comp_planes = 0; 937 int ret; 938 int i; 939 bool has_ctm = false; 940 uint gamma_lut_size = 0; 941 struct drm_crtc *tmp; 942 int crtc_i = 0; 943 944 if (!path) 945 return 0; 946 947 priv = priv->all_drm_private[priv_data_index]; 948 949 drm_for_each_crtc(tmp, drm_dev) 950 crtc_i++; 951 952 for (i = 0; i < path_len; i++) { 953 enum mtk_ddp_comp_id comp_id = path[i]; 954 struct device_node *node; 955 struct mtk_ddp_comp *comp; 956 957 node = priv->comp_node[comp_id]; 958 comp = &priv->ddp_comp[comp_id]; 959 960 /* Not all drm components have a DTS device node, such as ovl_adaptor, 961 * which is the drm bring up sub driver 962 */ 963 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) { 964 dev_info(dev, 965 "Not creating crtc %d because component %d is disabled or missing\n", 966 crtc_i, comp_id); 967 return 0; 968 } 969 970 if (!comp->dev) { 971 dev_err(dev, "Component %pOF not initialized\n", node); 972 return -ENODEV; 973 } 974 } 975 976 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 977 if (!mtk_crtc) 978 return -ENOMEM; 979 980 mtk_crtc->mmsys_dev = priv->mmsys_dev; 981 mtk_crtc->ddp_comp_nr = path_len; 982 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 983 sizeof(*mtk_crtc->ddp_comp), 984 GFP_KERNEL); 985 if (!mtk_crtc->ddp_comp) 986 return -ENOMEM; 987 988 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); 989 if (IS_ERR(mtk_crtc->mutex)) { 990 ret = PTR_ERR(mtk_crtc->mutex); 991 dev_err(dev, "Failed to get mutex: %d\n", ret); 992 return ret; 993 } 994 995 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 996 unsigned int comp_id = path[i]; 997 struct mtk_ddp_comp *comp; 998 999 comp = &priv->ddp_comp[comp_id]; 1000 mtk_crtc->ddp_comp[i] = comp; 1001 1002 if (comp->funcs) { 1003 if (comp->funcs->gamma_set) 1004 gamma_lut_size = MTK_LUT_SIZE; 1005 1006 if (comp->funcs->ctm_set) 1007 has_ctm = true; 1008 } 1009 1010 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, 1011 &mtk_crtc->base); 1012 } 1013 1014 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 1015 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 1016 1017 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 1018 sizeof(struct drm_plane), GFP_KERNEL); 1019 if (!mtk_crtc->planes) 1020 return -ENOMEM; 1021 1022 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 1023 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 1024 crtc_i); 1025 if (ret) 1026 return ret; 1027 } 1028 1029 /* 1030 * Default to use the first component as the dma dev. 1031 * In the case of ovl_adaptor sub driver, it needs to use the 1032 * dma_dev_get function to get representative dma dev. 1033 */ 1034 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]); 1035 1036 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i); 1037 if (ret < 0) 1038 return ret; 1039 1040 if (gamma_lut_size) 1041 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 1042 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 1043 mutex_init(&mtk_crtc->hw_lock); 1044 spin_lock_init(&mtk_crtc->config_lock); 1045 1046 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 1047 i = priv->mbox_index++; 1048 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev; 1049 mtk_crtc->cmdq_client.client.tx_block = false; 1050 mtk_crtc->cmdq_client.client.knows_txdone = true; 1051 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb; 1052 mtk_crtc->cmdq_client.chan = 1053 mbox_request_channel(&mtk_crtc->cmdq_client.client, i); 1054 if (IS_ERR(mtk_crtc->cmdq_client.chan)) { 1055 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 1056 drm_crtc_index(&mtk_crtc->base)); 1057 mtk_crtc->cmdq_client.chan = NULL; 1058 } 1059 1060 if (mtk_crtc->cmdq_client.chan) { 1061 ret = of_property_read_u32_index(priv->mutex_node, 1062 "mediatek,gce-events", 1063 i, 1064 &mtk_crtc->cmdq_event); 1065 if (ret) { 1066 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 1067 drm_crtc_index(&mtk_crtc->base)); 1068 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1069 mtk_crtc->cmdq_client.chan = NULL; 1070 } else { 1071 ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client, 1072 &mtk_crtc->cmdq_handle, 1073 PAGE_SIZE); 1074 if (ret) { 1075 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n", 1076 drm_crtc_index(&mtk_crtc->base)); 1077 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1078 mtk_crtc->cmdq_client.chan = NULL; 1079 } 1080 } 1081 1082 /* for sending blocking cmd in crtc disable */ 1083 init_waitqueue_head(&mtk_crtc->cb_blocking_queue); 1084 } 1085 #endif 1086 return 0; 1087 } 1088