1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 #include <linux/soc/mediatek/mtk-cmdq.h> 9 #include <linux/soc/mediatek/mtk-mmsys.h> 10 #include <linux/soc/mediatek/mtk-mutex.h> 11 12 #include <asm/barrier.h> 13 #include <soc/mediatek/smi.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_plane_helper.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_vblank.h> 20 21 #include "mtk_drm_drv.h" 22 #include "mtk_drm_crtc.h" 23 #include "mtk_drm_ddp_comp.h" 24 #include "mtk_drm_gem.h" 25 #include "mtk_drm_plane.h" 26 27 /* 28 * struct mtk_drm_crtc - MediaTek specific crtc structure. 29 * @base: crtc object. 30 * @enabled: records whether crtc_enable succeeded 31 * @planes: array of 4 drm_plane structures, one for each overlay plane 32 * @pending_planes: whether any plane has pending changes to be applied 33 * @mmsys_dev: pointer to the mmsys device for configuration registers 34 * @mutex: handle to one of the ten disp_mutex streams 35 * @ddp_comp_nr: number of components in ddp_comp 36 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 37 * 38 * TODO: Needs update: this header is missing a bunch of member descriptions. 39 */ 40 struct mtk_drm_crtc { 41 struct drm_crtc base; 42 bool enabled; 43 44 bool pending_needs_vblank; 45 struct drm_pending_vblank_event *event; 46 47 struct drm_plane *planes; 48 unsigned int layer_nr; 49 bool pending_planes; 50 bool pending_async_planes; 51 52 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 53 struct cmdq_client *cmdq_client; 54 u32 cmdq_event; 55 #endif 56 57 struct device *mmsys_dev; 58 struct mtk_mutex *mutex; 59 unsigned int ddp_comp_nr; 60 struct mtk_ddp_comp **ddp_comp; 61 62 /* lock for display hardware access */ 63 struct mutex hw_lock; 64 }; 65 66 struct mtk_crtc_state { 67 struct drm_crtc_state base; 68 69 bool pending_config; 70 unsigned int pending_width; 71 unsigned int pending_height; 72 unsigned int pending_vrefresh; 73 }; 74 75 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 76 { 77 return container_of(c, struct mtk_drm_crtc, base); 78 } 79 80 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 81 { 82 return container_of(s, struct mtk_crtc_state, base); 83 } 84 85 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 86 { 87 struct drm_crtc *crtc = &mtk_crtc->base; 88 unsigned long flags; 89 90 spin_lock_irqsave(&crtc->dev->event_lock, flags); 91 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 92 drm_crtc_vblank_put(crtc); 93 mtk_crtc->event = NULL; 94 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 95 } 96 97 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 98 { 99 drm_crtc_handle_vblank(&mtk_crtc->base); 100 if (mtk_crtc->pending_needs_vblank) { 101 mtk_drm_crtc_finish_page_flip(mtk_crtc); 102 mtk_crtc->pending_needs_vblank = false; 103 } 104 } 105 106 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 107 { 108 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 109 110 mtk_mutex_put(mtk_crtc->mutex); 111 112 drm_crtc_cleanup(crtc); 113 } 114 115 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 116 { 117 struct mtk_crtc_state *state; 118 119 if (crtc->state) 120 __drm_atomic_helper_crtc_destroy_state(crtc->state); 121 122 kfree(to_mtk_crtc_state(crtc->state)); 123 crtc->state = NULL; 124 125 state = kzalloc(sizeof(*state), GFP_KERNEL); 126 if (state) 127 __drm_atomic_helper_crtc_reset(crtc, &state->base); 128 } 129 130 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 131 { 132 struct mtk_crtc_state *state; 133 134 state = kzalloc(sizeof(*state), GFP_KERNEL); 135 if (!state) 136 return NULL; 137 138 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 139 140 WARN_ON(state->base.crtc != crtc); 141 state->base.crtc = crtc; 142 143 return &state->base; 144 } 145 146 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 147 struct drm_crtc_state *state) 148 { 149 __drm_atomic_helper_crtc_destroy_state(state); 150 kfree(to_mtk_crtc_state(state)); 151 } 152 153 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 154 const struct drm_display_mode *mode, 155 struct drm_display_mode *adjusted_mode) 156 { 157 /* Nothing to do here, but this callback is mandatory. */ 158 return true; 159 } 160 161 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 162 { 163 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 164 165 state->pending_width = crtc->mode.hdisplay; 166 state->pending_height = crtc->mode.vdisplay; 167 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 168 wmb(); /* Make sure the above parameters are set before update */ 169 state->pending_config = true; 170 } 171 172 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 173 { 174 int ret; 175 int i; 176 177 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 178 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 179 if (ret) { 180 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 181 goto err; 182 } 183 } 184 185 return 0; 186 err: 187 while (--i >= 0) 188 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 189 return ret; 190 } 191 192 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 193 { 194 int i; 195 196 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 197 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 198 } 199 200 static 201 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 202 struct drm_plane *plane, 203 unsigned int *local_layer) 204 { 205 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 206 struct mtk_ddp_comp *comp; 207 int i, count = 0; 208 unsigned int local_index = plane - mtk_crtc->planes; 209 210 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 211 comp = mtk_crtc->ddp_comp[i]; 212 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 213 *local_layer = local_index - count; 214 return comp; 215 } 216 count += mtk_ddp_comp_layer_nr(comp); 217 } 218 219 WARN(1, "Failed to find component for plane %d\n", plane->index); 220 return NULL; 221 } 222 223 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 224 static void ddp_cmdq_cb(struct cmdq_cb_data data) 225 { 226 cmdq_pkt_destroy(data.data); 227 } 228 #endif 229 230 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 231 { 232 struct drm_crtc *crtc = &mtk_crtc->base; 233 struct drm_connector *connector; 234 struct drm_encoder *encoder; 235 struct drm_connector_list_iter conn_iter; 236 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 237 int ret; 238 int i; 239 240 if (WARN_ON(!crtc->state)) 241 return -EINVAL; 242 243 width = crtc->state->adjusted_mode.hdisplay; 244 height = crtc->state->adjusted_mode.vdisplay; 245 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 246 247 drm_for_each_encoder(encoder, crtc->dev) { 248 if (encoder->crtc != crtc) 249 continue; 250 251 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 252 drm_for_each_connector_iter(connector, &conn_iter) { 253 if (connector->encoder != encoder) 254 continue; 255 if (connector->display_info.bpc != 0 && 256 bpc > connector->display_info.bpc) 257 bpc = connector->display_info.bpc; 258 } 259 drm_connector_list_iter_end(&conn_iter); 260 } 261 262 ret = pm_runtime_get_sync(crtc->dev->dev); 263 if (ret < 0) { 264 DRM_ERROR("Failed to enable power domain: %d\n", ret); 265 return ret; 266 } 267 268 ret = mtk_mutex_prepare(mtk_crtc->mutex); 269 if (ret < 0) { 270 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 271 goto err_pm_runtime_put; 272 } 273 274 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 275 if (ret < 0) { 276 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 277 goto err_mutex_unprepare; 278 } 279 280 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 281 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 282 mtk_crtc->ddp_comp[i]->id, 283 mtk_crtc->ddp_comp[i + 1]->id); 284 mtk_mutex_add_comp(mtk_crtc->mutex, 285 mtk_crtc->ddp_comp[i]->id); 286 } 287 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 288 mtk_mutex_enable(mtk_crtc->mutex); 289 290 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 291 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 292 293 if (i == 1) 294 mtk_ddp_comp_bgclr_in_on(comp); 295 296 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 297 mtk_ddp_comp_start(comp); 298 } 299 300 /* Initially configure all planes */ 301 for (i = 0; i < mtk_crtc->layer_nr; i++) { 302 struct drm_plane *plane = &mtk_crtc->planes[i]; 303 struct mtk_plane_state *plane_state; 304 struct mtk_ddp_comp *comp; 305 unsigned int local_layer; 306 307 plane_state = to_mtk_plane_state(plane->state); 308 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 309 if (comp) 310 mtk_ddp_comp_layer_config(comp, local_layer, 311 plane_state, NULL); 312 } 313 314 return 0; 315 316 err_mutex_unprepare: 317 mtk_mutex_unprepare(mtk_crtc->mutex); 318 err_pm_runtime_put: 319 pm_runtime_put(crtc->dev->dev); 320 return ret; 321 } 322 323 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 324 { 325 struct drm_device *drm = mtk_crtc->base.dev; 326 struct drm_crtc *crtc = &mtk_crtc->base; 327 int i; 328 329 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 330 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 331 if (i == 1) 332 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 333 } 334 335 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 336 mtk_mutex_remove_comp(mtk_crtc->mutex, 337 mtk_crtc->ddp_comp[i]->id); 338 mtk_mutex_disable(mtk_crtc->mutex); 339 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 340 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 341 mtk_crtc->ddp_comp[i]->id, 342 mtk_crtc->ddp_comp[i + 1]->id); 343 mtk_mutex_remove_comp(mtk_crtc->mutex, 344 mtk_crtc->ddp_comp[i]->id); 345 } 346 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 347 mtk_crtc_ddp_clk_disable(mtk_crtc); 348 mtk_mutex_unprepare(mtk_crtc->mutex); 349 350 pm_runtime_put(drm->dev); 351 352 if (crtc->state->event && !crtc->state->active) { 353 spin_lock_irq(&crtc->dev->event_lock); 354 drm_crtc_send_vblank_event(crtc, crtc->state->event); 355 crtc->state->event = NULL; 356 spin_unlock_irq(&crtc->dev->event_lock); 357 } 358 } 359 360 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 361 struct cmdq_pkt *cmdq_handle) 362 { 363 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 364 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 365 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 366 unsigned int i; 367 unsigned int local_layer; 368 369 /* 370 * TODO: instead of updating the registers here, we should prepare 371 * working registers in atomic_commit and let the hardware command 372 * queue update module registers on vblank. 373 */ 374 if (state->pending_config) { 375 mtk_ddp_comp_config(comp, state->pending_width, 376 state->pending_height, 377 state->pending_vrefresh, 0, 378 cmdq_handle); 379 380 state->pending_config = false; 381 } 382 383 if (mtk_crtc->pending_planes) { 384 for (i = 0; i < mtk_crtc->layer_nr; i++) { 385 struct drm_plane *plane = &mtk_crtc->planes[i]; 386 struct mtk_plane_state *plane_state; 387 388 plane_state = to_mtk_plane_state(plane->state); 389 390 if (!plane_state->pending.config) 391 continue; 392 393 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 394 &local_layer); 395 396 if (comp) 397 mtk_ddp_comp_layer_config(comp, local_layer, 398 plane_state, 399 cmdq_handle); 400 plane_state->pending.config = false; 401 } 402 mtk_crtc->pending_planes = false; 403 } 404 405 if (mtk_crtc->pending_async_planes) { 406 for (i = 0; i < mtk_crtc->layer_nr; i++) { 407 struct drm_plane *plane = &mtk_crtc->planes[i]; 408 struct mtk_plane_state *plane_state; 409 410 plane_state = to_mtk_plane_state(plane->state); 411 412 if (!plane_state->pending.async_config) 413 continue; 414 415 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 416 &local_layer); 417 418 if (comp) 419 mtk_ddp_comp_layer_config(comp, local_layer, 420 plane_state, 421 cmdq_handle); 422 plane_state->pending.async_config = false; 423 } 424 mtk_crtc->pending_async_planes = false; 425 } 426 } 427 428 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) 429 { 430 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 431 struct cmdq_pkt *cmdq_handle; 432 #endif 433 struct drm_crtc *crtc = &mtk_crtc->base; 434 struct mtk_drm_private *priv = crtc->dev->dev_private; 435 unsigned int pending_planes = 0, pending_async_planes = 0; 436 int i; 437 438 mutex_lock(&mtk_crtc->hw_lock); 439 for (i = 0; i < mtk_crtc->layer_nr; i++) { 440 struct drm_plane *plane = &mtk_crtc->planes[i]; 441 struct mtk_plane_state *plane_state; 442 443 plane_state = to_mtk_plane_state(plane->state); 444 if (plane_state->pending.dirty) { 445 plane_state->pending.config = true; 446 plane_state->pending.dirty = false; 447 pending_planes |= BIT(i); 448 } else if (plane_state->pending.async_dirty) { 449 plane_state->pending.async_config = true; 450 plane_state->pending.async_dirty = false; 451 pending_async_planes |= BIT(i); 452 } 453 } 454 if (pending_planes) 455 mtk_crtc->pending_planes = true; 456 if (pending_async_planes) 457 mtk_crtc->pending_async_planes = true; 458 459 if (priv->data->shadow_register) { 460 mtk_mutex_acquire(mtk_crtc->mutex); 461 mtk_crtc_ddp_config(crtc, NULL); 462 mtk_mutex_release(mtk_crtc->mutex); 463 } 464 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 465 if (mtk_crtc->cmdq_client) { 466 mbox_flush(mtk_crtc->cmdq_client->chan, 2000); 467 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 468 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 469 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 470 mtk_crtc_ddp_config(crtc, cmdq_handle); 471 cmdq_pkt_finalize(cmdq_handle); 472 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 473 } 474 #endif 475 mutex_unlock(&mtk_crtc->hw_lock); 476 } 477 478 static void mtk_crtc_ddp_irq(void *data) 479 { 480 struct drm_crtc *crtc = data; 481 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 482 struct mtk_drm_private *priv = crtc->dev->dev_private; 483 484 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 485 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 486 #else 487 if (!priv->data->shadow_register) 488 #endif 489 mtk_crtc_ddp_config(crtc, NULL); 490 491 mtk_drm_finish_page_flip(mtk_crtc); 492 } 493 494 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 495 { 496 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 497 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 498 499 mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base); 500 501 return 0; 502 } 503 504 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 505 { 506 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 507 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 508 509 mtk_ddp_comp_disable_vblank(comp); 510 } 511 512 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 513 struct mtk_plane_state *state) 514 { 515 unsigned int local_layer; 516 struct mtk_ddp_comp *comp; 517 518 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 519 if (comp) 520 return mtk_ddp_comp_layer_check(comp, local_layer, state); 521 return 0; 522 } 523 524 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 525 struct drm_plane_state *new_state) 526 { 527 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 528 const struct drm_plane_helper_funcs *plane_helper_funcs = 529 plane->helper_private; 530 531 if (!mtk_crtc->enabled) 532 return; 533 534 plane_helper_funcs->atomic_update(plane, new_state); 535 mtk_drm_crtc_hw_config(mtk_crtc); 536 } 537 538 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 539 struct drm_atomic_state *state) 540 { 541 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 542 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 543 int ret; 544 545 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 546 547 ret = mtk_smi_larb_get(comp->larb_dev); 548 if (ret) { 549 DRM_ERROR("Failed to get larb: %d\n", ret); 550 return; 551 } 552 553 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 554 if (ret) { 555 mtk_smi_larb_put(comp->larb_dev); 556 return; 557 } 558 559 drm_crtc_vblank_on(crtc); 560 mtk_crtc->enabled = true; 561 } 562 563 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 564 struct drm_atomic_state *state) 565 { 566 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 567 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 568 int i; 569 570 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 571 if (!mtk_crtc->enabled) 572 return; 573 574 /* Set all pending plane state to disabled */ 575 for (i = 0; i < mtk_crtc->layer_nr; i++) { 576 struct drm_plane *plane = &mtk_crtc->planes[i]; 577 struct mtk_plane_state *plane_state; 578 579 plane_state = to_mtk_plane_state(plane->state); 580 plane_state->pending.enable = false; 581 plane_state->pending.config = true; 582 } 583 mtk_crtc->pending_planes = true; 584 585 mtk_drm_crtc_hw_config(mtk_crtc); 586 /* Wait for planes to be disabled */ 587 drm_crtc_wait_one_vblank(crtc); 588 589 drm_crtc_vblank_off(crtc); 590 mtk_crtc_ddp_hw_fini(mtk_crtc); 591 mtk_smi_larb_put(comp->larb_dev); 592 593 mtk_crtc->enabled = false; 594 } 595 596 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 597 struct drm_atomic_state *state) 598 { 599 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 600 crtc); 601 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 602 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 603 604 if (mtk_crtc->event && mtk_crtc_state->base.event) 605 DRM_ERROR("new event while there is still a pending event\n"); 606 607 if (mtk_crtc_state->base.event) { 608 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 609 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 610 mtk_crtc->event = mtk_crtc_state->base.event; 611 mtk_crtc_state->base.event = NULL; 612 } 613 } 614 615 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 616 struct drm_atomic_state *state) 617 { 618 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 619 int i; 620 621 if (mtk_crtc->event) 622 mtk_crtc->pending_needs_vblank = true; 623 if (crtc->state->color_mgmt_changed) 624 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 625 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 626 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 627 } 628 mtk_drm_crtc_hw_config(mtk_crtc); 629 } 630 631 static const struct drm_crtc_funcs mtk_crtc_funcs = { 632 .set_config = drm_atomic_helper_set_config, 633 .page_flip = drm_atomic_helper_page_flip, 634 .destroy = mtk_drm_crtc_destroy, 635 .reset = mtk_drm_crtc_reset, 636 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 637 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 638 .enable_vblank = mtk_drm_crtc_enable_vblank, 639 .disable_vblank = mtk_drm_crtc_disable_vblank, 640 }; 641 642 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 643 .mode_fixup = mtk_drm_crtc_mode_fixup, 644 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 645 .atomic_begin = mtk_drm_crtc_atomic_begin, 646 .atomic_flush = mtk_drm_crtc_atomic_flush, 647 .atomic_enable = mtk_drm_crtc_atomic_enable, 648 .atomic_disable = mtk_drm_crtc_atomic_disable, 649 }; 650 651 static int mtk_drm_crtc_init(struct drm_device *drm, 652 struct mtk_drm_crtc *mtk_crtc, 653 unsigned int pipe) 654 { 655 struct drm_plane *primary = NULL; 656 struct drm_plane *cursor = NULL; 657 int i, ret; 658 659 for (i = 0; i < mtk_crtc->layer_nr; i++) { 660 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 661 primary = &mtk_crtc->planes[i]; 662 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 663 cursor = &mtk_crtc->planes[i]; 664 } 665 666 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 667 &mtk_crtc_funcs, NULL); 668 if (ret) 669 goto err_cleanup_crtc; 670 671 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 672 673 return 0; 674 675 err_cleanup_crtc: 676 drm_crtc_cleanup(&mtk_crtc->base); 677 return ret; 678 } 679 680 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 681 int comp_idx) 682 { 683 struct mtk_ddp_comp *comp; 684 685 if (comp_idx > 1) 686 return 0; 687 688 comp = mtk_crtc->ddp_comp[comp_idx]; 689 if (!comp->funcs) 690 return 0; 691 692 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 693 return 0; 694 695 return mtk_ddp_comp_layer_nr(comp); 696 } 697 698 static inline 699 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 700 unsigned int num_planes) 701 { 702 if (plane_idx == 0) 703 return DRM_PLANE_TYPE_PRIMARY; 704 else if (plane_idx == (num_planes - 1)) 705 return DRM_PLANE_TYPE_CURSOR; 706 else 707 return DRM_PLANE_TYPE_OVERLAY; 708 709 } 710 711 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 712 struct mtk_drm_crtc *mtk_crtc, 713 int comp_idx, int pipe) 714 { 715 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 716 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 717 int i, ret; 718 719 for (i = 0; i < num_planes; i++) { 720 ret = mtk_plane_init(drm_dev, 721 &mtk_crtc->planes[mtk_crtc->layer_nr], 722 BIT(pipe), 723 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 724 num_planes), 725 mtk_ddp_comp_supported_rotations(comp)); 726 if (ret) 727 return ret; 728 729 mtk_crtc->layer_nr++; 730 } 731 return 0; 732 } 733 734 int mtk_drm_crtc_create(struct drm_device *drm_dev, 735 const enum mtk_ddp_comp_id *path, unsigned int path_len) 736 { 737 struct mtk_drm_private *priv = drm_dev->dev_private; 738 struct device *dev = drm_dev->dev; 739 struct mtk_drm_crtc *mtk_crtc; 740 unsigned int num_comp_planes = 0; 741 int pipe = priv->num_pipes; 742 int ret; 743 int i; 744 bool has_ctm = false; 745 uint gamma_lut_size = 0; 746 747 if (!path) 748 return 0; 749 750 for (i = 0; i < path_len; i++) { 751 enum mtk_ddp_comp_id comp_id = path[i]; 752 struct device_node *node; 753 754 node = priv->comp_node[comp_id]; 755 if (!node) { 756 dev_info(dev, 757 "Not creating crtc %d because component %d is disabled or missing\n", 758 pipe, comp_id); 759 return 0; 760 } 761 } 762 763 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 764 if (!mtk_crtc) 765 return -ENOMEM; 766 767 mtk_crtc->mmsys_dev = priv->mmsys_dev; 768 mtk_crtc->ddp_comp_nr = path_len; 769 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 770 sizeof(*mtk_crtc->ddp_comp), 771 GFP_KERNEL); 772 if (!mtk_crtc->ddp_comp) 773 return -ENOMEM; 774 775 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); 776 if (IS_ERR(mtk_crtc->mutex)) { 777 ret = PTR_ERR(mtk_crtc->mutex); 778 dev_err(dev, "Failed to get mutex: %d\n", ret); 779 return ret; 780 } 781 782 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 783 enum mtk_ddp_comp_id comp_id = path[i]; 784 struct mtk_ddp_comp *comp; 785 struct device_node *node; 786 787 node = priv->comp_node[comp_id]; 788 comp = &priv->ddp_comp[comp_id]; 789 if (!comp) { 790 dev_err(dev, "Component %pOF not initialized\n", node); 791 ret = -ENODEV; 792 return ret; 793 } 794 795 mtk_crtc->ddp_comp[i] = comp; 796 797 if (comp->funcs) { 798 if (comp->funcs->gamma_set) 799 gamma_lut_size = MTK_LUT_SIZE; 800 801 if (comp->funcs->ctm_set) 802 has_ctm = true; 803 } 804 } 805 806 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 807 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 808 809 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 810 sizeof(struct drm_plane), GFP_KERNEL); 811 812 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 813 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 814 pipe); 815 if (ret) 816 return ret; 817 } 818 819 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); 820 if (ret < 0) 821 return ret; 822 823 if (gamma_lut_size) 824 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 825 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 826 priv->num_pipes++; 827 mutex_init(&mtk_crtc->hw_lock); 828 829 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 830 mtk_crtc->cmdq_client = 831 cmdq_mbox_create(mtk_crtc->mmsys_dev, 832 drm_crtc_index(&mtk_crtc->base)); 833 if (IS_ERR(mtk_crtc->cmdq_client)) { 834 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 835 drm_crtc_index(&mtk_crtc->base)); 836 mtk_crtc->cmdq_client = NULL; 837 } 838 839 if (mtk_crtc->cmdq_client) { 840 ret = of_property_read_u32_index(priv->mutex_node, 841 "mediatek,gce-events", 842 drm_crtc_index(&mtk_crtc->base), 843 &mtk_crtc->cmdq_event); 844 if (ret) { 845 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 846 drm_crtc_index(&mtk_crtc->base)); 847 cmdq_mbox_destroy(mtk_crtc->cmdq_client); 848 mtk_crtc->cmdq_client = NULL; 849 } 850 } 851 #endif 852 return 0; 853 } 854