1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/mailbox_controller.h> 9 #include <linux/of.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/soc/mediatek/mtk-cmdq.h> 12 #include <linux/soc/mediatek/mtk-mmsys.h> 13 #include <linux/soc/mediatek/mtk-mutex.h> 14 15 #include <asm/barrier.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_probe_helper.h> 20 #include <drm/drm_vblank.h> 21 22 #include "mtk_drm_drv.h" 23 #include "mtk_drm_crtc.h" 24 #include "mtk_drm_ddp_comp.h" 25 #include "mtk_drm_gem.h" 26 #include "mtk_drm_plane.h" 27 28 /* 29 * struct mtk_drm_crtc - MediaTek specific crtc structure. 30 * @base: crtc object. 31 * @enabled: records whether crtc_enable succeeded 32 * @planes: array of 4 drm_plane structures, one for each overlay plane 33 * @pending_planes: whether any plane has pending changes to be applied 34 * @mmsys_dev: pointer to the mmsys device for configuration registers 35 * @mutex: handle to one of the ten disp_mutex streams 36 * @ddp_comp_nr: number of components in ddp_comp 37 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 38 * 39 * TODO: Needs update: this header is missing a bunch of member descriptions. 40 */ 41 struct mtk_drm_crtc { 42 struct drm_crtc base; 43 bool enabled; 44 45 bool pending_needs_vblank; 46 struct drm_pending_vblank_event *event; 47 48 struct drm_plane *planes; 49 unsigned int layer_nr; 50 bool pending_planes; 51 bool pending_async_planes; 52 53 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 54 struct cmdq_client cmdq_client; 55 struct cmdq_pkt cmdq_handle; 56 u32 cmdq_event; 57 u32 cmdq_vblank_cnt; 58 wait_queue_head_t cb_blocking_queue; 59 #endif 60 61 struct device *mmsys_dev; 62 struct device *dma_dev; 63 struct mtk_mutex *mutex; 64 unsigned int ddp_comp_nr; 65 struct mtk_ddp_comp **ddp_comp; 66 67 /* lock for display hardware access */ 68 struct mutex hw_lock; 69 bool config_updating; 70 }; 71 72 struct mtk_crtc_state { 73 struct drm_crtc_state base; 74 75 bool pending_config; 76 unsigned int pending_width; 77 unsigned int pending_height; 78 unsigned int pending_vrefresh; 79 }; 80 81 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 82 { 83 return container_of(c, struct mtk_drm_crtc, base); 84 } 85 86 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 87 { 88 return container_of(s, struct mtk_crtc_state, base); 89 } 90 91 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 92 { 93 struct drm_crtc *crtc = &mtk_crtc->base; 94 unsigned long flags; 95 96 spin_lock_irqsave(&crtc->dev->event_lock, flags); 97 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 98 drm_crtc_vblank_put(crtc); 99 mtk_crtc->event = NULL; 100 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 101 } 102 103 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 104 { 105 drm_crtc_handle_vblank(&mtk_crtc->base); 106 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) { 107 mtk_drm_crtc_finish_page_flip(mtk_crtc); 108 mtk_crtc->pending_needs_vblank = false; 109 } 110 } 111 112 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 113 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, 114 size_t size) 115 { 116 struct device *dev; 117 dma_addr_t dma_addr; 118 119 pkt->va_base = kzalloc(size, GFP_KERNEL); 120 if (!pkt->va_base) { 121 kfree(pkt); 122 return -ENOMEM; 123 } 124 pkt->buf_size = size; 125 pkt->cl = (void *)client; 126 127 dev = client->chan->mbox->dev; 128 dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, 129 DMA_TO_DEVICE); 130 if (dma_mapping_error(dev, dma_addr)) { 131 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); 132 kfree(pkt->va_base); 133 kfree(pkt); 134 return -ENOMEM; 135 } 136 137 pkt->pa_base = dma_addr; 138 139 return 0; 140 } 141 142 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt) 143 { 144 struct cmdq_client *client = (struct cmdq_client *)pkt->cl; 145 146 dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, 147 DMA_TO_DEVICE); 148 kfree(pkt->va_base); 149 kfree(pkt); 150 } 151 #endif 152 153 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 154 { 155 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 156 int i; 157 158 mtk_mutex_put(mtk_crtc->mutex); 159 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 160 mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle); 161 162 if (mtk_crtc->cmdq_client.chan) { 163 mbox_free_channel(mtk_crtc->cmdq_client.chan); 164 mtk_crtc->cmdq_client.chan = NULL; 165 } 166 #endif 167 168 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 169 struct mtk_ddp_comp *comp; 170 171 comp = mtk_crtc->ddp_comp[i]; 172 mtk_ddp_comp_unregister_vblank_cb(comp); 173 } 174 175 drm_crtc_cleanup(crtc); 176 } 177 178 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 179 { 180 struct mtk_crtc_state *state; 181 182 if (crtc->state) 183 __drm_atomic_helper_crtc_destroy_state(crtc->state); 184 185 kfree(to_mtk_crtc_state(crtc->state)); 186 crtc->state = NULL; 187 188 state = kzalloc(sizeof(*state), GFP_KERNEL); 189 if (state) 190 __drm_atomic_helper_crtc_reset(crtc, &state->base); 191 } 192 193 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 194 { 195 struct mtk_crtc_state *state; 196 197 state = kmalloc(sizeof(*state), GFP_KERNEL); 198 if (!state) 199 return NULL; 200 201 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 202 203 WARN_ON(state->base.crtc != crtc); 204 state->base.crtc = crtc; 205 state->pending_config = false; 206 207 return &state->base; 208 } 209 210 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 211 struct drm_crtc_state *state) 212 { 213 __drm_atomic_helper_crtc_destroy_state(state); 214 kfree(to_mtk_crtc_state(state)); 215 } 216 217 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 218 const struct drm_display_mode *mode, 219 struct drm_display_mode *adjusted_mode) 220 { 221 /* Nothing to do here, but this callback is mandatory. */ 222 return true; 223 } 224 225 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 226 { 227 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 228 229 state->pending_width = crtc->mode.hdisplay; 230 state->pending_height = crtc->mode.vdisplay; 231 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 232 wmb(); /* Make sure the above parameters are set before update */ 233 state->pending_config = true; 234 } 235 236 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 237 { 238 int ret; 239 int i; 240 241 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 242 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 243 if (ret) { 244 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 245 goto err; 246 } 247 } 248 249 return 0; 250 err: 251 while (--i >= 0) 252 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 253 return ret; 254 } 255 256 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 257 { 258 int i; 259 260 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 261 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); 262 } 263 264 static 265 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 266 struct drm_plane *plane, 267 unsigned int *local_layer) 268 { 269 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 270 struct mtk_ddp_comp *comp; 271 int i, count = 0; 272 unsigned int local_index = plane - mtk_crtc->planes; 273 274 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 275 comp = mtk_crtc->ddp_comp[i]; 276 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 277 *local_layer = local_index - count; 278 return comp; 279 } 280 count += mtk_ddp_comp_layer_nr(comp); 281 } 282 283 WARN(1, "Failed to find component for plane %d\n", plane->index); 284 return NULL; 285 } 286 287 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 288 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) 289 { 290 struct cmdq_cb_data *data = mssg; 291 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client); 292 struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client); 293 struct mtk_crtc_state *state; 294 unsigned int i; 295 296 if (data->sta < 0) 297 return; 298 299 state = to_mtk_crtc_state(mtk_crtc->base.state); 300 301 state->pending_config = false; 302 303 if (mtk_crtc->pending_planes) { 304 for (i = 0; i < mtk_crtc->layer_nr; i++) { 305 struct drm_plane *plane = &mtk_crtc->planes[i]; 306 struct mtk_plane_state *plane_state; 307 308 plane_state = to_mtk_plane_state(plane->state); 309 310 plane_state->pending.config = false; 311 } 312 mtk_crtc->pending_planes = false; 313 } 314 315 if (mtk_crtc->pending_async_planes) { 316 for (i = 0; i < mtk_crtc->layer_nr; i++) { 317 struct drm_plane *plane = &mtk_crtc->planes[i]; 318 struct mtk_plane_state *plane_state; 319 320 plane_state = to_mtk_plane_state(plane->state); 321 322 plane_state->pending.async_config = false; 323 } 324 mtk_crtc->pending_async_planes = false; 325 } 326 327 mtk_crtc->cmdq_vblank_cnt = 0; 328 wake_up(&mtk_crtc->cb_blocking_queue); 329 } 330 #endif 331 332 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 333 { 334 struct drm_crtc *crtc = &mtk_crtc->base; 335 struct drm_connector *connector; 336 struct drm_encoder *encoder; 337 struct drm_connector_list_iter conn_iter; 338 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 339 int ret; 340 int i; 341 342 if (WARN_ON(!crtc->state)) 343 return -EINVAL; 344 345 width = crtc->state->adjusted_mode.hdisplay; 346 height = crtc->state->adjusted_mode.vdisplay; 347 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 348 349 drm_for_each_encoder(encoder, crtc->dev) { 350 if (encoder->crtc != crtc) 351 continue; 352 353 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 354 drm_for_each_connector_iter(connector, &conn_iter) { 355 if (connector->encoder != encoder) 356 continue; 357 if (connector->display_info.bpc != 0 && 358 bpc > connector->display_info.bpc) 359 bpc = connector->display_info.bpc; 360 } 361 drm_connector_list_iter_end(&conn_iter); 362 } 363 364 ret = pm_runtime_resume_and_get(crtc->dev->dev); 365 if (ret < 0) { 366 DRM_ERROR("Failed to enable power domain: %d\n", ret); 367 return ret; 368 } 369 370 ret = mtk_mutex_prepare(mtk_crtc->mutex); 371 if (ret < 0) { 372 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 373 goto err_pm_runtime_put; 374 } 375 376 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 377 if (ret < 0) { 378 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 379 goto err_mutex_unprepare; 380 } 381 382 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 383 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 384 mtk_crtc->ddp_comp[i + 1]->id)) 385 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 386 mtk_crtc->ddp_comp[i]->id, 387 mtk_crtc->ddp_comp[i + 1]->id); 388 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 389 mtk_mutex_add_comp(mtk_crtc->mutex, 390 mtk_crtc->ddp_comp[i]->id); 391 } 392 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 393 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 394 mtk_mutex_enable(mtk_crtc->mutex); 395 396 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 397 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 398 399 if (i == 1) 400 mtk_ddp_comp_bgclr_in_on(comp); 401 402 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 403 mtk_ddp_comp_start(comp); 404 } 405 406 /* Initially configure all planes */ 407 for (i = 0; i < mtk_crtc->layer_nr; i++) { 408 struct drm_plane *plane = &mtk_crtc->planes[i]; 409 struct mtk_plane_state *plane_state; 410 struct mtk_ddp_comp *comp; 411 unsigned int local_layer; 412 413 plane_state = to_mtk_plane_state(plane->state); 414 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 415 if (comp) 416 mtk_ddp_comp_layer_config(comp, local_layer, 417 plane_state, NULL); 418 } 419 420 return 0; 421 422 err_mutex_unprepare: 423 mtk_mutex_unprepare(mtk_crtc->mutex); 424 err_pm_runtime_put: 425 pm_runtime_put(crtc->dev->dev); 426 return ret; 427 } 428 429 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 430 { 431 struct drm_device *drm = mtk_crtc->base.dev; 432 struct drm_crtc *crtc = &mtk_crtc->base; 433 int i; 434 435 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 436 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 437 if (i == 1) 438 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 439 } 440 441 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 442 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 443 mtk_mutex_remove_comp(mtk_crtc->mutex, 444 mtk_crtc->ddp_comp[i]->id); 445 mtk_mutex_disable(mtk_crtc->mutex); 446 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 447 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, 448 mtk_crtc->ddp_comp[i + 1]->id)) 449 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 450 mtk_crtc->ddp_comp[i]->id, 451 mtk_crtc->ddp_comp[i + 1]->id); 452 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 453 mtk_mutex_remove_comp(mtk_crtc->mutex, 454 mtk_crtc->ddp_comp[i]->id); 455 } 456 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) 457 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 458 mtk_crtc_ddp_clk_disable(mtk_crtc); 459 mtk_mutex_unprepare(mtk_crtc->mutex); 460 461 pm_runtime_put(drm->dev); 462 463 if (crtc->state->event && !crtc->state->active) { 464 spin_lock_irq(&crtc->dev->event_lock); 465 drm_crtc_send_vblank_event(crtc, crtc->state->event); 466 crtc->state->event = NULL; 467 spin_unlock_irq(&crtc->dev->event_lock); 468 } 469 } 470 471 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 472 struct cmdq_pkt *cmdq_handle) 473 { 474 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 475 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 476 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 477 unsigned int i; 478 unsigned int local_layer; 479 480 /* 481 * TODO: instead of updating the registers here, we should prepare 482 * working registers in atomic_commit and let the hardware command 483 * queue update module registers on vblank. 484 */ 485 if (state->pending_config) { 486 mtk_ddp_comp_config(comp, state->pending_width, 487 state->pending_height, 488 state->pending_vrefresh, 0, 489 cmdq_handle); 490 491 if (!cmdq_handle) 492 state->pending_config = false; 493 } 494 495 if (mtk_crtc->pending_planes) { 496 for (i = 0; i < mtk_crtc->layer_nr; i++) { 497 struct drm_plane *plane = &mtk_crtc->planes[i]; 498 struct mtk_plane_state *plane_state; 499 500 plane_state = to_mtk_plane_state(plane->state); 501 502 if (!plane_state->pending.config) 503 continue; 504 505 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 506 &local_layer); 507 508 if (comp) 509 mtk_ddp_comp_layer_config(comp, local_layer, 510 plane_state, 511 cmdq_handle); 512 if (!cmdq_handle) 513 plane_state->pending.config = false; 514 } 515 516 if (!cmdq_handle) 517 mtk_crtc->pending_planes = false; 518 } 519 520 if (mtk_crtc->pending_async_planes) { 521 for (i = 0; i < mtk_crtc->layer_nr; i++) { 522 struct drm_plane *plane = &mtk_crtc->planes[i]; 523 struct mtk_plane_state *plane_state; 524 525 plane_state = to_mtk_plane_state(plane->state); 526 527 if (!plane_state->pending.async_config) 528 continue; 529 530 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 531 &local_layer); 532 533 if (comp) 534 mtk_ddp_comp_layer_config(comp, local_layer, 535 plane_state, 536 cmdq_handle); 537 if (!cmdq_handle) 538 plane_state->pending.async_config = false; 539 } 540 541 if (!cmdq_handle) 542 mtk_crtc->pending_async_planes = false; 543 } 544 } 545 546 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc, 547 bool needs_vblank) 548 { 549 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 550 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle; 551 #endif 552 struct drm_crtc *crtc = &mtk_crtc->base; 553 struct mtk_drm_private *priv = crtc->dev->dev_private; 554 unsigned int pending_planes = 0, pending_async_planes = 0; 555 int i; 556 557 mutex_lock(&mtk_crtc->hw_lock); 558 mtk_crtc->config_updating = true; 559 if (needs_vblank) 560 mtk_crtc->pending_needs_vblank = true; 561 562 for (i = 0; i < mtk_crtc->layer_nr; i++) { 563 struct drm_plane *plane = &mtk_crtc->planes[i]; 564 struct mtk_plane_state *plane_state; 565 566 plane_state = to_mtk_plane_state(plane->state); 567 if (plane_state->pending.dirty) { 568 plane_state->pending.config = true; 569 plane_state->pending.dirty = false; 570 pending_planes |= BIT(i); 571 } else if (plane_state->pending.async_dirty) { 572 plane_state->pending.async_config = true; 573 plane_state->pending.async_dirty = false; 574 pending_async_planes |= BIT(i); 575 } 576 } 577 if (pending_planes) 578 mtk_crtc->pending_planes = true; 579 if (pending_async_planes) 580 mtk_crtc->pending_async_planes = true; 581 582 if (priv->data->shadow_register) { 583 mtk_mutex_acquire(mtk_crtc->mutex); 584 mtk_crtc_ddp_config(crtc, NULL); 585 mtk_mutex_release(mtk_crtc->mutex); 586 } 587 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 588 if (mtk_crtc->cmdq_client.chan) { 589 mbox_flush(mtk_crtc->cmdq_client.chan, 2000); 590 cmdq_handle->cmd_buf_size = 0; 591 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 592 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 593 mtk_crtc_ddp_config(crtc, cmdq_handle); 594 cmdq_pkt_finalize(cmdq_handle); 595 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev, 596 cmdq_handle->pa_base, 597 cmdq_handle->cmd_buf_size, 598 DMA_TO_DEVICE); 599 /* 600 * CMDQ command should execute in next 3 vblank. 601 * One vblank interrupt before send message (occasionally) 602 * and one vblank interrupt after cmdq done, 603 * so it's timeout after 3 vblank interrupt. 604 * If it fail to execute in next 3 vblank, timeout happen. 605 */ 606 mtk_crtc->cmdq_vblank_cnt = 3; 607 608 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); 609 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); 610 } 611 #endif 612 mtk_crtc->config_updating = false; 613 mutex_unlock(&mtk_crtc->hw_lock); 614 } 615 616 static void mtk_crtc_ddp_irq(void *data) 617 { 618 struct drm_crtc *crtc = data; 619 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 620 struct mtk_drm_private *priv = crtc->dev->dev_private; 621 622 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 623 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) 624 mtk_crtc_ddp_config(crtc, NULL); 625 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) 626 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", 627 drm_crtc_index(&mtk_crtc->base)); 628 #else 629 if (!priv->data->shadow_register) 630 mtk_crtc_ddp_config(crtc, NULL); 631 #endif 632 mtk_drm_finish_page_flip(mtk_crtc); 633 } 634 635 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 636 { 637 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 638 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 639 640 mtk_ddp_comp_enable_vblank(comp); 641 642 return 0; 643 } 644 645 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 646 { 647 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 648 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 649 650 mtk_ddp_comp_disable_vblank(comp); 651 } 652 653 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 654 struct mtk_plane_state *state) 655 { 656 unsigned int local_layer; 657 struct mtk_ddp_comp *comp; 658 659 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 660 if (comp) 661 return mtk_ddp_comp_layer_check(comp, local_layer, state); 662 return 0; 663 } 664 665 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 666 struct drm_atomic_state *state) 667 { 668 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 669 670 if (!mtk_crtc->enabled) 671 return; 672 673 mtk_drm_crtc_update_config(mtk_crtc, false); 674 } 675 676 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 677 struct drm_atomic_state *state) 678 { 679 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 680 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 681 int ret; 682 683 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 684 685 ret = pm_runtime_resume_and_get(comp->dev); 686 if (ret < 0) { 687 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret); 688 return; 689 } 690 691 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 692 if (ret) { 693 pm_runtime_put(comp->dev); 694 return; 695 } 696 697 drm_crtc_vblank_on(crtc); 698 mtk_crtc->enabled = true; 699 } 700 701 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 702 struct drm_atomic_state *state) 703 { 704 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 705 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 706 int i, ret; 707 708 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 709 if (!mtk_crtc->enabled) 710 return; 711 712 /* Set all pending plane state to disabled */ 713 for (i = 0; i < mtk_crtc->layer_nr; i++) { 714 struct drm_plane *plane = &mtk_crtc->planes[i]; 715 struct mtk_plane_state *plane_state; 716 717 plane_state = to_mtk_plane_state(plane->state); 718 plane_state->pending.enable = false; 719 plane_state->pending.config = true; 720 } 721 mtk_crtc->pending_planes = true; 722 723 mtk_drm_crtc_update_config(mtk_crtc, false); 724 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 725 /* Wait for planes to be disabled by cmdq */ 726 if (mtk_crtc->cmdq_client.chan) 727 wait_event_timeout(mtk_crtc->cb_blocking_queue, 728 mtk_crtc->cmdq_vblank_cnt == 0, 729 msecs_to_jiffies(500)); 730 #endif 731 /* Wait for planes to be disabled */ 732 drm_crtc_wait_one_vblank(crtc); 733 734 drm_crtc_vblank_off(crtc); 735 mtk_crtc_ddp_hw_fini(mtk_crtc); 736 ret = pm_runtime_put(comp->dev); 737 if (ret < 0) 738 DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret); 739 740 mtk_crtc->enabled = false; 741 } 742 743 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 744 struct drm_atomic_state *state) 745 { 746 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 747 crtc); 748 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 749 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 750 751 if (mtk_crtc->event && mtk_crtc_state->base.event) 752 DRM_ERROR("new event while there is still a pending event\n"); 753 754 if (mtk_crtc_state->base.event) { 755 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc); 756 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 757 mtk_crtc->event = mtk_crtc_state->base.event; 758 mtk_crtc_state->base.event = NULL; 759 } 760 } 761 762 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 763 struct drm_atomic_state *state) 764 { 765 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 766 int i; 767 768 if (crtc->state->color_mgmt_changed) 769 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 770 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 771 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 772 } 773 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event); 774 } 775 776 static const struct drm_crtc_funcs mtk_crtc_funcs = { 777 .set_config = drm_atomic_helper_set_config, 778 .page_flip = drm_atomic_helper_page_flip, 779 .destroy = mtk_drm_crtc_destroy, 780 .reset = mtk_drm_crtc_reset, 781 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 782 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 783 .enable_vblank = mtk_drm_crtc_enable_vblank, 784 .disable_vblank = mtk_drm_crtc_disable_vblank, 785 }; 786 787 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 788 .mode_fixup = mtk_drm_crtc_mode_fixup, 789 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 790 .atomic_begin = mtk_drm_crtc_atomic_begin, 791 .atomic_flush = mtk_drm_crtc_atomic_flush, 792 .atomic_enable = mtk_drm_crtc_atomic_enable, 793 .atomic_disable = mtk_drm_crtc_atomic_disable, 794 }; 795 796 static int mtk_drm_crtc_init(struct drm_device *drm, 797 struct mtk_drm_crtc *mtk_crtc, 798 unsigned int pipe) 799 { 800 struct drm_plane *primary = NULL; 801 struct drm_plane *cursor = NULL; 802 int i, ret; 803 804 for (i = 0; i < mtk_crtc->layer_nr; i++) { 805 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 806 primary = &mtk_crtc->planes[i]; 807 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 808 cursor = &mtk_crtc->planes[i]; 809 } 810 811 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 812 &mtk_crtc_funcs, NULL); 813 if (ret) 814 goto err_cleanup_crtc; 815 816 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 817 818 return 0; 819 820 err_cleanup_crtc: 821 drm_crtc_cleanup(&mtk_crtc->base); 822 return ret; 823 } 824 825 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 826 int comp_idx) 827 { 828 struct mtk_ddp_comp *comp; 829 830 if (comp_idx > 1) 831 return 0; 832 833 comp = mtk_crtc->ddp_comp[comp_idx]; 834 if (!comp->funcs) 835 return 0; 836 837 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 838 return 0; 839 840 return mtk_ddp_comp_layer_nr(comp); 841 } 842 843 static inline 844 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 845 unsigned int num_planes) 846 { 847 if (plane_idx == 0) 848 return DRM_PLANE_TYPE_PRIMARY; 849 else if (plane_idx == (num_planes - 1)) 850 return DRM_PLANE_TYPE_CURSOR; 851 else 852 return DRM_PLANE_TYPE_OVERLAY; 853 854 } 855 856 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 857 struct mtk_drm_crtc *mtk_crtc, 858 int comp_idx, int pipe) 859 { 860 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 861 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 862 int i, ret; 863 864 for (i = 0; i < num_planes; i++) { 865 ret = mtk_plane_init(drm_dev, 866 &mtk_crtc->planes[mtk_crtc->layer_nr], 867 BIT(pipe), 868 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 869 num_planes), 870 mtk_ddp_comp_supported_rotations(comp), 871 mtk_ddp_comp_get_formats(comp), 872 mtk_ddp_comp_get_num_formats(comp)); 873 if (ret) 874 return ret; 875 876 mtk_crtc->layer_nr++; 877 } 878 return 0; 879 } 880 881 struct device *mtk_drm_crtc_dma_dev_get(struct drm_crtc *crtc) 882 { 883 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 884 885 return mtk_crtc->dma_dev; 886 } 887 888 int mtk_drm_crtc_create(struct drm_device *drm_dev, 889 const unsigned int *path, unsigned int path_len, 890 int priv_data_index) 891 { 892 struct mtk_drm_private *priv = drm_dev->dev_private; 893 struct device *dev = drm_dev->dev; 894 struct mtk_drm_crtc *mtk_crtc; 895 unsigned int num_comp_planes = 0; 896 int ret; 897 int i; 898 bool has_ctm = false; 899 uint gamma_lut_size = 0; 900 struct drm_crtc *tmp; 901 int crtc_i = 0; 902 903 if (!path) 904 return 0; 905 906 priv = priv->all_drm_private[priv_data_index]; 907 908 drm_for_each_crtc(tmp, drm_dev) 909 crtc_i++; 910 911 for (i = 0; i < path_len; i++) { 912 enum mtk_ddp_comp_id comp_id = path[i]; 913 struct device_node *node; 914 struct mtk_ddp_comp *comp; 915 916 node = priv->comp_node[comp_id]; 917 comp = &priv->ddp_comp[comp_id]; 918 919 /* Not all drm components have a DTS device node, such as ovl_adaptor, 920 * which is the drm bring up sub driver 921 */ 922 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) { 923 dev_info(dev, 924 "Not creating crtc %d because component %d is disabled or missing\n", 925 crtc_i, comp_id); 926 return 0; 927 } 928 929 if (!comp->dev) { 930 dev_err(dev, "Component %pOF not initialized\n", node); 931 return -ENODEV; 932 } 933 } 934 935 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 936 if (!mtk_crtc) 937 return -ENOMEM; 938 939 mtk_crtc->mmsys_dev = priv->mmsys_dev; 940 mtk_crtc->ddp_comp_nr = path_len; 941 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 942 sizeof(*mtk_crtc->ddp_comp), 943 GFP_KERNEL); 944 if (!mtk_crtc->ddp_comp) 945 return -ENOMEM; 946 947 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); 948 if (IS_ERR(mtk_crtc->mutex)) { 949 ret = PTR_ERR(mtk_crtc->mutex); 950 dev_err(dev, "Failed to get mutex: %d\n", ret); 951 return ret; 952 } 953 954 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 955 unsigned int comp_id = path[i]; 956 struct mtk_ddp_comp *comp; 957 958 comp = &priv->ddp_comp[comp_id]; 959 mtk_crtc->ddp_comp[i] = comp; 960 961 if (comp->funcs) { 962 if (comp->funcs->gamma_set) 963 gamma_lut_size = MTK_LUT_SIZE; 964 965 if (comp->funcs->ctm_set) 966 has_ctm = true; 967 } 968 969 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, 970 &mtk_crtc->base); 971 } 972 973 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 974 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 975 976 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 977 sizeof(struct drm_plane), GFP_KERNEL); 978 if (!mtk_crtc->planes) 979 return -ENOMEM; 980 981 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 982 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 983 crtc_i); 984 if (ret) 985 return ret; 986 } 987 988 /* 989 * Default to use the first component as the dma dev. 990 * In the case of ovl_adaptor sub driver, it needs to use the 991 * dma_dev_get function to get representative dma dev. 992 */ 993 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]); 994 995 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i); 996 if (ret < 0) 997 return ret; 998 999 if (gamma_lut_size) 1000 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 1001 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 1002 mutex_init(&mtk_crtc->hw_lock); 1003 1004 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 1005 i = priv->mbox_index++; 1006 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev; 1007 mtk_crtc->cmdq_client.client.tx_block = false; 1008 mtk_crtc->cmdq_client.client.knows_txdone = true; 1009 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb; 1010 mtk_crtc->cmdq_client.chan = 1011 mbox_request_channel(&mtk_crtc->cmdq_client.client, i); 1012 if (IS_ERR(mtk_crtc->cmdq_client.chan)) { 1013 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 1014 drm_crtc_index(&mtk_crtc->base)); 1015 mtk_crtc->cmdq_client.chan = NULL; 1016 } 1017 1018 if (mtk_crtc->cmdq_client.chan) { 1019 ret = of_property_read_u32_index(priv->mutex_node, 1020 "mediatek,gce-events", 1021 i, 1022 &mtk_crtc->cmdq_event); 1023 if (ret) { 1024 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 1025 drm_crtc_index(&mtk_crtc->base)); 1026 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1027 mtk_crtc->cmdq_client.chan = NULL; 1028 } else { 1029 ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client, 1030 &mtk_crtc->cmdq_handle, 1031 PAGE_SIZE); 1032 if (ret) { 1033 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n", 1034 drm_crtc_index(&mtk_crtc->base)); 1035 mbox_free_channel(mtk_crtc->cmdq_client.chan); 1036 mtk_crtc->cmdq_client.chan = NULL; 1037 } 1038 } 1039 1040 /* for sending blocking cmd in crtc disable */ 1041 init_waitqueue_head(&mtk_crtc->cb_blocking_queue); 1042 } 1043 #endif 1044 return 0; 1045 } 1046