1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 9 #include <asm/barrier.h> 10 #include <soc/mediatek/smi.h> 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_plane_helper.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_vblank.h> 16 17 #include "mtk_drm_drv.h" 18 #include "mtk_drm_crtc.h" 19 #include "mtk_drm_ddp.h" 20 #include "mtk_drm_ddp_comp.h" 21 #include "mtk_drm_gem.h" 22 #include "mtk_drm_plane.h" 23 24 /** 25 * struct mtk_drm_crtc - MediaTek specific crtc structure. 26 * @base: crtc object. 27 * @enabled: records whether crtc_enable succeeded 28 * @planes: array of 4 drm_plane structures, one for each overlay plane 29 * @pending_planes: whether any plane has pending changes to be applied 30 * @config_regs: memory mapped mmsys configuration register space 31 * @mutex: handle to one of the ten disp_mutex streams 32 * @ddp_comp_nr: number of components in ddp_comp 33 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 34 */ 35 struct mtk_drm_crtc { 36 struct drm_crtc base; 37 bool enabled; 38 39 bool pending_needs_vblank; 40 struct drm_pending_vblank_event *event; 41 42 struct drm_plane *planes; 43 unsigned int layer_nr; 44 bool pending_planes; 45 46 void __iomem *config_regs; 47 struct mtk_disp_mutex *mutex; 48 unsigned int ddp_comp_nr; 49 struct mtk_ddp_comp **ddp_comp; 50 }; 51 52 struct mtk_crtc_state { 53 struct drm_crtc_state base; 54 55 bool pending_config; 56 unsigned int pending_width; 57 unsigned int pending_height; 58 unsigned int pending_vrefresh; 59 }; 60 61 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 62 { 63 return container_of(c, struct mtk_drm_crtc, base); 64 } 65 66 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 67 { 68 return container_of(s, struct mtk_crtc_state, base); 69 } 70 71 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 72 { 73 struct drm_crtc *crtc = &mtk_crtc->base; 74 unsigned long flags; 75 76 spin_lock_irqsave(&crtc->dev->event_lock, flags); 77 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 78 drm_crtc_vblank_put(crtc); 79 mtk_crtc->event = NULL; 80 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 81 } 82 83 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 84 { 85 drm_crtc_handle_vblank(&mtk_crtc->base); 86 if (mtk_crtc->pending_needs_vblank) { 87 mtk_drm_crtc_finish_page_flip(mtk_crtc); 88 mtk_crtc->pending_needs_vblank = false; 89 } 90 } 91 92 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 93 { 94 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 95 96 mtk_disp_mutex_put(mtk_crtc->mutex); 97 98 drm_crtc_cleanup(crtc); 99 } 100 101 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 102 { 103 struct mtk_crtc_state *state; 104 105 if (crtc->state) { 106 __drm_atomic_helper_crtc_destroy_state(crtc->state); 107 108 state = to_mtk_crtc_state(crtc->state); 109 memset(state, 0, sizeof(*state)); 110 } else { 111 state = kzalloc(sizeof(*state), GFP_KERNEL); 112 if (!state) 113 return; 114 crtc->state = &state->base; 115 } 116 117 state->base.crtc = crtc; 118 } 119 120 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 121 { 122 struct mtk_crtc_state *state; 123 124 state = kzalloc(sizeof(*state), GFP_KERNEL); 125 if (!state) 126 return NULL; 127 128 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 129 130 WARN_ON(state->base.crtc != crtc); 131 state->base.crtc = crtc; 132 133 return &state->base; 134 } 135 136 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 137 struct drm_crtc_state *state) 138 { 139 __drm_atomic_helper_crtc_destroy_state(state); 140 kfree(to_mtk_crtc_state(state)); 141 } 142 143 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 144 const struct drm_display_mode *mode, 145 struct drm_display_mode *adjusted_mode) 146 { 147 /* Nothing to do here, but this callback is mandatory. */ 148 return true; 149 } 150 151 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 152 { 153 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 154 155 state->pending_width = crtc->mode.hdisplay; 156 state->pending_height = crtc->mode.vdisplay; 157 state->pending_vrefresh = crtc->mode.vrefresh; 158 wmb(); /* Make sure the above parameters are set before update */ 159 state->pending_config = true; 160 } 161 162 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 163 { 164 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 165 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 166 167 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 168 169 return 0; 170 } 171 172 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_disable_vblank(comp); 178 } 179 180 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 181 { 182 int ret; 183 int i; 184 185 DRM_DEBUG_DRIVER("%s\n", __func__); 186 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 187 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 188 if (ret) { 189 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 190 goto err; 191 } 192 } 193 194 return 0; 195 err: 196 while (--i >= 0) 197 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 198 return ret; 199 } 200 201 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 202 { 203 int i; 204 205 DRM_DEBUG_DRIVER("%s\n", __func__); 206 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 207 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 208 } 209 210 static 211 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 212 struct drm_plane *plane, 213 unsigned int *local_layer) 214 { 215 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 216 struct mtk_ddp_comp *comp; 217 int i, count = 0; 218 219 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 220 comp = mtk_crtc->ddp_comp[i]; 221 if (plane->index < (count + mtk_ddp_comp_layer_nr(comp))) { 222 *local_layer = plane->index - count; 223 return comp; 224 } 225 count += mtk_ddp_comp_layer_nr(comp); 226 } 227 228 WARN(1, "Failed to find component for plane %d\n", plane->index); 229 return NULL; 230 } 231 232 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 233 { 234 struct drm_crtc *crtc = &mtk_crtc->base; 235 struct drm_connector *connector; 236 struct drm_encoder *encoder; 237 struct drm_connector_list_iter conn_iter; 238 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 239 int ret; 240 int i; 241 242 DRM_DEBUG_DRIVER("%s\n", __func__); 243 if (WARN_ON(!crtc->state)) 244 return -EINVAL; 245 246 width = crtc->state->adjusted_mode.hdisplay; 247 height = crtc->state->adjusted_mode.vdisplay; 248 vrefresh = crtc->state->adjusted_mode.vrefresh; 249 250 drm_for_each_encoder(encoder, crtc->dev) { 251 if (encoder->crtc != crtc) 252 continue; 253 254 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 255 drm_for_each_connector_iter(connector, &conn_iter) { 256 if (connector->encoder != encoder) 257 continue; 258 if (connector->display_info.bpc != 0 && 259 bpc > connector->display_info.bpc) 260 bpc = connector->display_info.bpc; 261 } 262 drm_connector_list_iter_end(&conn_iter); 263 } 264 265 ret = pm_runtime_get_sync(crtc->dev->dev); 266 if (ret < 0) { 267 DRM_ERROR("Failed to enable power domain: %d\n", ret); 268 return ret; 269 } 270 271 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 272 if (ret < 0) { 273 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 274 goto err_pm_runtime_put; 275 } 276 277 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 278 if (ret < 0) { 279 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 280 goto err_mutex_unprepare; 281 } 282 283 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 284 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 285 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 286 mtk_crtc->ddp_comp[i]->id, 287 mtk_crtc->ddp_comp[i + 1]->id); 288 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 289 mtk_crtc->ddp_comp[i]->id); 290 } 291 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 292 mtk_disp_mutex_enable(mtk_crtc->mutex); 293 294 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 295 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 296 297 if (i == 1) 298 mtk_ddp_comp_bgclr_in_on(comp); 299 300 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); 301 mtk_ddp_comp_start(comp); 302 } 303 304 /* Initially configure all planes */ 305 for (i = 0; i < mtk_crtc->layer_nr; i++) { 306 struct drm_plane *plane = &mtk_crtc->planes[i]; 307 struct mtk_plane_state *plane_state; 308 struct mtk_ddp_comp *comp; 309 unsigned int local_layer; 310 311 plane_state = to_mtk_plane_state(plane->state); 312 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 313 mtk_ddp_comp_layer_config(comp, local_layer, plane_state); 314 } 315 316 return 0; 317 318 err_mutex_unprepare: 319 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 320 err_pm_runtime_put: 321 pm_runtime_put(crtc->dev->dev); 322 return ret; 323 } 324 325 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 326 { 327 struct drm_device *drm = mtk_crtc->base.dev; 328 int i; 329 330 DRM_DEBUG_DRIVER("%s\n", __func__); 331 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 332 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 333 if (i == 1) 334 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 335 } 336 337 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 338 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 339 mtk_crtc->ddp_comp[i]->id); 340 mtk_disp_mutex_disable(mtk_crtc->mutex); 341 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 342 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 343 mtk_crtc->ddp_comp[i]->id, 344 mtk_crtc->ddp_comp[i + 1]->id); 345 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 346 mtk_crtc->ddp_comp[i]->id); 347 } 348 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 349 mtk_crtc_ddp_clk_disable(mtk_crtc); 350 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 351 352 pm_runtime_put(drm->dev); 353 } 354 355 static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 356 { 357 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 358 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 359 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 360 unsigned int i; 361 unsigned int local_layer; 362 363 /* 364 * TODO: instead of updating the registers here, we should prepare 365 * working registers in atomic_commit and let the hardware command 366 * queue update module registers on vblank. 367 */ 368 if (state->pending_config) { 369 mtk_ddp_comp_config(comp, state->pending_width, 370 state->pending_height, 371 state->pending_vrefresh, 0); 372 373 state->pending_config = false; 374 } 375 376 if (mtk_crtc->pending_planes) { 377 for (i = 0; i < mtk_crtc->layer_nr; i++) { 378 struct drm_plane *plane = &mtk_crtc->planes[i]; 379 struct mtk_plane_state *plane_state; 380 381 plane_state = to_mtk_plane_state(plane->state); 382 383 if (!plane_state->pending.config) 384 continue; 385 386 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 387 &local_layer); 388 389 mtk_ddp_comp_layer_config(comp, local_layer, 390 plane_state); 391 plane_state->pending.config = false; 392 } 393 mtk_crtc->pending_planes = false; 394 } 395 } 396 397 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 398 struct mtk_plane_state *state) 399 { 400 unsigned int local_layer; 401 struct mtk_ddp_comp *comp; 402 403 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 404 return mtk_ddp_comp_layer_check(comp, local_layer, state); 405 } 406 407 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 408 struct drm_crtc_state *old_state) 409 { 410 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 411 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 412 int ret; 413 414 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 415 416 ret = mtk_smi_larb_get(comp->larb_dev); 417 if (ret) { 418 DRM_ERROR("Failed to get larb: %d\n", ret); 419 return; 420 } 421 422 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 423 if (ret) { 424 mtk_smi_larb_put(comp->larb_dev); 425 return; 426 } 427 428 drm_crtc_vblank_on(crtc); 429 mtk_crtc->enabled = true; 430 } 431 432 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 433 struct drm_crtc_state *old_state) 434 { 435 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 436 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 437 int i; 438 439 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 440 if (!mtk_crtc->enabled) 441 return; 442 443 /* Set all pending plane state to disabled */ 444 for (i = 0; i < mtk_crtc->layer_nr; i++) { 445 struct drm_plane *plane = &mtk_crtc->planes[i]; 446 struct mtk_plane_state *plane_state; 447 448 plane_state = to_mtk_plane_state(plane->state); 449 plane_state->pending.enable = false; 450 plane_state->pending.config = true; 451 } 452 mtk_crtc->pending_planes = true; 453 454 /* Wait for planes to be disabled */ 455 drm_crtc_wait_one_vblank(crtc); 456 457 drm_crtc_vblank_off(crtc); 458 mtk_crtc_ddp_hw_fini(mtk_crtc); 459 mtk_smi_larb_put(comp->larb_dev); 460 461 mtk_crtc->enabled = false; 462 } 463 464 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 465 struct drm_crtc_state *old_crtc_state) 466 { 467 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 468 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 469 470 if (mtk_crtc->event && state->base.event) 471 DRM_ERROR("new event while there is still a pending event\n"); 472 473 if (state->base.event) { 474 state->base.event->pipe = drm_crtc_index(crtc); 475 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 476 mtk_crtc->event = state->base.event; 477 state->base.event = NULL; 478 } 479 } 480 481 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 482 struct drm_crtc_state *old_crtc_state) 483 { 484 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 485 struct mtk_drm_private *priv = crtc->dev->dev_private; 486 unsigned int pending_planes = 0; 487 int i; 488 489 if (mtk_crtc->event) 490 mtk_crtc->pending_needs_vblank = true; 491 for (i = 0; i < mtk_crtc->layer_nr; i++) { 492 struct drm_plane *plane = &mtk_crtc->planes[i]; 493 struct mtk_plane_state *plane_state; 494 495 plane_state = to_mtk_plane_state(plane->state); 496 if (plane_state->pending.dirty) { 497 plane_state->pending.config = true; 498 plane_state->pending.dirty = false; 499 pending_planes |= BIT(i); 500 } 501 } 502 if (pending_planes) 503 mtk_crtc->pending_planes = true; 504 if (crtc->state->color_mgmt_changed) 505 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 506 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 507 508 if (priv->data->shadow_register) { 509 mtk_disp_mutex_acquire(mtk_crtc->mutex); 510 mtk_crtc_ddp_config(crtc); 511 mtk_disp_mutex_release(mtk_crtc->mutex); 512 } 513 } 514 515 static const struct drm_crtc_funcs mtk_crtc_funcs = { 516 .set_config = drm_atomic_helper_set_config, 517 .page_flip = drm_atomic_helper_page_flip, 518 .destroy = mtk_drm_crtc_destroy, 519 .reset = mtk_drm_crtc_reset, 520 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 521 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 522 .gamma_set = drm_atomic_helper_legacy_gamma_set, 523 .enable_vblank = mtk_drm_crtc_enable_vblank, 524 .disable_vblank = mtk_drm_crtc_disable_vblank, 525 }; 526 527 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 528 .mode_fixup = mtk_drm_crtc_mode_fixup, 529 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 530 .atomic_begin = mtk_drm_crtc_atomic_begin, 531 .atomic_flush = mtk_drm_crtc_atomic_flush, 532 .atomic_enable = mtk_drm_crtc_atomic_enable, 533 .atomic_disable = mtk_drm_crtc_atomic_disable, 534 }; 535 536 static int mtk_drm_crtc_init(struct drm_device *drm, 537 struct mtk_drm_crtc *mtk_crtc, 538 struct drm_plane *primary, 539 struct drm_plane *cursor, unsigned int pipe) 540 { 541 int ret; 542 543 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 544 &mtk_crtc_funcs, NULL); 545 if (ret) 546 goto err_cleanup_crtc; 547 548 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 549 550 return 0; 551 552 err_cleanup_crtc: 553 drm_crtc_cleanup(&mtk_crtc->base); 554 return ret; 555 } 556 557 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 558 { 559 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 560 struct mtk_drm_private *priv = crtc->dev->dev_private; 561 562 if (!priv->data->shadow_register) 563 mtk_crtc_ddp_config(crtc); 564 565 mtk_drm_finish_page_flip(mtk_crtc); 566 } 567 568 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 569 int comp_idx) 570 { 571 struct mtk_ddp_comp *comp; 572 573 if (comp_idx > 1) 574 return 0; 575 576 comp = mtk_crtc->ddp_comp[comp_idx]; 577 if (!comp->funcs) 578 return 0; 579 580 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 581 return 0; 582 583 return mtk_ddp_comp_layer_nr(comp); 584 } 585 586 static inline 587 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx) 588 { 589 if (plane_idx == 0) 590 return DRM_PLANE_TYPE_PRIMARY; 591 else if (plane_idx == 1) 592 return DRM_PLANE_TYPE_CURSOR; 593 else 594 return DRM_PLANE_TYPE_OVERLAY; 595 596 } 597 598 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 599 struct mtk_drm_crtc *mtk_crtc, 600 int comp_idx, int pipe) 601 { 602 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 603 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 604 int i, ret; 605 606 for (i = 0; i < num_planes; i++) { 607 ret = mtk_plane_init(drm_dev, 608 &mtk_crtc->planes[mtk_crtc->layer_nr], 609 BIT(pipe), 610 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr), 611 mtk_ddp_comp_supported_rotations(comp)); 612 if (ret) 613 return ret; 614 615 mtk_crtc->layer_nr++; 616 } 617 return 0; 618 } 619 620 int mtk_drm_crtc_create(struct drm_device *drm_dev, 621 const enum mtk_ddp_comp_id *path, unsigned int path_len) 622 { 623 struct mtk_drm_private *priv = drm_dev->dev_private; 624 struct device *dev = drm_dev->dev; 625 struct mtk_drm_crtc *mtk_crtc; 626 unsigned int num_comp_planes = 0; 627 int pipe = priv->num_pipes; 628 int ret; 629 int i; 630 631 if (!path) 632 return 0; 633 634 for (i = 0; i < path_len; i++) { 635 enum mtk_ddp_comp_id comp_id = path[i]; 636 struct device_node *node; 637 638 node = priv->comp_node[comp_id]; 639 if (!node) { 640 dev_info(dev, 641 "Not creating crtc %d because component %d is disabled or missing\n", 642 pipe, comp_id); 643 return 0; 644 } 645 } 646 647 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 648 if (!mtk_crtc) 649 return -ENOMEM; 650 651 mtk_crtc->config_regs = priv->config_regs; 652 mtk_crtc->ddp_comp_nr = path_len; 653 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 654 sizeof(*mtk_crtc->ddp_comp), 655 GFP_KERNEL); 656 if (!mtk_crtc->ddp_comp) 657 return -ENOMEM; 658 659 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 660 if (IS_ERR(mtk_crtc->mutex)) { 661 ret = PTR_ERR(mtk_crtc->mutex); 662 dev_err(dev, "Failed to get mutex: %d\n", ret); 663 return ret; 664 } 665 666 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 667 enum mtk_ddp_comp_id comp_id = path[i]; 668 struct mtk_ddp_comp *comp; 669 struct device_node *node; 670 671 node = priv->comp_node[comp_id]; 672 comp = priv->ddp_comp[comp_id]; 673 if (!comp) { 674 dev_err(dev, "Component %pOF not initialized\n", node); 675 ret = -ENODEV; 676 return ret; 677 } 678 679 mtk_crtc->ddp_comp[i] = comp; 680 } 681 682 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 683 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 684 685 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 686 sizeof(struct drm_plane), GFP_KERNEL); 687 688 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 689 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 690 pipe); 691 if (ret) 692 return ret; 693 } 694 695 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 696 mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] : 697 NULL, pipe); 698 if (ret < 0) 699 return ret; 700 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); 701 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); 702 priv->num_pipes++; 703 704 return 0; 705 } 706