1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2014 MediaTek Inc.
4  * Author: Jie Qiu <jie.qiu@mediatek.com>
5  */
6 #ifndef __MTK_DPI_REGS_H
7 #define __MTK_DPI_REGS_H
8 
9 #define DPI_EN			0x00
10 #define EN				BIT(0)
11 
12 #define DPI_RET			0x04
13 #define RST				BIT(0)
14 
15 #define DPI_INTEN		0x08
16 #define INT_VSYNC_EN			BIT(0)
17 #define INT_VDE_EN			BIT(1)
18 #define INT_UNDERFLOW_EN		BIT(2)
19 
20 #define DPI_INTSTA		0x0C
21 #define INT_VSYNC_STA			BIT(0)
22 #define INT_VDE_STA			BIT(1)
23 #define INT_UNDERFLOW_STA		BIT(2)
24 
25 #define DPI_CON			0x10
26 #define BG_ENABLE			BIT(0)
27 #define IN_RB_SWAP			BIT(1)
28 #define INTL_EN				BIT(2)
29 #define TDFP_EN				BIT(3)
30 #define CLPF_EN				BIT(4)
31 #define YUV422_EN			BIT(5)
32 #define CSC_ENABLE			BIT(6)
33 #define R601_SEL			BIT(7)
34 #define EMBSYNC_EN			BIT(8)
35 #define VS_LODD_EN			BIT(16)
36 #define VS_LEVEN_EN			BIT(17)
37 #define VS_RODD_EN			BIT(18)
38 #define VS_REVEN			BIT(19)
39 #define FAKE_DE_LODD			BIT(20)
40 #define FAKE_DE_LEVEN			BIT(21)
41 #define FAKE_DE_RODD			BIT(22)
42 #define FAKE_DE_REVEN			BIT(23)
43 
44 #define DPI_OUTPUT_SETTING	0x14
45 #define CH_SWAP				0
46 #define CH_SWAP_MASK			(0x7 << 0)
47 #define SWAP_RGB			0x00
48 #define SWAP_GBR			0x01
49 #define SWAP_BRG			0x02
50 #define SWAP_RBG			0x03
51 #define SWAP_GRB			0x04
52 #define SWAP_BGR			0x05
53 #define BIT_SWAP			BIT(3)
54 #define B_MASK				BIT(4)
55 #define G_MASK				BIT(5)
56 #define R_MASK				BIT(6)
57 #define DE_MASK				BIT(8)
58 #define HS_MASK				BIT(9)
59 #define VS_MASK				BIT(10)
60 #define DE_POL				BIT(12)
61 #define HSYNC_POL			BIT(13)
62 #define VSYNC_POL			BIT(14)
63 #define CK_POL				BIT(15)
64 #define OEN_OFF				BIT(16)
65 #define EDGE_SEL			BIT(17)
66 #define OUT_BIT				18
67 #define OUT_BIT_MASK			(0x3 << 18)
68 #define OUT_BIT_8			0x00
69 #define OUT_BIT_10			0x01
70 #define OUT_BIT_12			0x02
71 #define OUT_BIT_16			0x03
72 #define YC_MAP				20
73 #define YC_MAP_MASK			(0x7 << 20)
74 #define YC_MAP_RGB			0x00
75 #define YC_MAP_CYCY			0x04
76 #define YC_MAP_YCYC			0x05
77 #define YC_MAP_CY			0x06
78 #define YC_MAP_YC			0x07
79 
80 #define DPI_SIZE		0x18
81 #define HSIZE				0
82 #define HSIZE_MASK			(0x1FFF << 0)
83 #define VSIZE				16
84 #define VSIZE_MASK			(0x1FFF << 16)
85 
86 #define DPI_DDR_SETTING		0x1C
87 #define DDR_EN				BIT(0)
88 #define DDDR_SEL			BIT(1)
89 #define DDR_4PHASE			BIT(2)
90 #define DDR_WIDTH			(0x3 << 4)
91 #define DDR_PAD_MODE			(0x1 << 8)
92 
93 #define DPI_TGEN_HWIDTH		0x20
94 #define HPW				0
95 #define HPW_MASK			(0xFFF << 0)
96 
97 #define DPI_TGEN_HPORCH		0x24
98 #define HBP				0
99 #define HBP_MASK			(0xFFF << 0)
100 #define HFP				16
101 #define HFP_MASK			(0xFFF << 16)
102 
103 #define DPI_TGEN_VWIDTH		0x28
104 #define DPI_TGEN_VPORCH		0x2C
105 
106 #define VSYNC_WIDTH_SHIFT		0
107 #define VSYNC_WIDTH_MASK		(0xFFF << 0)
108 #define VSYNC_HALF_LINE_SHIFT		16
109 #define VSYNC_HALF_LINE_MASK		BIT(16)
110 #define VSYNC_BACK_PORCH_SHIFT		0
111 #define VSYNC_BACK_PORCH_MASK		(0xFFF << 0)
112 #define VSYNC_FRONT_PORCH_SHIFT		16
113 #define VSYNC_FRONT_PORCH_MASK		(0xFFF << 16)
114 
115 #define DPI_BG_HCNTL		0x30
116 #define BG_RIGHT			(0x1FFF << 0)
117 #define BG_LEFT				(0x1FFF << 16)
118 
119 #define DPI_BG_VCNTL		0x34
120 #define BG_BOT				(0x1FFF << 0)
121 #define BG_TOP				(0x1FFF << 16)
122 
123 #define DPI_BG_COLOR		0x38
124 #define BG_B				(0xF << 0)
125 #define BG_G				(0xF << 8)
126 #define BG_R				(0xF << 16)
127 
128 #define DPI_FIFO_CTL		0x3C
129 #define FIFO_VALID_SET			(0x1F << 0)
130 #define FIFO_RST_SEL			(0x1 << 8)
131 
132 #define DPI_STATUS		0x40
133 #define VCOUNTER			(0x1FFF << 0)
134 #define DPI_BUSY			BIT(16)
135 #define OUTEN				BIT(17)
136 #define FIELD				BIT(20)
137 #define TDLR				BIT(21)
138 
139 #define DPI_TMODE		0x44
140 #define DPI_OEN_ON			BIT(0)
141 
142 #define DPI_CHECKSUM		0x48
143 #define DPI_CHECKSUM_MASK		(0xFFFFFF << 0)
144 #define DPI_CHECKSUM_READY		BIT(30)
145 #define DPI_CHECKSUM_EN			BIT(31)
146 
147 #define DPI_DUMMY		0x50
148 #define DPI_DUMMY_MASK			(0xFFFFFFFF << 0)
149 
150 #define DPI_TGEN_VWIDTH_LEVEN	0x68
151 #define DPI_TGEN_VPORCH_LEVEN	0x6C
152 #define DPI_TGEN_VWIDTH_RODD	0x70
153 #define DPI_TGEN_VPORCH_RODD	0x74
154 #define DPI_TGEN_VWIDTH_REVEN	0x78
155 #define DPI_TGEN_VPORCH_REVEN	0x7C
156 
157 #define DPI_ESAV_VTIMING_LODD	0x80
158 #define ESAV_VOFST_LODD			(0xFFF << 0)
159 #define ESAV_VWID_LODD			(0xFFF << 16)
160 
161 #define DPI_ESAV_VTIMING_LEVEN	0x84
162 #define ESAV_VOFST_LEVEN		(0xFFF << 0)
163 #define ESAV_VWID_LEVEN			(0xFFF << 16)
164 
165 #define DPI_ESAV_VTIMING_RODD	0x88
166 #define ESAV_VOFST_RODD			(0xFFF << 0)
167 #define ESAV_VWID_RODD			(0xFFF << 16)
168 
169 #define DPI_ESAV_VTIMING_REVEN	0x8C
170 #define ESAV_VOFST_REVEN		(0xFFF << 0)
171 #define ESAV_VWID_REVEN			(0xFFF << 16)
172 
173 #define DPI_ESAV_FTIMING	0x90
174 #define ESAV_FOFST_ODD			(0xFFF << 0)
175 #define ESAV_FOFST_EVEN			(0xFFF << 16)
176 
177 #define DPI_CLPF_SETTING	0x94
178 #define CLPF_TYPE			(0x3 << 0)
179 #define ROUND_EN			BIT(4)
180 
181 #define DPI_Y_LIMIT		0x98
182 #define Y_LIMINT_BOT			0
183 #define Y_LIMINT_BOT_MASK		(0xFFF << 0)
184 #define Y_LIMINT_TOP			16
185 #define Y_LIMINT_TOP_MASK		(0xFFF << 16)
186 
187 #define DPI_C_LIMIT		0x9C
188 #define C_LIMIT_BOT			0
189 #define C_LIMIT_BOT_MASK		(0xFFF << 0)
190 #define C_LIMIT_TOP			16
191 #define C_LIMIT_TOP_MASK		(0xFFF << 16)
192 
193 #define DPI_YUV422_SETTING	0xA0
194 #define UV_SWAP				BIT(0)
195 #define CR_DELSEL			BIT(4)
196 #define CB_DELSEL			BIT(5)
197 #define Y_DELSEL			BIT(6)
198 #define DE_DELSEL			BIT(7)
199 
200 #define DPI_EMBSYNC_SETTING	0xA4
201 #define EMBSYNC_R_CR_EN			BIT(0)
202 #define EMPSYNC_G_Y_EN			BIT(1)
203 #define EMPSYNC_B_CB_EN			BIT(2)
204 #define ESAV_F_INV			BIT(4)
205 #define ESAV_V_INV			BIT(5)
206 #define ESAV_H_INV			BIT(6)
207 #define ESAV_CODE_MAN			BIT(8)
208 #define VS_OUT_SEL			(0x7 << 12)
209 
210 #define DPI_ESAV_CODE_SET0	0xA8
211 #define ESAV_CODE0			(0xFFF << 0)
212 #define ESAV_CODE1			(0xFFF << 16)
213 
214 #define DPI_ESAV_CODE_SET1	0xAC
215 #define ESAV_CODE2			(0xFFF << 0)
216 #define ESAV_CODE3_MSB			BIT(16)
217 
218 #define EDGE_SEL_EN			BIT(5)
219 #define H_FRE_2N			BIT(25)
220 #endif /* __MTK_DPI_REGS_H */
221