1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/media-bus-format.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/types.h> 18 19 #include <video/videomode.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_bridge_connector.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_edid.h> 26 #include <drm/drm_of.h> 27 #include <drm/drm_simple_kms_helper.h> 28 29 #include "mtk_disp_drv.h" 30 #include "mtk_dpi_regs.h" 31 #include "mtk_drm_ddp_comp.h" 32 33 enum mtk_dpi_out_bit_num { 34 MTK_DPI_OUT_BIT_NUM_8BITS, 35 MTK_DPI_OUT_BIT_NUM_10BITS, 36 MTK_DPI_OUT_BIT_NUM_12BITS, 37 MTK_DPI_OUT_BIT_NUM_16BITS 38 }; 39 40 enum mtk_dpi_out_yc_map { 41 MTK_DPI_OUT_YC_MAP_RGB, 42 MTK_DPI_OUT_YC_MAP_CYCY, 43 MTK_DPI_OUT_YC_MAP_YCYC, 44 MTK_DPI_OUT_YC_MAP_CY, 45 MTK_DPI_OUT_YC_MAP_YC 46 }; 47 48 enum mtk_dpi_out_channel_swap { 49 MTK_DPI_OUT_CHANNEL_SWAP_RGB, 50 MTK_DPI_OUT_CHANNEL_SWAP_GBR, 51 MTK_DPI_OUT_CHANNEL_SWAP_BRG, 52 MTK_DPI_OUT_CHANNEL_SWAP_RBG, 53 MTK_DPI_OUT_CHANNEL_SWAP_GRB, 54 MTK_DPI_OUT_CHANNEL_SWAP_BGR 55 }; 56 57 enum mtk_dpi_out_color_format { 58 MTK_DPI_COLOR_FORMAT_RGB, 59 MTK_DPI_COLOR_FORMAT_YCBCR_422 60 }; 61 62 struct mtk_dpi { 63 struct drm_encoder encoder; 64 struct drm_bridge bridge; 65 struct drm_bridge *next_bridge; 66 struct drm_connector *connector; 67 void __iomem *regs; 68 struct device *dev; 69 struct clk *engine_clk; 70 struct clk *pixel_clk; 71 struct clk *tvd_clk; 72 int irq; 73 struct drm_display_mode mode; 74 const struct mtk_dpi_conf *conf; 75 enum mtk_dpi_out_color_format color_format; 76 enum mtk_dpi_out_yc_map yc_map; 77 enum mtk_dpi_out_bit_num bit_num; 78 enum mtk_dpi_out_channel_swap channel_swap; 79 struct pinctrl *pinctrl; 80 struct pinctrl_state *pins_gpio; 81 struct pinctrl_state *pins_dpi; 82 u32 output_fmt; 83 int refcount; 84 }; 85 86 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b) 87 { 88 return container_of(b, struct mtk_dpi, bridge); 89 } 90 91 enum mtk_dpi_polarity { 92 MTK_DPI_POLARITY_RISING, 93 MTK_DPI_POLARITY_FALLING, 94 }; 95 96 struct mtk_dpi_polarities { 97 enum mtk_dpi_polarity de_pol; 98 enum mtk_dpi_polarity ck_pol; 99 enum mtk_dpi_polarity hsync_pol; 100 enum mtk_dpi_polarity vsync_pol; 101 }; 102 103 struct mtk_dpi_sync_param { 104 u32 sync_width; 105 u32 front_porch; 106 u32 back_porch; 107 bool shift_half_line; 108 }; 109 110 struct mtk_dpi_yc_limit { 111 u16 y_top; 112 u16 y_bottom; 113 u16 c_top; 114 u16 c_bottom; 115 }; 116 117 /** 118 * struct mtk_dpi_conf - Configuration of mediatek dpi. 119 * @cal_factor: Callback function to calculate factor value. 120 * @reg_h_fre_con: Register address of frequency control. 121 * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. 122 * @edge_sel_en: Enable of edge selection. 123 * @output_fmts: Array of supported output formats. 124 * @num_output_fmts: Quantity of supported output formats. 125 * @is_ck_de_pol: Support CK/DE polarity. 126 * @swap_input_support: Support input swap function. 127 * @support_direct_pin: IP supports direct connection to dpi panels. 128 * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this 129 * config to enable this feature. 130 * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH 131 * (no shift). 132 * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). 133 * @channel_swap_shift: Shift value of channel swap. 134 * @yuv422_en_bit: Enable bit of yuv422. 135 * @csc_enable_bit: Enable bit of CSC. 136 * @pixels_per_iter: Quantity of transferred pixels per iteration. 137 */ 138 struct mtk_dpi_conf { 139 unsigned int (*cal_factor)(int clock); 140 u32 reg_h_fre_con; 141 u32 max_clock_khz; 142 bool edge_sel_en; 143 const u32 *output_fmts; 144 u32 num_output_fmts; 145 bool is_ck_de_pol; 146 bool swap_input_support; 147 bool support_direct_pin; 148 bool input_2pixel; 149 u32 dimension_mask; 150 u32 hvsize_mask; 151 u32 channel_swap_shift; 152 u32 yuv422_en_bit; 153 u32 csc_enable_bit; 154 u32 pixels_per_iter; 155 }; 156 157 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) 158 { 159 u32 tmp = readl(dpi->regs + offset) & ~mask; 160 161 tmp |= (val & mask); 162 writel(tmp, dpi->regs + offset); 163 } 164 165 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) 166 { 167 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); 168 } 169 170 static void mtk_dpi_enable(struct mtk_dpi *dpi) 171 { 172 mtk_dpi_mask(dpi, DPI_EN, EN, EN); 173 } 174 175 static void mtk_dpi_disable(struct mtk_dpi *dpi) 176 { 177 mtk_dpi_mask(dpi, DPI_EN, 0, EN); 178 } 179 180 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, 181 struct mtk_dpi_sync_param *sync) 182 { 183 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, 184 dpi->conf->dimension_mask << HPW); 185 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, 186 dpi->conf->dimension_mask << HBP); 187 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, 188 dpi->conf->dimension_mask << HFP); 189 } 190 191 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, 192 struct mtk_dpi_sync_param *sync, 193 u32 width_addr, u32 porch_addr) 194 { 195 mtk_dpi_mask(dpi, width_addr, 196 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, 197 VSYNC_HALF_LINE_MASK); 198 mtk_dpi_mask(dpi, width_addr, 199 sync->sync_width << VSYNC_WIDTH_SHIFT, 200 dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); 201 mtk_dpi_mask(dpi, porch_addr, 202 sync->back_porch << VSYNC_BACK_PORCH_SHIFT, 203 dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); 204 mtk_dpi_mask(dpi, porch_addr, 205 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, 206 dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); 207 } 208 209 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, 210 struct mtk_dpi_sync_param *sync) 211 { 212 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); 213 } 214 215 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, 216 struct mtk_dpi_sync_param *sync) 217 { 218 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, 219 DPI_TGEN_VPORCH_LEVEN); 220 } 221 222 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, 223 struct mtk_dpi_sync_param *sync) 224 { 225 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, 226 DPI_TGEN_VPORCH_RODD); 227 } 228 229 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, 230 struct mtk_dpi_sync_param *sync) 231 { 232 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, 233 DPI_TGEN_VPORCH_REVEN); 234 } 235 236 static void mtk_dpi_config_pol(struct mtk_dpi *dpi, 237 struct mtk_dpi_polarities *dpi_pol) 238 { 239 unsigned int pol; 240 unsigned int mask; 241 242 mask = HSYNC_POL | VSYNC_POL; 243 pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | 244 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); 245 if (dpi->conf->is_ck_de_pol) { 246 mask |= CK_POL | DE_POL; 247 pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 248 0 : CK_POL) | 249 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 250 0 : DE_POL); 251 } 252 253 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); 254 } 255 256 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) 257 { 258 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN); 259 } 260 261 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) 262 { 263 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN); 264 } 265 266 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) 267 { 268 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, 269 dpi->conf->hvsize_mask << HSIZE); 270 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, 271 dpi->conf->hvsize_mask << VSIZE); 272 } 273 274 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) 275 { 276 struct mtk_dpi_yc_limit limit; 277 278 if (drm_default_rgb_quant_range(&dpi->mode) == 279 HDMI_QUANTIZATION_RANGE_LIMITED) { 280 limit.y_bottom = 0x10; 281 limit.y_top = 0xfe0; 282 limit.c_bottom = 0x10; 283 limit.c_top = 0xfe0; 284 } else { 285 limit.y_bottom = 0; 286 limit.y_top = 0xfff; 287 limit.c_bottom = 0; 288 limit.c_top = 0xfff; 289 } 290 291 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, 292 Y_LIMINT_BOT_MASK); 293 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, 294 Y_LIMINT_TOP_MASK); 295 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, 296 C_LIMIT_BOT_MASK); 297 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, 298 C_LIMIT_TOP_MASK); 299 } 300 301 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, 302 enum mtk_dpi_out_bit_num num) 303 { 304 u32 val; 305 306 switch (num) { 307 case MTK_DPI_OUT_BIT_NUM_8BITS: 308 val = OUT_BIT_8; 309 break; 310 case MTK_DPI_OUT_BIT_NUM_10BITS: 311 val = OUT_BIT_10; 312 break; 313 case MTK_DPI_OUT_BIT_NUM_12BITS: 314 val = OUT_BIT_12; 315 break; 316 case MTK_DPI_OUT_BIT_NUM_16BITS: 317 val = OUT_BIT_16; 318 break; 319 default: 320 val = OUT_BIT_8; 321 break; 322 } 323 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, 324 OUT_BIT_MASK); 325 } 326 327 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, 328 enum mtk_dpi_out_yc_map map) 329 { 330 u32 val; 331 332 switch (map) { 333 case MTK_DPI_OUT_YC_MAP_RGB: 334 val = YC_MAP_RGB; 335 break; 336 case MTK_DPI_OUT_YC_MAP_CYCY: 337 val = YC_MAP_CYCY; 338 break; 339 case MTK_DPI_OUT_YC_MAP_YCYC: 340 val = YC_MAP_YCYC; 341 break; 342 case MTK_DPI_OUT_YC_MAP_CY: 343 val = YC_MAP_CY; 344 break; 345 case MTK_DPI_OUT_YC_MAP_YC: 346 val = YC_MAP_YC; 347 break; 348 default: 349 val = YC_MAP_RGB; 350 break; 351 } 352 353 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); 354 } 355 356 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, 357 enum mtk_dpi_out_channel_swap swap) 358 { 359 u32 val; 360 361 switch (swap) { 362 case MTK_DPI_OUT_CHANNEL_SWAP_RGB: 363 val = SWAP_RGB; 364 break; 365 case MTK_DPI_OUT_CHANNEL_SWAP_GBR: 366 val = SWAP_GBR; 367 break; 368 case MTK_DPI_OUT_CHANNEL_SWAP_BRG: 369 val = SWAP_BRG; 370 break; 371 case MTK_DPI_OUT_CHANNEL_SWAP_RBG: 372 val = SWAP_RBG; 373 break; 374 case MTK_DPI_OUT_CHANNEL_SWAP_GRB: 375 val = SWAP_GRB; 376 break; 377 case MTK_DPI_OUT_CHANNEL_SWAP_BGR: 378 val = SWAP_BGR; 379 break; 380 default: 381 val = SWAP_RGB; 382 break; 383 } 384 385 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, 386 val << dpi->conf->channel_swap_shift, 387 CH_SWAP_MASK << dpi->conf->channel_swap_shift); 388 } 389 390 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) 391 { 392 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, 393 dpi->conf->yuv422_en_bit); 394 } 395 396 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) 397 { 398 mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, 399 dpi->conf->csc_enable_bit); 400 } 401 402 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) 403 { 404 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); 405 } 406 407 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 408 { 409 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 410 } 411 412 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 413 { 414 if (dpi->conf->edge_sel_en) 415 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 416 } 417 418 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, 419 enum mtk_dpi_out_color_format format) 420 { 421 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 422 423 if (format == MTK_DPI_COLOR_FORMAT_YCBCR_422) { 424 mtk_dpi_config_yuv422_enable(dpi, true); 425 mtk_dpi_config_csc_enable(dpi, true); 426 427 /* 428 * If height is smaller than 720, we need to use RGB_TO_BT601 429 * to transfer to yuv422. Otherwise, we use RGB_TO_JPEG. 430 */ 431 mtk_dpi_mask(dpi, DPI_MATRIX_SET, dpi->mode.hdisplay <= 720 ? 432 MATRIX_SEL_RGB_TO_BT601 : MATRIX_SEL_RGB_TO_JPEG, 433 INT_MATRIX_SEL_MASK); 434 } else { 435 mtk_dpi_config_yuv422_enable(dpi, false); 436 mtk_dpi_config_csc_enable(dpi, false); 437 if (dpi->conf->swap_input_support) 438 mtk_dpi_config_swap_input(dpi, false); 439 } 440 } 441 442 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) 443 { 444 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 445 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) { 446 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 447 DDR_EN | DDR_4PHASE); 448 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, 449 dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? 450 EDGE_SEL : 0, EDGE_SEL); 451 } else { 452 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0); 453 } 454 } 455 456 static void mtk_dpi_power_off(struct mtk_dpi *dpi) 457 { 458 if (WARN_ON(dpi->refcount == 0)) 459 return; 460 461 if (--dpi->refcount != 0) 462 return; 463 464 mtk_dpi_disable(dpi); 465 clk_disable_unprepare(dpi->pixel_clk); 466 clk_disable_unprepare(dpi->engine_clk); 467 } 468 469 static int mtk_dpi_power_on(struct mtk_dpi *dpi) 470 { 471 int ret; 472 473 if (++dpi->refcount != 1) 474 return 0; 475 476 ret = clk_prepare_enable(dpi->engine_clk); 477 if (ret) { 478 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 479 goto err_refcount; 480 } 481 482 ret = clk_prepare_enable(dpi->pixel_clk); 483 if (ret) { 484 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 485 goto err_pixel; 486 } 487 488 return 0; 489 490 err_pixel: 491 clk_disable_unprepare(dpi->engine_clk); 492 err_refcount: 493 dpi->refcount--; 494 return ret; 495 } 496 497 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 498 struct drm_display_mode *mode) 499 { 500 struct mtk_dpi_polarities dpi_pol; 501 struct mtk_dpi_sync_param hsync; 502 struct mtk_dpi_sync_param vsync_lodd = { 0 }; 503 struct mtk_dpi_sync_param vsync_leven = { 0 }; 504 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 505 struct mtk_dpi_sync_param vsync_reven = { 0 }; 506 struct videomode vm = { 0 }; 507 unsigned long pll_rate; 508 unsigned int factor; 509 510 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 511 factor = dpi->conf->cal_factor(mode->clock); 512 drm_display_mode_to_videomode(mode, &vm); 513 pll_rate = vm.pixelclock * factor; 514 515 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 516 pll_rate, vm.pixelclock); 517 518 clk_set_rate(dpi->tvd_clk, pll_rate); 519 pll_rate = clk_get_rate(dpi->tvd_clk); 520 521 /* 522 * Depending on the IP version, we may output a different amount of 523 * pixels for each iteration: divide the clock by this number and 524 * adjust the display porches accordingly. 525 */ 526 vm.pixelclock = pll_rate / factor; 527 vm.pixelclock /= dpi->conf->pixels_per_iter; 528 529 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 530 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) 531 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); 532 else 533 clk_set_rate(dpi->pixel_clk, vm.pixelclock); 534 535 536 vm.pixelclock = clk_get_rate(dpi->pixel_clk); 537 538 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 539 pll_rate, vm.pixelclock); 540 541 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 542 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; 543 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 544 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 545 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 546 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 547 548 /* 549 * Depending on the IP version, we may output a different amount of 550 * pixels for each iteration: divide the clock by this number and 551 * adjust the display porches accordingly. 552 */ 553 hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_iter; 554 hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_iter; 555 hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_iter; 556 557 hsync.shift_half_line = false; 558 vsync_lodd.sync_width = vm.vsync_len; 559 vsync_lodd.back_porch = vm.vback_porch; 560 vsync_lodd.front_porch = vm.vfront_porch; 561 vsync_lodd.shift_half_line = false; 562 563 if (vm.flags & DISPLAY_FLAGS_INTERLACED && 564 mode->flags & DRM_MODE_FLAG_3D_MASK) { 565 vsync_leven = vsync_lodd; 566 vsync_rodd = vsync_lodd; 567 vsync_reven = vsync_lodd; 568 vsync_leven.shift_half_line = true; 569 vsync_reven.shift_half_line = true; 570 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && 571 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { 572 vsync_leven = vsync_lodd; 573 vsync_leven.shift_half_line = true; 574 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && 575 mode->flags & DRM_MODE_FLAG_3D_MASK) { 576 vsync_rodd = vsync_lodd; 577 } 578 mtk_dpi_sw_reset(dpi, true); 579 mtk_dpi_config_pol(dpi, &dpi_pol); 580 581 mtk_dpi_config_hsync(dpi, &hsync); 582 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); 583 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); 584 mtk_dpi_config_vsync_leven(dpi, &vsync_leven); 585 mtk_dpi_config_vsync_reven(dpi, &vsync_reven); 586 587 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); 588 mtk_dpi_config_interface(dpi, !!(vm.flags & 589 DISPLAY_FLAGS_INTERLACED)); 590 if (vm.flags & DISPLAY_FLAGS_INTERLACED) 591 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); 592 else 593 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); 594 595 mtk_dpi_config_channel_limit(dpi); 596 mtk_dpi_config_bit_num(dpi, dpi->bit_num); 597 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 598 mtk_dpi_config_color_format(dpi, dpi->color_format); 599 if (dpi->conf->support_direct_pin) { 600 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 601 mtk_dpi_config_2n_h_fre(dpi); 602 mtk_dpi_dual_edge(dpi); 603 mtk_dpi_config_disable_edge(dpi); 604 } 605 if (dpi->conf->input_2pixel) { 606 mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, 607 DPINTF_INPUT_2P_EN); 608 } 609 mtk_dpi_sw_reset(dpi, false); 610 611 return 0; 612 } 613 614 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 615 struct drm_bridge_state *bridge_state, 616 struct drm_crtc_state *crtc_state, 617 struct drm_connector_state *conn_state, 618 unsigned int *num_output_fmts) 619 { 620 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 621 u32 *output_fmts; 622 623 *num_output_fmts = 0; 624 625 if (!dpi->conf->output_fmts) { 626 dev_err(dpi->dev, "output_fmts should not be null\n"); 627 return NULL; 628 } 629 630 output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts), 631 GFP_KERNEL); 632 if (!output_fmts) 633 return NULL; 634 635 *num_output_fmts = dpi->conf->num_output_fmts; 636 637 memcpy(output_fmts, dpi->conf->output_fmts, 638 sizeof(*output_fmts) * dpi->conf->num_output_fmts); 639 640 return output_fmts; 641 } 642 643 static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 644 struct drm_bridge_state *bridge_state, 645 struct drm_crtc_state *crtc_state, 646 struct drm_connector_state *conn_state, 647 u32 output_fmt, 648 unsigned int *num_input_fmts) 649 { 650 u32 *input_fmts; 651 652 *num_input_fmts = 0; 653 654 input_fmts = kcalloc(1, sizeof(*input_fmts), 655 GFP_KERNEL); 656 if (!input_fmts) 657 return NULL; 658 659 *num_input_fmts = 1; 660 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 661 662 return input_fmts; 663 } 664 665 static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, 666 struct drm_bridge_state *bridge_state, 667 struct drm_crtc_state *crtc_state, 668 struct drm_connector_state *conn_state) 669 { 670 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 671 unsigned int out_bus_format; 672 673 out_bus_format = bridge_state->output_bus_cfg.format; 674 675 if (out_bus_format == MEDIA_BUS_FMT_FIXED) 676 if (dpi->conf->num_output_fmts) 677 out_bus_format = dpi->conf->output_fmts[0]; 678 679 dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", 680 bridge_state->input_bus_cfg.format, 681 bridge_state->output_bus_cfg.format); 682 683 dpi->output_fmt = out_bus_format; 684 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; 685 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; 686 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; 687 if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16) 688 dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422; 689 else 690 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; 691 692 return 0; 693 } 694 695 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, 696 enum drm_bridge_attach_flags flags) 697 { 698 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 699 700 return drm_bridge_attach(bridge->encoder, dpi->next_bridge, 701 &dpi->bridge, flags); 702 } 703 704 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, 705 const struct drm_display_mode *mode, 706 const struct drm_display_mode *adjusted_mode) 707 { 708 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 709 710 drm_mode_copy(&dpi->mode, adjusted_mode); 711 } 712 713 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge) 714 { 715 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 716 717 mtk_dpi_power_off(dpi); 718 719 if (dpi->pinctrl && dpi->pins_gpio) 720 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 721 } 722 723 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) 724 { 725 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 726 727 if (dpi->pinctrl && dpi->pins_dpi) 728 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); 729 730 mtk_dpi_power_on(dpi); 731 mtk_dpi_set_display_mode(dpi, &dpi->mode); 732 mtk_dpi_enable(dpi); 733 } 734 735 static enum drm_mode_status 736 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, 737 const struct drm_display_info *info, 738 const struct drm_display_mode *mode) 739 { 740 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 741 742 if (mode->clock > dpi->conf->max_clock_khz) 743 return MODE_CLOCK_HIGH; 744 745 return MODE_OK; 746 } 747 748 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { 749 .attach = mtk_dpi_bridge_attach, 750 .mode_set = mtk_dpi_bridge_mode_set, 751 .mode_valid = mtk_dpi_bridge_mode_valid, 752 .disable = mtk_dpi_bridge_disable, 753 .enable = mtk_dpi_bridge_enable, 754 .atomic_check = mtk_dpi_bridge_atomic_check, 755 .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts, 756 .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts, 757 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 758 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 759 .atomic_reset = drm_atomic_helper_bridge_reset, 760 }; 761 762 void mtk_dpi_start(struct device *dev) 763 { 764 struct mtk_dpi *dpi = dev_get_drvdata(dev); 765 766 mtk_dpi_power_on(dpi); 767 } 768 769 void mtk_dpi_stop(struct device *dev) 770 { 771 struct mtk_dpi *dpi = dev_get_drvdata(dev); 772 773 mtk_dpi_power_off(dpi); 774 } 775 776 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) 777 { 778 struct mtk_dpi *dpi = dev_get_drvdata(dev); 779 struct drm_device *drm_dev = data; 780 int ret; 781 782 ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, 783 DRM_MODE_ENCODER_TMDS); 784 if (ret) { 785 dev_err(dev, "Failed to initialize decoder: %d\n", ret); 786 return ret; 787 } 788 789 dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev); 790 791 ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 792 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 793 if (ret) 794 goto err_cleanup; 795 796 dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder); 797 if (IS_ERR(dpi->connector)) { 798 dev_err(dev, "Unable to create bridge connector\n"); 799 ret = PTR_ERR(dpi->connector); 800 goto err_cleanup; 801 } 802 drm_connector_attach_encoder(dpi->connector, &dpi->encoder); 803 804 return 0; 805 806 err_cleanup: 807 drm_encoder_cleanup(&dpi->encoder); 808 return ret; 809 } 810 811 static void mtk_dpi_unbind(struct device *dev, struct device *master, 812 void *data) 813 { 814 struct mtk_dpi *dpi = dev_get_drvdata(dev); 815 816 drm_encoder_cleanup(&dpi->encoder); 817 } 818 819 static const struct component_ops mtk_dpi_component_ops = { 820 .bind = mtk_dpi_bind, 821 .unbind = mtk_dpi_unbind, 822 }; 823 824 static unsigned int mt8173_calculate_factor(int clock) 825 { 826 if (clock <= 27000) 827 return 3 << 4; 828 else if (clock <= 84000) 829 return 3 << 3; 830 else if (clock <= 167000) 831 return 3 << 2; 832 else 833 return 3 << 1; 834 } 835 836 static unsigned int mt2701_calculate_factor(int clock) 837 { 838 if (clock <= 64000) 839 return 4; 840 else if (clock <= 128000) 841 return 2; 842 else 843 return 1; 844 } 845 846 static unsigned int mt8183_calculate_factor(int clock) 847 { 848 if (clock <= 27000) 849 return 8; 850 else if (clock <= 167000) 851 return 4; 852 else 853 return 2; 854 } 855 856 static unsigned int mt8195_dpintf_calculate_factor(int clock) 857 { 858 if (clock < 70000) 859 return 4; 860 else if (clock < 200000) 861 return 2; 862 else 863 return 1; 864 } 865 866 static const u32 mt8173_output_fmts[] = { 867 MEDIA_BUS_FMT_RGB888_1X24, 868 }; 869 870 static const u32 mt8183_output_fmts[] = { 871 MEDIA_BUS_FMT_RGB888_2X12_LE, 872 MEDIA_BUS_FMT_RGB888_2X12_BE, 873 }; 874 875 static const u32 mt8195_output_fmts[] = { 876 MEDIA_BUS_FMT_RGB888_1X24, 877 MEDIA_BUS_FMT_YUYV8_1X16, 878 }; 879 880 static const struct mtk_dpi_conf mt8173_conf = { 881 .cal_factor = mt8173_calculate_factor, 882 .reg_h_fre_con = 0xe0, 883 .max_clock_khz = 300000, 884 .output_fmts = mt8173_output_fmts, 885 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 886 .pixels_per_iter = 1, 887 .is_ck_de_pol = true, 888 .swap_input_support = true, 889 .support_direct_pin = true, 890 .dimension_mask = HPW_MASK, 891 .hvsize_mask = HSIZE_MASK, 892 .channel_swap_shift = CH_SWAP, 893 .yuv422_en_bit = YUV422_EN, 894 .csc_enable_bit = CSC_ENABLE, 895 }; 896 897 static const struct mtk_dpi_conf mt2701_conf = { 898 .cal_factor = mt2701_calculate_factor, 899 .reg_h_fre_con = 0xb0, 900 .edge_sel_en = true, 901 .max_clock_khz = 150000, 902 .output_fmts = mt8173_output_fmts, 903 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 904 .pixels_per_iter = 1, 905 .is_ck_de_pol = true, 906 .swap_input_support = true, 907 .support_direct_pin = true, 908 .dimension_mask = HPW_MASK, 909 .hvsize_mask = HSIZE_MASK, 910 .channel_swap_shift = CH_SWAP, 911 .yuv422_en_bit = YUV422_EN, 912 .csc_enable_bit = CSC_ENABLE, 913 }; 914 915 static const struct mtk_dpi_conf mt8183_conf = { 916 .cal_factor = mt8183_calculate_factor, 917 .reg_h_fre_con = 0xe0, 918 .max_clock_khz = 100000, 919 .output_fmts = mt8183_output_fmts, 920 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 921 .pixels_per_iter = 1, 922 .is_ck_de_pol = true, 923 .swap_input_support = true, 924 .support_direct_pin = true, 925 .dimension_mask = HPW_MASK, 926 .hvsize_mask = HSIZE_MASK, 927 .channel_swap_shift = CH_SWAP, 928 .yuv422_en_bit = YUV422_EN, 929 .csc_enable_bit = CSC_ENABLE, 930 }; 931 932 static const struct mtk_dpi_conf mt8188_dpintf_conf = { 933 .cal_factor = mt8195_dpintf_calculate_factor, 934 .max_clock_khz = 600000, 935 .output_fmts = mt8195_output_fmts, 936 .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), 937 .pixels_per_iter = 4, 938 .input_2pixel = false, 939 .dimension_mask = DPINTF_HPW_MASK, 940 .hvsize_mask = DPINTF_HSIZE_MASK, 941 .channel_swap_shift = DPINTF_CH_SWAP, 942 .yuv422_en_bit = DPINTF_YUV422_EN, 943 .csc_enable_bit = DPINTF_CSC_ENABLE, 944 }; 945 946 static const struct mtk_dpi_conf mt8192_conf = { 947 .cal_factor = mt8183_calculate_factor, 948 .reg_h_fre_con = 0xe0, 949 .max_clock_khz = 150000, 950 .output_fmts = mt8183_output_fmts, 951 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 952 .pixels_per_iter = 1, 953 .is_ck_de_pol = true, 954 .swap_input_support = true, 955 .support_direct_pin = true, 956 .dimension_mask = HPW_MASK, 957 .hvsize_mask = HSIZE_MASK, 958 .channel_swap_shift = CH_SWAP, 959 .yuv422_en_bit = YUV422_EN, 960 .csc_enable_bit = CSC_ENABLE, 961 }; 962 963 static const struct mtk_dpi_conf mt8195_dpintf_conf = { 964 .cal_factor = mt8195_dpintf_calculate_factor, 965 .max_clock_khz = 600000, 966 .output_fmts = mt8195_output_fmts, 967 .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), 968 .pixels_per_iter = 4, 969 .input_2pixel = true, 970 .dimension_mask = DPINTF_HPW_MASK, 971 .hvsize_mask = DPINTF_HSIZE_MASK, 972 .channel_swap_shift = DPINTF_CH_SWAP, 973 .yuv422_en_bit = DPINTF_YUV422_EN, 974 .csc_enable_bit = DPINTF_CSC_ENABLE, 975 }; 976 977 static int mtk_dpi_probe(struct platform_device *pdev) 978 { 979 struct device *dev = &pdev->dev; 980 struct mtk_dpi *dpi; 981 struct resource *mem; 982 int ret; 983 984 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); 985 if (!dpi) 986 return -ENOMEM; 987 988 dpi->dev = dev; 989 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); 990 dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 991 992 dpi->pinctrl = devm_pinctrl_get(&pdev->dev); 993 if (IS_ERR(dpi->pinctrl)) { 994 dpi->pinctrl = NULL; 995 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n"); 996 } 997 if (dpi->pinctrl) { 998 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep"); 999 if (IS_ERR(dpi->pins_gpio)) { 1000 dpi->pins_gpio = NULL; 1001 dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n"); 1002 } 1003 if (dpi->pins_gpio) 1004 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 1005 1006 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default"); 1007 if (IS_ERR(dpi->pins_dpi)) { 1008 dpi->pins_dpi = NULL; 1009 dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n"); 1010 } 1011 } 1012 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1013 dpi->regs = devm_ioremap_resource(dev, mem); 1014 if (IS_ERR(dpi->regs)) { 1015 ret = PTR_ERR(dpi->regs); 1016 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret); 1017 return ret; 1018 } 1019 1020 dpi->engine_clk = devm_clk_get(dev, "engine"); 1021 if (IS_ERR(dpi->engine_clk)) { 1022 ret = PTR_ERR(dpi->engine_clk); 1023 if (ret != -EPROBE_DEFER) 1024 dev_err(dev, "Failed to get engine clock: %d\n", ret); 1025 1026 return ret; 1027 } 1028 1029 dpi->pixel_clk = devm_clk_get(dev, "pixel"); 1030 if (IS_ERR(dpi->pixel_clk)) { 1031 ret = PTR_ERR(dpi->pixel_clk); 1032 if (ret != -EPROBE_DEFER) 1033 dev_err(dev, "Failed to get pixel clock: %d\n", ret); 1034 1035 return ret; 1036 } 1037 1038 dpi->tvd_clk = devm_clk_get(dev, "pll"); 1039 if (IS_ERR(dpi->tvd_clk)) { 1040 ret = PTR_ERR(dpi->tvd_clk); 1041 if (ret != -EPROBE_DEFER) 1042 dev_err(dev, "Failed to get tvdpll clock: %d\n", ret); 1043 1044 return ret; 1045 } 1046 1047 dpi->irq = platform_get_irq(pdev, 0); 1048 if (dpi->irq <= 0) 1049 return -EINVAL; 1050 1051 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 1052 NULL, &dpi->next_bridge); 1053 if (ret) 1054 return ret; 1055 1056 dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node); 1057 1058 platform_set_drvdata(pdev, dpi); 1059 1060 dpi->bridge.funcs = &mtk_dpi_bridge_funcs; 1061 dpi->bridge.of_node = dev->of_node; 1062 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI; 1063 1064 drm_bridge_add(&dpi->bridge); 1065 1066 ret = component_add(dev, &mtk_dpi_component_ops); 1067 if (ret) { 1068 drm_bridge_remove(&dpi->bridge); 1069 dev_err(dev, "Failed to add component: %d\n", ret); 1070 return ret; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int mtk_dpi_remove(struct platform_device *pdev) 1077 { 1078 struct mtk_dpi *dpi = platform_get_drvdata(pdev); 1079 1080 component_del(&pdev->dev, &mtk_dpi_component_ops); 1081 drm_bridge_remove(&dpi->bridge); 1082 1083 return 0; 1084 } 1085 1086 static const struct of_device_id mtk_dpi_of_ids[] = { 1087 { .compatible = "mediatek,mt2701-dpi", 1088 .data = &mt2701_conf, 1089 }, 1090 { .compatible = "mediatek,mt8173-dpi", 1091 .data = &mt8173_conf, 1092 }, 1093 { .compatible = "mediatek,mt8183-dpi", 1094 .data = &mt8183_conf, 1095 }, 1096 { .compatible = "mediatek,mt8188-dp-intf", 1097 .data = &mt8188_dpintf_conf, 1098 }, 1099 { .compatible = "mediatek,mt8192-dpi", 1100 .data = &mt8192_conf, 1101 }, 1102 { .compatible = "mediatek,mt8195-dp-intf", 1103 .data = &mt8195_dpintf_conf, 1104 }, 1105 { }, 1106 }; 1107 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); 1108 1109 struct platform_driver mtk_dpi_driver = { 1110 .probe = mtk_dpi_probe, 1111 .remove = mtk_dpi_remove, 1112 .driver = { 1113 .name = "mediatek-dpi", 1114 .of_match_table = mtk_dpi_of_ids, 1115 }, 1116 }; 1117