1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 #include <drm/drmP.h> 7 #include <drm/drm_crtc.h> 8 #include <drm/drm_atomic_helper.h> 9 #include <drm/drm_of.h> 10 #include <linux/kernel.h> 11 #include <linux/component.h> 12 #include <linux/platform_device.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_graph.h> 16 #include <linux/interrupt.h> 17 #include <linux/types.h> 18 #include <linux/clk.h> 19 #include <video/videomode.h> 20 21 #include "mtk_dpi_regs.h" 22 #include "mtk_drm_ddp_comp.h" 23 24 enum mtk_dpi_out_bit_num { 25 MTK_DPI_OUT_BIT_NUM_8BITS, 26 MTK_DPI_OUT_BIT_NUM_10BITS, 27 MTK_DPI_OUT_BIT_NUM_12BITS, 28 MTK_DPI_OUT_BIT_NUM_16BITS 29 }; 30 31 enum mtk_dpi_out_yc_map { 32 MTK_DPI_OUT_YC_MAP_RGB, 33 MTK_DPI_OUT_YC_MAP_CYCY, 34 MTK_DPI_OUT_YC_MAP_YCYC, 35 MTK_DPI_OUT_YC_MAP_CY, 36 MTK_DPI_OUT_YC_MAP_YC 37 }; 38 39 enum mtk_dpi_out_channel_swap { 40 MTK_DPI_OUT_CHANNEL_SWAP_RGB, 41 MTK_DPI_OUT_CHANNEL_SWAP_GBR, 42 MTK_DPI_OUT_CHANNEL_SWAP_BRG, 43 MTK_DPI_OUT_CHANNEL_SWAP_RBG, 44 MTK_DPI_OUT_CHANNEL_SWAP_GRB, 45 MTK_DPI_OUT_CHANNEL_SWAP_BGR 46 }; 47 48 enum mtk_dpi_out_color_format { 49 MTK_DPI_COLOR_FORMAT_RGB, 50 MTK_DPI_COLOR_FORMAT_RGB_FULL, 51 MTK_DPI_COLOR_FORMAT_YCBCR_444, 52 MTK_DPI_COLOR_FORMAT_YCBCR_422, 53 MTK_DPI_COLOR_FORMAT_XV_YCC, 54 MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL, 55 MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL 56 }; 57 58 struct mtk_dpi { 59 struct mtk_ddp_comp ddp_comp; 60 struct drm_encoder encoder; 61 struct drm_bridge *bridge; 62 void __iomem *regs; 63 struct device *dev; 64 struct clk *engine_clk; 65 struct clk *pixel_clk; 66 struct clk *tvd_clk; 67 int irq; 68 struct drm_display_mode mode; 69 const struct mtk_dpi_conf *conf; 70 enum mtk_dpi_out_color_format color_format; 71 enum mtk_dpi_out_yc_map yc_map; 72 enum mtk_dpi_out_bit_num bit_num; 73 enum mtk_dpi_out_channel_swap channel_swap; 74 int refcount; 75 }; 76 77 static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e) 78 { 79 return container_of(e, struct mtk_dpi, encoder); 80 } 81 82 enum mtk_dpi_polarity { 83 MTK_DPI_POLARITY_RISING, 84 MTK_DPI_POLARITY_FALLING, 85 }; 86 87 struct mtk_dpi_polarities { 88 enum mtk_dpi_polarity de_pol; 89 enum mtk_dpi_polarity ck_pol; 90 enum mtk_dpi_polarity hsync_pol; 91 enum mtk_dpi_polarity vsync_pol; 92 }; 93 94 struct mtk_dpi_sync_param { 95 u32 sync_width; 96 u32 front_porch; 97 u32 back_porch; 98 bool shift_half_line; 99 }; 100 101 struct mtk_dpi_yc_limit { 102 u16 y_top; 103 u16 y_bottom; 104 u16 c_top; 105 u16 c_bottom; 106 }; 107 108 struct mtk_dpi_conf { 109 unsigned int (*cal_factor)(int clock); 110 u32 reg_h_fre_con; 111 bool edge_sel_en; 112 }; 113 114 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) 115 { 116 u32 tmp = readl(dpi->regs + offset) & ~mask; 117 118 tmp |= (val & mask); 119 writel(tmp, dpi->regs + offset); 120 } 121 122 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) 123 { 124 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); 125 } 126 127 static void mtk_dpi_enable(struct mtk_dpi *dpi) 128 { 129 mtk_dpi_mask(dpi, DPI_EN, EN, EN); 130 } 131 132 static void mtk_dpi_disable(struct mtk_dpi *dpi) 133 { 134 mtk_dpi_mask(dpi, DPI_EN, 0, EN); 135 } 136 137 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, 138 struct mtk_dpi_sync_param *sync) 139 { 140 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, 141 sync->sync_width << HPW, HPW_MASK); 142 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, 143 sync->back_porch << HBP, HBP_MASK); 144 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, 145 HFP_MASK); 146 } 147 148 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, 149 struct mtk_dpi_sync_param *sync, 150 u32 width_addr, u32 porch_addr) 151 { 152 mtk_dpi_mask(dpi, width_addr, 153 sync->sync_width << VSYNC_WIDTH_SHIFT, 154 VSYNC_WIDTH_MASK); 155 mtk_dpi_mask(dpi, width_addr, 156 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, 157 VSYNC_HALF_LINE_MASK); 158 mtk_dpi_mask(dpi, porch_addr, 159 sync->back_porch << VSYNC_BACK_PORCH_SHIFT, 160 VSYNC_BACK_PORCH_MASK); 161 mtk_dpi_mask(dpi, porch_addr, 162 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, 163 VSYNC_FRONT_PORCH_MASK); 164 } 165 166 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, 167 struct mtk_dpi_sync_param *sync) 168 { 169 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); 170 } 171 172 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, 173 struct mtk_dpi_sync_param *sync) 174 { 175 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, 176 DPI_TGEN_VPORCH_LEVEN); 177 } 178 179 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, 180 struct mtk_dpi_sync_param *sync) 181 { 182 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, 183 DPI_TGEN_VPORCH_RODD); 184 } 185 186 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, 187 struct mtk_dpi_sync_param *sync) 188 { 189 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, 190 DPI_TGEN_VPORCH_REVEN); 191 } 192 193 static void mtk_dpi_config_pol(struct mtk_dpi *dpi, 194 struct mtk_dpi_polarities *dpi_pol) 195 { 196 unsigned int pol; 197 198 pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | 199 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | 200 (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | 201 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); 202 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, 203 CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); 204 } 205 206 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) 207 { 208 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN); 209 } 210 211 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) 212 { 213 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN); 214 } 215 216 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) 217 { 218 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); 219 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); 220 } 221 222 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, 223 struct mtk_dpi_yc_limit *limit) 224 { 225 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, 226 Y_LIMINT_BOT_MASK); 227 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, 228 Y_LIMINT_TOP_MASK); 229 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, 230 C_LIMIT_BOT_MASK); 231 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, 232 C_LIMIT_TOP_MASK); 233 } 234 235 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, 236 enum mtk_dpi_out_bit_num num) 237 { 238 u32 val; 239 240 switch (num) { 241 case MTK_DPI_OUT_BIT_NUM_8BITS: 242 val = OUT_BIT_8; 243 break; 244 case MTK_DPI_OUT_BIT_NUM_10BITS: 245 val = OUT_BIT_10; 246 break; 247 case MTK_DPI_OUT_BIT_NUM_12BITS: 248 val = OUT_BIT_12; 249 break; 250 case MTK_DPI_OUT_BIT_NUM_16BITS: 251 val = OUT_BIT_16; 252 break; 253 default: 254 val = OUT_BIT_8; 255 break; 256 } 257 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, 258 OUT_BIT_MASK); 259 } 260 261 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, 262 enum mtk_dpi_out_yc_map map) 263 { 264 u32 val; 265 266 switch (map) { 267 case MTK_DPI_OUT_YC_MAP_RGB: 268 val = YC_MAP_RGB; 269 break; 270 case MTK_DPI_OUT_YC_MAP_CYCY: 271 val = YC_MAP_CYCY; 272 break; 273 case MTK_DPI_OUT_YC_MAP_YCYC: 274 val = YC_MAP_YCYC; 275 break; 276 case MTK_DPI_OUT_YC_MAP_CY: 277 val = YC_MAP_CY; 278 break; 279 case MTK_DPI_OUT_YC_MAP_YC: 280 val = YC_MAP_YC; 281 break; 282 default: 283 val = YC_MAP_RGB; 284 break; 285 } 286 287 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); 288 } 289 290 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, 291 enum mtk_dpi_out_channel_swap swap) 292 { 293 u32 val; 294 295 switch (swap) { 296 case MTK_DPI_OUT_CHANNEL_SWAP_RGB: 297 val = SWAP_RGB; 298 break; 299 case MTK_DPI_OUT_CHANNEL_SWAP_GBR: 300 val = SWAP_GBR; 301 break; 302 case MTK_DPI_OUT_CHANNEL_SWAP_BRG: 303 val = SWAP_BRG; 304 break; 305 case MTK_DPI_OUT_CHANNEL_SWAP_RBG: 306 val = SWAP_RBG; 307 break; 308 case MTK_DPI_OUT_CHANNEL_SWAP_GRB: 309 val = SWAP_GRB; 310 break; 311 case MTK_DPI_OUT_CHANNEL_SWAP_BGR: 312 val = SWAP_BGR; 313 break; 314 default: 315 val = SWAP_RGB; 316 break; 317 } 318 319 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); 320 } 321 322 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) 323 { 324 mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); 325 } 326 327 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) 328 { 329 mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); 330 } 331 332 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) 333 { 334 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); 335 } 336 337 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 338 { 339 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 340 } 341 342 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 343 { 344 if (dpi->conf->edge_sel_en) 345 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 346 } 347 348 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, 349 enum mtk_dpi_out_color_format format) 350 { 351 if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) || 352 (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { 353 mtk_dpi_config_yuv422_enable(dpi, false); 354 mtk_dpi_config_csc_enable(dpi, true); 355 mtk_dpi_config_swap_input(dpi, false); 356 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); 357 } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || 358 (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { 359 mtk_dpi_config_yuv422_enable(dpi, true); 360 mtk_dpi_config_csc_enable(dpi, true); 361 mtk_dpi_config_swap_input(dpi, true); 362 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 363 } else { 364 mtk_dpi_config_yuv422_enable(dpi, false); 365 mtk_dpi_config_csc_enable(dpi, false); 366 mtk_dpi_config_swap_input(dpi, false); 367 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 368 } 369 } 370 371 static void mtk_dpi_power_off(struct mtk_dpi *dpi) 372 { 373 if (WARN_ON(dpi->refcount == 0)) 374 return; 375 376 if (--dpi->refcount != 0) 377 return; 378 379 mtk_dpi_disable(dpi); 380 clk_disable_unprepare(dpi->pixel_clk); 381 clk_disable_unprepare(dpi->engine_clk); 382 } 383 384 static int mtk_dpi_power_on(struct mtk_dpi *dpi) 385 { 386 int ret; 387 388 if (++dpi->refcount != 1) 389 return 0; 390 391 ret = clk_prepare_enable(dpi->engine_clk); 392 if (ret) { 393 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 394 goto err_refcount; 395 } 396 397 ret = clk_prepare_enable(dpi->pixel_clk); 398 if (ret) { 399 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 400 goto err_pixel; 401 } 402 403 mtk_dpi_enable(dpi); 404 return 0; 405 406 err_pixel: 407 clk_disable_unprepare(dpi->engine_clk); 408 err_refcount: 409 dpi->refcount--; 410 return ret; 411 } 412 413 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 414 struct drm_display_mode *mode) 415 { 416 struct mtk_dpi_yc_limit limit; 417 struct mtk_dpi_polarities dpi_pol; 418 struct mtk_dpi_sync_param hsync; 419 struct mtk_dpi_sync_param vsync_lodd = { 0 }; 420 struct mtk_dpi_sync_param vsync_leven = { 0 }; 421 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 422 struct mtk_dpi_sync_param vsync_reven = { 0 }; 423 struct videomode vm = { 0 }; 424 unsigned long pll_rate; 425 unsigned int factor; 426 427 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 428 factor = dpi->conf->cal_factor(mode->clock); 429 drm_display_mode_to_videomode(mode, &vm); 430 pll_rate = vm.pixelclock * factor; 431 432 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 433 pll_rate, vm.pixelclock); 434 435 clk_set_rate(dpi->tvd_clk, pll_rate); 436 pll_rate = clk_get_rate(dpi->tvd_clk); 437 438 vm.pixelclock = pll_rate / factor; 439 clk_set_rate(dpi->pixel_clk, vm.pixelclock); 440 vm.pixelclock = clk_get_rate(dpi->pixel_clk); 441 442 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 443 pll_rate, vm.pixelclock); 444 445 limit.c_bottom = 0x0010; 446 limit.c_top = 0x0FE0; 447 limit.y_bottom = 0x0010; 448 limit.y_top = 0x0FE0; 449 450 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 451 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; 452 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 453 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 454 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 455 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 456 hsync.sync_width = vm.hsync_len; 457 hsync.back_porch = vm.hback_porch; 458 hsync.front_porch = vm.hfront_porch; 459 hsync.shift_half_line = false; 460 vsync_lodd.sync_width = vm.vsync_len; 461 vsync_lodd.back_porch = vm.vback_porch; 462 vsync_lodd.front_porch = vm.vfront_porch; 463 vsync_lodd.shift_half_line = false; 464 465 if (vm.flags & DISPLAY_FLAGS_INTERLACED && 466 mode->flags & DRM_MODE_FLAG_3D_MASK) { 467 vsync_leven = vsync_lodd; 468 vsync_rodd = vsync_lodd; 469 vsync_reven = vsync_lodd; 470 vsync_leven.shift_half_line = true; 471 vsync_reven.shift_half_line = true; 472 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && 473 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { 474 vsync_leven = vsync_lodd; 475 vsync_leven.shift_half_line = true; 476 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && 477 mode->flags & DRM_MODE_FLAG_3D_MASK) { 478 vsync_rodd = vsync_lodd; 479 } 480 mtk_dpi_sw_reset(dpi, true); 481 mtk_dpi_config_pol(dpi, &dpi_pol); 482 483 mtk_dpi_config_hsync(dpi, &hsync); 484 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); 485 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); 486 mtk_dpi_config_vsync_leven(dpi, &vsync_leven); 487 mtk_dpi_config_vsync_reven(dpi, &vsync_reven); 488 489 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); 490 mtk_dpi_config_interface(dpi, !!(vm.flags & 491 DISPLAY_FLAGS_INTERLACED)); 492 if (vm.flags & DISPLAY_FLAGS_INTERLACED) 493 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); 494 else 495 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); 496 497 mtk_dpi_config_channel_limit(dpi, &limit); 498 mtk_dpi_config_bit_num(dpi, dpi->bit_num); 499 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 500 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 501 mtk_dpi_config_color_format(dpi, dpi->color_format); 502 mtk_dpi_config_2n_h_fre(dpi); 503 mtk_dpi_config_disable_edge(dpi); 504 mtk_dpi_sw_reset(dpi, false); 505 506 return 0; 507 } 508 509 static void mtk_dpi_encoder_destroy(struct drm_encoder *encoder) 510 { 511 drm_encoder_cleanup(encoder); 512 } 513 514 static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = { 515 .destroy = mtk_dpi_encoder_destroy, 516 }; 517 518 static bool mtk_dpi_encoder_mode_fixup(struct drm_encoder *encoder, 519 const struct drm_display_mode *mode, 520 struct drm_display_mode *adjusted_mode) 521 { 522 return true; 523 } 524 525 static void mtk_dpi_encoder_mode_set(struct drm_encoder *encoder, 526 struct drm_display_mode *mode, 527 struct drm_display_mode *adjusted_mode) 528 { 529 struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder); 530 531 drm_mode_copy(&dpi->mode, adjusted_mode); 532 } 533 534 static void mtk_dpi_encoder_disable(struct drm_encoder *encoder) 535 { 536 struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder); 537 538 mtk_dpi_power_off(dpi); 539 } 540 541 static void mtk_dpi_encoder_enable(struct drm_encoder *encoder) 542 { 543 struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder); 544 545 mtk_dpi_power_on(dpi); 546 mtk_dpi_set_display_mode(dpi, &dpi->mode); 547 } 548 549 static int mtk_dpi_atomic_check(struct drm_encoder *encoder, 550 struct drm_crtc_state *crtc_state, 551 struct drm_connector_state *conn_state) 552 { 553 return 0; 554 } 555 556 static const struct drm_encoder_helper_funcs mtk_dpi_encoder_helper_funcs = { 557 .mode_fixup = mtk_dpi_encoder_mode_fixup, 558 .mode_set = mtk_dpi_encoder_mode_set, 559 .disable = mtk_dpi_encoder_disable, 560 .enable = mtk_dpi_encoder_enable, 561 .atomic_check = mtk_dpi_atomic_check, 562 }; 563 564 static void mtk_dpi_start(struct mtk_ddp_comp *comp) 565 { 566 struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp); 567 568 mtk_dpi_power_on(dpi); 569 } 570 571 static void mtk_dpi_stop(struct mtk_ddp_comp *comp) 572 { 573 struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp); 574 575 mtk_dpi_power_off(dpi); 576 } 577 578 static const struct mtk_ddp_comp_funcs mtk_dpi_funcs = { 579 .start = mtk_dpi_start, 580 .stop = mtk_dpi_stop, 581 }; 582 583 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) 584 { 585 struct mtk_dpi *dpi = dev_get_drvdata(dev); 586 struct drm_device *drm_dev = data; 587 int ret; 588 589 ret = mtk_ddp_comp_register(drm_dev, &dpi->ddp_comp); 590 if (ret < 0) { 591 dev_err(dev, "Failed to register component %pOF: %d\n", 592 dev->of_node, ret); 593 return ret; 594 } 595 596 ret = drm_encoder_init(drm_dev, &dpi->encoder, &mtk_dpi_encoder_funcs, 597 DRM_MODE_ENCODER_TMDS, NULL); 598 if (ret) { 599 dev_err(dev, "Failed to initialize decoder: %d\n", ret); 600 goto err_unregister; 601 } 602 drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs); 603 604 /* Currently DPI0 is fixed to be driven by OVL1 */ 605 dpi->encoder.possible_crtcs = BIT(1); 606 607 ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL); 608 if (ret) { 609 dev_err(dev, "Failed to attach bridge: %d\n", ret); 610 goto err_cleanup; 611 } 612 613 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; 614 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; 615 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; 616 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; 617 618 return 0; 619 620 err_cleanup: 621 drm_encoder_cleanup(&dpi->encoder); 622 err_unregister: 623 mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp); 624 return ret; 625 } 626 627 static void mtk_dpi_unbind(struct device *dev, struct device *master, 628 void *data) 629 { 630 struct mtk_dpi *dpi = dev_get_drvdata(dev); 631 struct drm_device *drm_dev = data; 632 633 drm_encoder_cleanup(&dpi->encoder); 634 mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp); 635 } 636 637 static const struct component_ops mtk_dpi_component_ops = { 638 .bind = mtk_dpi_bind, 639 .unbind = mtk_dpi_unbind, 640 }; 641 642 static unsigned int mt8173_calculate_factor(int clock) 643 { 644 if (clock <= 27000) 645 return 3 << 4; 646 else if (clock <= 84000) 647 return 3 << 3; 648 else if (clock <= 167000) 649 return 3 << 2; 650 else 651 return 3 << 1; 652 } 653 654 static unsigned int mt2701_calculate_factor(int clock) 655 { 656 if (clock <= 64000) 657 return 4; 658 else if (clock <= 128000) 659 return 2; 660 else 661 return 1; 662 } 663 664 static const struct mtk_dpi_conf mt8173_conf = { 665 .cal_factor = mt8173_calculate_factor, 666 .reg_h_fre_con = 0xe0, 667 }; 668 669 static const struct mtk_dpi_conf mt2701_conf = { 670 .cal_factor = mt2701_calculate_factor, 671 .reg_h_fre_con = 0xb0, 672 .edge_sel_en = true, 673 }; 674 675 static int mtk_dpi_probe(struct platform_device *pdev) 676 { 677 struct device *dev = &pdev->dev; 678 struct mtk_dpi *dpi; 679 struct resource *mem; 680 int comp_id; 681 int ret; 682 683 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); 684 if (!dpi) 685 return -ENOMEM; 686 687 dpi->dev = dev; 688 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); 689 690 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 691 dpi->regs = devm_ioremap_resource(dev, mem); 692 if (IS_ERR(dpi->regs)) { 693 ret = PTR_ERR(dpi->regs); 694 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret); 695 return ret; 696 } 697 698 dpi->engine_clk = devm_clk_get(dev, "engine"); 699 if (IS_ERR(dpi->engine_clk)) { 700 ret = PTR_ERR(dpi->engine_clk); 701 dev_err(dev, "Failed to get engine clock: %d\n", ret); 702 return ret; 703 } 704 705 dpi->pixel_clk = devm_clk_get(dev, "pixel"); 706 if (IS_ERR(dpi->pixel_clk)) { 707 ret = PTR_ERR(dpi->pixel_clk); 708 dev_err(dev, "Failed to get pixel clock: %d\n", ret); 709 return ret; 710 } 711 712 dpi->tvd_clk = devm_clk_get(dev, "pll"); 713 if (IS_ERR(dpi->tvd_clk)) { 714 ret = PTR_ERR(dpi->tvd_clk); 715 dev_err(dev, "Failed to get tvdpll clock: %d\n", ret); 716 return ret; 717 } 718 719 dpi->irq = platform_get_irq(pdev, 0); 720 if (dpi->irq <= 0) { 721 dev_err(dev, "Failed to get irq: %d\n", dpi->irq); 722 return -EINVAL; 723 } 724 725 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 726 NULL, &dpi->bridge); 727 if (ret) 728 return ret; 729 730 dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge->of_node); 731 732 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI); 733 if (comp_id < 0) { 734 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 735 return comp_id; 736 } 737 738 ret = mtk_ddp_comp_init(dev, dev->of_node, &dpi->ddp_comp, comp_id, 739 &mtk_dpi_funcs); 740 if (ret) { 741 dev_err(dev, "Failed to initialize component: %d\n", ret); 742 return ret; 743 } 744 745 platform_set_drvdata(pdev, dpi); 746 747 ret = component_add(dev, &mtk_dpi_component_ops); 748 if (ret) { 749 dev_err(dev, "Failed to add component: %d\n", ret); 750 return ret; 751 } 752 753 return 0; 754 } 755 756 static int mtk_dpi_remove(struct platform_device *pdev) 757 { 758 component_del(&pdev->dev, &mtk_dpi_component_ops); 759 760 return 0; 761 } 762 763 static const struct of_device_id mtk_dpi_of_ids[] = { 764 { .compatible = "mediatek,mt2701-dpi", 765 .data = &mt2701_conf, 766 }, 767 { .compatible = "mediatek,mt8173-dpi", 768 .data = &mt8173_conf, 769 }, 770 { }, 771 }; 772 773 struct platform_driver mtk_dpi_driver = { 774 .probe = mtk_dpi_probe, 775 .remove = mtk_dpi_remove, 776 .driver = { 777 .name = "mediatek-dpi", 778 .of_match_table = mtk_dpi_of_ids, 779 }, 780 }; 781