1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of_graph.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/types.h> 18 19 #include <video/videomode.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_bridge_connector.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "mtk_disp_drv.h" 29 #include "mtk_dpi_regs.h" 30 #include "mtk_drm_ddp_comp.h" 31 32 enum mtk_dpi_out_bit_num { 33 MTK_DPI_OUT_BIT_NUM_8BITS, 34 MTK_DPI_OUT_BIT_NUM_10BITS, 35 MTK_DPI_OUT_BIT_NUM_12BITS, 36 MTK_DPI_OUT_BIT_NUM_16BITS 37 }; 38 39 enum mtk_dpi_out_yc_map { 40 MTK_DPI_OUT_YC_MAP_RGB, 41 MTK_DPI_OUT_YC_MAP_CYCY, 42 MTK_DPI_OUT_YC_MAP_YCYC, 43 MTK_DPI_OUT_YC_MAP_CY, 44 MTK_DPI_OUT_YC_MAP_YC 45 }; 46 47 enum mtk_dpi_out_channel_swap { 48 MTK_DPI_OUT_CHANNEL_SWAP_RGB, 49 MTK_DPI_OUT_CHANNEL_SWAP_GBR, 50 MTK_DPI_OUT_CHANNEL_SWAP_BRG, 51 MTK_DPI_OUT_CHANNEL_SWAP_RBG, 52 MTK_DPI_OUT_CHANNEL_SWAP_GRB, 53 MTK_DPI_OUT_CHANNEL_SWAP_BGR 54 }; 55 56 enum mtk_dpi_out_color_format { 57 MTK_DPI_COLOR_FORMAT_RGB, 58 MTK_DPI_COLOR_FORMAT_RGB_FULL, 59 MTK_DPI_COLOR_FORMAT_YCBCR_444, 60 MTK_DPI_COLOR_FORMAT_YCBCR_422, 61 MTK_DPI_COLOR_FORMAT_XV_YCC, 62 MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL, 63 MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL 64 }; 65 66 struct mtk_dpi { 67 struct drm_encoder encoder; 68 struct drm_bridge bridge; 69 struct drm_bridge *next_bridge; 70 struct drm_connector *connector; 71 void __iomem *regs; 72 struct device *dev; 73 struct clk *engine_clk; 74 struct clk *pixel_clk; 75 struct clk *tvd_clk; 76 int irq; 77 struct drm_display_mode mode; 78 const struct mtk_dpi_conf *conf; 79 enum mtk_dpi_out_color_format color_format; 80 enum mtk_dpi_out_yc_map yc_map; 81 enum mtk_dpi_out_bit_num bit_num; 82 enum mtk_dpi_out_channel_swap channel_swap; 83 struct pinctrl *pinctrl; 84 struct pinctrl_state *pins_gpio; 85 struct pinctrl_state *pins_dpi; 86 int refcount; 87 }; 88 89 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b) 90 { 91 return container_of(b, struct mtk_dpi, bridge); 92 } 93 94 enum mtk_dpi_polarity { 95 MTK_DPI_POLARITY_RISING, 96 MTK_DPI_POLARITY_FALLING, 97 }; 98 99 struct mtk_dpi_polarities { 100 enum mtk_dpi_polarity de_pol; 101 enum mtk_dpi_polarity ck_pol; 102 enum mtk_dpi_polarity hsync_pol; 103 enum mtk_dpi_polarity vsync_pol; 104 }; 105 106 struct mtk_dpi_sync_param { 107 u32 sync_width; 108 u32 front_porch; 109 u32 back_porch; 110 bool shift_half_line; 111 }; 112 113 struct mtk_dpi_yc_limit { 114 u16 y_top; 115 u16 y_bottom; 116 u16 c_top; 117 u16 c_bottom; 118 }; 119 120 struct mtk_dpi_conf { 121 unsigned int (*cal_factor)(int clock); 122 u32 reg_h_fre_con; 123 u32 max_clock_khz; 124 bool edge_sel_en; 125 }; 126 127 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) 128 { 129 u32 tmp = readl(dpi->regs + offset) & ~mask; 130 131 tmp |= (val & mask); 132 writel(tmp, dpi->regs + offset); 133 } 134 135 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) 136 { 137 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); 138 } 139 140 static void mtk_dpi_enable(struct mtk_dpi *dpi) 141 { 142 mtk_dpi_mask(dpi, DPI_EN, EN, EN); 143 } 144 145 static void mtk_dpi_disable(struct mtk_dpi *dpi) 146 { 147 mtk_dpi_mask(dpi, DPI_EN, 0, EN); 148 } 149 150 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, 151 struct mtk_dpi_sync_param *sync) 152 { 153 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, 154 sync->sync_width << HPW, HPW_MASK); 155 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, 156 sync->back_porch << HBP, HBP_MASK); 157 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, 158 HFP_MASK); 159 } 160 161 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, 162 struct mtk_dpi_sync_param *sync, 163 u32 width_addr, u32 porch_addr) 164 { 165 mtk_dpi_mask(dpi, width_addr, 166 sync->sync_width << VSYNC_WIDTH_SHIFT, 167 VSYNC_WIDTH_MASK); 168 mtk_dpi_mask(dpi, width_addr, 169 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, 170 VSYNC_HALF_LINE_MASK); 171 mtk_dpi_mask(dpi, porch_addr, 172 sync->back_porch << VSYNC_BACK_PORCH_SHIFT, 173 VSYNC_BACK_PORCH_MASK); 174 mtk_dpi_mask(dpi, porch_addr, 175 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, 176 VSYNC_FRONT_PORCH_MASK); 177 } 178 179 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, 180 struct mtk_dpi_sync_param *sync) 181 { 182 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); 183 } 184 185 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, 186 struct mtk_dpi_sync_param *sync) 187 { 188 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, 189 DPI_TGEN_VPORCH_LEVEN); 190 } 191 192 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, 193 struct mtk_dpi_sync_param *sync) 194 { 195 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, 196 DPI_TGEN_VPORCH_RODD); 197 } 198 199 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, 200 struct mtk_dpi_sync_param *sync) 201 { 202 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, 203 DPI_TGEN_VPORCH_REVEN); 204 } 205 206 static void mtk_dpi_config_pol(struct mtk_dpi *dpi, 207 struct mtk_dpi_polarities *dpi_pol) 208 { 209 unsigned int pol; 210 211 pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | 212 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | 213 (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | 214 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); 215 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, 216 CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); 217 } 218 219 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) 220 { 221 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN); 222 } 223 224 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) 225 { 226 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN); 227 } 228 229 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) 230 { 231 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); 232 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); 233 } 234 235 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, 236 struct mtk_dpi_yc_limit *limit) 237 { 238 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, 239 Y_LIMINT_BOT_MASK); 240 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, 241 Y_LIMINT_TOP_MASK); 242 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, 243 C_LIMIT_BOT_MASK); 244 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, 245 C_LIMIT_TOP_MASK); 246 } 247 248 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, 249 enum mtk_dpi_out_bit_num num) 250 { 251 u32 val; 252 253 switch (num) { 254 case MTK_DPI_OUT_BIT_NUM_8BITS: 255 val = OUT_BIT_8; 256 break; 257 case MTK_DPI_OUT_BIT_NUM_10BITS: 258 val = OUT_BIT_10; 259 break; 260 case MTK_DPI_OUT_BIT_NUM_12BITS: 261 val = OUT_BIT_12; 262 break; 263 case MTK_DPI_OUT_BIT_NUM_16BITS: 264 val = OUT_BIT_16; 265 break; 266 default: 267 val = OUT_BIT_8; 268 break; 269 } 270 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, 271 OUT_BIT_MASK); 272 } 273 274 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, 275 enum mtk_dpi_out_yc_map map) 276 { 277 u32 val; 278 279 switch (map) { 280 case MTK_DPI_OUT_YC_MAP_RGB: 281 val = YC_MAP_RGB; 282 break; 283 case MTK_DPI_OUT_YC_MAP_CYCY: 284 val = YC_MAP_CYCY; 285 break; 286 case MTK_DPI_OUT_YC_MAP_YCYC: 287 val = YC_MAP_YCYC; 288 break; 289 case MTK_DPI_OUT_YC_MAP_CY: 290 val = YC_MAP_CY; 291 break; 292 case MTK_DPI_OUT_YC_MAP_YC: 293 val = YC_MAP_YC; 294 break; 295 default: 296 val = YC_MAP_RGB; 297 break; 298 } 299 300 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); 301 } 302 303 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, 304 enum mtk_dpi_out_channel_swap swap) 305 { 306 u32 val; 307 308 switch (swap) { 309 case MTK_DPI_OUT_CHANNEL_SWAP_RGB: 310 val = SWAP_RGB; 311 break; 312 case MTK_DPI_OUT_CHANNEL_SWAP_GBR: 313 val = SWAP_GBR; 314 break; 315 case MTK_DPI_OUT_CHANNEL_SWAP_BRG: 316 val = SWAP_BRG; 317 break; 318 case MTK_DPI_OUT_CHANNEL_SWAP_RBG: 319 val = SWAP_RBG; 320 break; 321 case MTK_DPI_OUT_CHANNEL_SWAP_GRB: 322 val = SWAP_GRB; 323 break; 324 case MTK_DPI_OUT_CHANNEL_SWAP_BGR: 325 val = SWAP_BGR; 326 break; 327 default: 328 val = SWAP_RGB; 329 break; 330 } 331 332 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); 333 } 334 335 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) 336 { 337 mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); 338 } 339 340 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) 341 { 342 mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); 343 } 344 345 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) 346 { 347 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); 348 } 349 350 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 351 { 352 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 353 } 354 355 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 356 { 357 if (dpi->conf->edge_sel_en) 358 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 359 } 360 361 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, 362 enum mtk_dpi_out_color_format format) 363 { 364 if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) || 365 (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { 366 mtk_dpi_config_yuv422_enable(dpi, false); 367 mtk_dpi_config_csc_enable(dpi, true); 368 mtk_dpi_config_swap_input(dpi, false); 369 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); 370 } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || 371 (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { 372 mtk_dpi_config_yuv422_enable(dpi, true); 373 mtk_dpi_config_csc_enable(dpi, true); 374 mtk_dpi_config_swap_input(dpi, true); 375 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 376 } else { 377 mtk_dpi_config_yuv422_enable(dpi, false); 378 mtk_dpi_config_csc_enable(dpi, false); 379 mtk_dpi_config_swap_input(dpi, false); 380 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 381 } 382 } 383 384 static void mtk_dpi_power_off(struct mtk_dpi *dpi) 385 { 386 if (WARN_ON(dpi->refcount == 0)) 387 return; 388 389 if (--dpi->refcount != 0) 390 return; 391 392 if (dpi->pinctrl && dpi->pins_gpio) 393 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 394 395 mtk_dpi_disable(dpi); 396 clk_disable_unprepare(dpi->pixel_clk); 397 clk_disable_unprepare(dpi->engine_clk); 398 } 399 400 static int mtk_dpi_power_on(struct mtk_dpi *dpi) 401 { 402 int ret; 403 404 if (++dpi->refcount != 1) 405 return 0; 406 407 ret = clk_prepare_enable(dpi->engine_clk); 408 if (ret) { 409 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 410 goto err_refcount; 411 } 412 413 ret = clk_prepare_enable(dpi->pixel_clk); 414 if (ret) { 415 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 416 goto err_pixel; 417 } 418 419 if (dpi->pinctrl && dpi->pins_dpi) 420 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); 421 422 mtk_dpi_enable(dpi); 423 return 0; 424 425 err_pixel: 426 clk_disable_unprepare(dpi->engine_clk); 427 err_refcount: 428 dpi->refcount--; 429 return ret; 430 } 431 432 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 433 struct drm_display_mode *mode) 434 { 435 struct mtk_dpi_yc_limit limit; 436 struct mtk_dpi_polarities dpi_pol; 437 struct mtk_dpi_sync_param hsync; 438 struct mtk_dpi_sync_param vsync_lodd = { 0 }; 439 struct mtk_dpi_sync_param vsync_leven = { 0 }; 440 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 441 struct mtk_dpi_sync_param vsync_reven = { 0 }; 442 struct videomode vm = { 0 }; 443 unsigned long pll_rate; 444 unsigned int factor; 445 446 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 447 factor = dpi->conf->cal_factor(mode->clock); 448 drm_display_mode_to_videomode(mode, &vm); 449 pll_rate = vm.pixelclock * factor; 450 451 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 452 pll_rate, vm.pixelclock); 453 454 clk_set_rate(dpi->tvd_clk, pll_rate); 455 pll_rate = clk_get_rate(dpi->tvd_clk); 456 457 vm.pixelclock = pll_rate / factor; 458 clk_set_rate(dpi->pixel_clk, vm.pixelclock); 459 vm.pixelclock = clk_get_rate(dpi->pixel_clk); 460 461 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 462 pll_rate, vm.pixelclock); 463 464 limit.c_bottom = 0x0010; 465 limit.c_top = 0x0FE0; 466 limit.y_bottom = 0x0010; 467 limit.y_top = 0x0FE0; 468 469 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 470 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; 471 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 472 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 473 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 474 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 475 hsync.sync_width = vm.hsync_len; 476 hsync.back_porch = vm.hback_porch; 477 hsync.front_porch = vm.hfront_porch; 478 hsync.shift_half_line = false; 479 vsync_lodd.sync_width = vm.vsync_len; 480 vsync_lodd.back_porch = vm.vback_porch; 481 vsync_lodd.front_porch = vm.vfront_porch; 482 vsync_lodd.shift_half_line = false; 483 484 if (vm.flags & DISPLAY_FLAGS_INTERLACED && 485 mode->flags & DRM_MODE_FLAG_3D_MASK) { 486 vsync_leven = vsync_lodd; 487 vsync_rodd = vsync_lodd; 488 vsync_reven = vsync_lodd; 489 vsync_leven.shift_half_line = true; 490 vsync_reven.shift_half_line = true; 491 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && 492 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { 493 vsync_leven = vsync_lodd; 494 vsync_leven.shift_half_line = true; 495 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && 496 mode->flags & DRM_MODE_FLAG_3D_MASK) { 497 vsync_rodd = vsync_lodd; 498 } 499 mtk_dpi_sw_reset(dpi, true); 500 mtk_dpi_config_pol(dpi, &dpi_pol); 501 502 mtk_dpi_config_hsync(dpi, &hsync); 503 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); 504 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); 505 mtk_dpi_config_vsync_leven(dpi, &vsync_leven); 506 mtk_dpi_config_vsync_reven(dpi, &vsync_reven); 507 508 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); 509 mtk_dpi_config_interface(dpi, !!(vm.flags & 510 DISPLAY_FLAGS_INTERLACED)); 511 if (vm.flags & DISPLAY_FLAGS_INTERLACED) 512 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); 513 else 514 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); 515 516 mtk_dpi_config_channel_limit(dpi, &limit); 517 mtk_dpi_config_bit_num(dpi, dpi->bit_num); 518 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 519 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 520 mtk_dpi_config_color_format(dpi, dpi->color_format); 521 mtk_dpi_config_2n_h_fre(dpi); 522 mtk_dpi_config_disable_edge(dpi); 523 mtk_dpi_sw_reset(dpi, false); 524 525 return 0; 526 } 527 528 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, 529 enum drm_bridge_attach_flags flags) 530 { 531 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 532 533 return drm_bridge_attach(bridge->encoder, dpi->next_bridge, 534 &dpi->bridge, flags); 535 } 536 537 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, 538 const struct drm_display_mode *mode, 539 const struct drm_display_mode *adjusted_mode) 540 { 541 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 542 543 drm_mode_copy(&dpi->mode, adjusted_mode); 544 } 545 546 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge) 547 { 548 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 549 550 mtk_dpi_power_off(dpi); 551 } 552 553 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) 554 { 555 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 556 557 mtk_dpi_power_on(dpi); 558 mtk_dpi_set_display_mode(dpi, &dpi->mode); 559 } 560 561 static enum drm_mode_status 562 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, 563 const struct drm_display_info *info, 564 const struct drm_display_mode *mode) 565 { 566 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 567 568 if (mode->clock > dpi->conf->max_clock_khz) 569 return MODE_CLOCK_HIGH; 570 571 return MODE_OK; 572 } 573 574 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { 575 .attach = mtk_dpi_bridge_attach, 576 .mode_set = mtk_dpi_bridge_mode_set, 577 .mode_valid = mtk_dpi_bridge_mode_valid, 578 .disable = mtk_dpi_bridge_disable, 579 .enable = mtk_dpi_bridge_enable, 580 }; 581 582 void mtk_dpi_start(struct device *dev) 583 { 584 struct mtk_dpi *dpi = dev_get_drvdata(dev); 585 586 mtk_dpi_power_on(dpi); 587 } 588 589 void mtk_dpi_stop(struct device *dev) 590 { 591 struct mtk_dpi *dpi = dev_get_drvdata(dev); 592 593 mtk_dpi_power_off(dpi); 594 } 595 596 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) 597 { 598 struct mtk_dpi *dpi = dev_get_drvdata(dev); 599 struct drm_device *drm_dev = data; 600 int ret; 601 602 ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, 603 DRM_MODE_ENCODER_TMDS); 604 if (ret) { 605 dev_err(dev, "Failed to initialize decoder: %d\n", ret); 606 return ret; 607 } 608 609 dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev); 610 611 ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 612 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 613 if (ret) { 614 dev_err(dev, "Failed to attach bridge: %d\n", ret); 615 goto err_cleanup; 616 } 617 618 dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder); 619 if (IS_ERR(dpi->connector)) { 620 dev_err(dev, "Unable to create bridge connector\n"); 621 ret = PTR_ERR(dpi->connector); 622 goto err_cleanup; 623 } 624 drm_connector_attach_encoder(dpi->connector, &dpi->encoder); 625 626 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; 627 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; 628 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; 629 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; 630 631 return 0; 632 633 err_cleanup: 634 drm_encoder_cleanup(&dpi->encoder); 635 return ret; 636 } 637 638 static void mtk_dpi_unbind(struct device *dev, struct device *master, 639 void *data) 640 { 641 struct mtk_dpi *dpi = dev_get_drvdata(dev); 642 643 drm_encoder_cleanup(&dpi->encoder); 644 } 645 646 static const struct component_ops mtk_dpi_component_ops = { 647 .bind = mtk_dpi_bind, 648 .unbind = mtk_dpi_unbind, 649 }; 650 651 static unsigned int mt8173_calculate_factor(int clock) 652 { 653 if (clock <= 27000) 654 return 3 << 4; 655 else if (clock <= 84000) 656 return 3 << 3; 657 else if (clock <= 167000) 658 return 3 << 2; 659 else 660 return 3 << 1; 661 } 662 663 static unsigned int mt2701_calculate_factor(int clock) 664 { 665 if (clock <= 64000) 666 return 4; 667 else if (clock <= 128000) 668 return 2; 669 else 670 return 1; 671 } 672 673 static unsigned int mt8183_calculate_factor(int clock) 674 { 675 if (clock <= 27000) 676 return 8; 677 else if (clock <= 167000) 678 return 4; 679 else 680 return 2; 681 } 682 683 static const struct mtk_dpi_conf mt8173_conf = { 684 .cal_factor = mt8173_calculate_factor, 685 .reg_h_fre_con = 0xe0, 686 .max_clock_khz = 300000, 687 }; 688 689 static const struct mtk_dpi_conf mt2701_conf = { 690 .cal_factor = mt2701_calculate_factor, 691 .reg_h_fre_con = 0xb0, 692 .edge_sel_en = true, 693 .max_clock_khz = 150000, 694 }; 695 696 static const struct mtk_dpi_conf mt8183_conf = { 697 .cal_factor = mt8183_calculate_factor, 698 .reg_h_fre_con = 0xe0, 699 .max_clock_khz = 100000, 700 }; 701 702 static const struct mtk_dpi_conf mt8192_conf = { 703 .cal_factor = mt8183_calculate_factor, 704 .reg_h_fre_con = 0xe0, 705 .max_clock_khz = 150000, 706 }; 707 708 static int mtk_dpi_probe(struct platform_device *pdev) 709 { 710 struct device *dev = &pdev->dev; 711 struct mtk_dpi *dpi; 712 struct resource *mem; 713 int ret; 714 715 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); 716 if (!dpi) 717 return -ENOMEM; 718 719 dpi->dev = dev; 720 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); 721 722 dpi->pinctrl = devm_pinctrl_get(&pdev->dev); 723 if (IS_ERR(dpi->pinctrl)) { 724 dpi->pinctrl = NULL; 725 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n"); 726 } 727 if (dpi->pinctrl) { 728 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep"); 729 if (IS_ERR(dpi->pins_gpio)) { 730 dpi->pins_gpio = NULL; 731 dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n"); 732 } 733 if (dpi->pins_gpio) 734 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 735 736 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default"); 737 if (IS_ERR(dpi->pins_dpi)) { 738 dpi->pins_dpi = NULL; 739 dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n"); 740 } 741 } 742 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 743 dpi->regs = devm_ioremap_resource(dev, mem); 744 if (IS_ERR(dpi->regs)) { 745 ret = PTR_ERR(dpi->regs); 746 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret); 747 return ret; 748 } 749 750 dpi->engine_clk = devm_clk_get(dev, "engine"); 751 if (IS_ERR(dpi->engine_clk)) { 752 ret = PTR_ERR(dpi->engine_clk); 753 if (ret != -EPROBE_DEFER) 754 dev_err(dev, "Failed to get engine clock: %d\n", ret); 755 756 return ret; 757 } 758 759 dpi->pixel_clk = devm_clk_get(dev, "pixel"); 760 if (IS_ERR(dpi->pixel_clk)) { 761 ret = PTR_ERR(dpi->pixel_clk); 762 if (ret != -EPROBE_DEFER) 763 dev_err(dev, "Failed to get pixel clock: %d\n", ret); 764 765 return ret; 766 } 767 768 dpi->tvd_clk = devm_clk_get(dev, "pll"); 769 if (IS_ERR(dpi->tvd_clk)) { 770 ret = PTR_ERR(dpi->tvd_clk); 771 if (ret != -EPROBE_DEFER) 772 dev_err(dev, "Failed to get tvdpll clock: %d\n", ret); 773 774 return ret; 775 } 776 777 dpi->irq = platform_get_irq(pdev, 0); 778 if (dpi->irq <= 0) 779 return -EINVAL; 780 781 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 782 NULL, &dpi->next_bridge); 783 if (ret) 784 return ret; 785 786 dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node); 787 788 platform_set_drvdata(pdev, dpi); 789 790 dpi->bridge.funcs = &mtk_dpi_bridge_funcs; 791 dpi->bridge.of_node = dev->of_node; 792 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI; 793 794 drm_bridge_add(&dpi->bridge); 795 796 ret = component_add(dev, &mtk_dpi_component_ops); 797 if (ret) { 798 drm_bridge_remove(&dpi->bridge); 799 dev_err(dev, "Failed to add component: %d\n", ret); 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static int mtk_dpi_remove(struct platform_device *pdev) 807 { 808 struct mtk_dpi *dpi = platform_get_drvdata(pdev); 809 810 component_del(&pdev->dev, &mtk_dpi_component_ops); 811 drm_bridge_remove(&dpi->bridge); 812 813 return 0; 814 } 815 816 static const struct of_device_id mtk_dpi_of_ids[] = { 817 { .compatible = "mediatek,mt2701-dpi", 818 .data = &mt2701_conf, 819 }, 820 { .compatible = "mediatek,mt8173-dpi", 821 .data = &mt8173_conf, 822 }, 823 { .compatible = "mediatek,mt8183-dpi", 824 .data = &mt8183_conf, 825 }, 826 { .compatible = "mediatek,mt8192-dpi", 827 .data = &mt8192_conf, 828 }, 829 { }, 830 }; 831 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); 832 833 struct platform_driver mtk_dpi_driver = { 834 .probe = mtk_dpi_probe, 835 .remove = mtk_dpi_remove, 836 .driver = { 837 .name = "mediatek-dpi", 838 .of_match_table = mtk_dpi_of_ids, 839 }, 840 }; 841