1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of_graph.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/types.h> 18 19 #include <video/videomode.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_bridge_connector.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "mtk_disp_drv.h" 29 #include "mtk_dpi_regs.h" 30 #include "mtk_drm_ddp_comp.h" 31 32 enum mtk_dpi_out_bit_num { 33 MTK_DPI_OUT_BIT_NUM_8BITS, 34 MTK_DPI_OUT_BIT_NUM_10BITS, 35 MTK_DPI_OUT_BIT_NUM_12BITS, 36 MTK_DPI_OUT_BIT_NUM_16BITS 37 }; 38 39 enum mtk_dpi_out_yc_map { 40 MTK_DPI_OUT_YC_MAP_RGB, 41 MTK_DPI_OUT_YC_MAP_CYCY, 42 MTK_DPI_OUT_YC_MAP_YCYC, 43 MTK_DPI_OUT_YC_MAP_CY, 44 MTK_DPI_OUT_YC_MAP_YC 45 }; 46 47 enum mtk_dpi_out_channel_swap { 48 MTK_DPI_OUT_CHANNEL_SWAP_RGB, 49 MTK_DPI_OUT_CHANNEL_SWAP_GBR, 50 MTK_DPI_OUT_CHANNEL_SWAP_BRG, 51 MTK_DPI_OUT_CHANNEL_SWAP_RBG, 52 MTK_DPI_OUT_CHANNEL_SWAP_GRB, 53 MTK_DPI_OUT_CHANNEL_SWAP_BGR 54 }; 55 56 enum mtk_dpi_out_color_format { 57 MTK_DPI_COLOR_FORMAT_RGB, 58 MTK_DPI_COLOR_FORMAT_RGB_FULL, 59 MTK_DPI_COLOR_FORMAT_YCBCR_444, 60 MTK_DPI_COLOR_FORMAT_YCBCR_422, 61 MTK_DPI_COLOR_FORMAT_XV_YCC, 62 MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL, 63 MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL 64 }; 65 66 struct mtk_dpi { 67 struct drm_encoder encoder; 68 struct drm_bridge bridge; 69 struct drm_bridge *next_bridge; 70 struct drm_connector *connector; 71 void __iomem *regs; 72 struct device *dev; 73 struct clk *engine_clk; 74 struct clk *pixel_clk; 75 struct clk *tvd_clk; 76 int irq; 77 struct drm_display_mode mode; 78 const struct mtk_dpi_conf *conf; 79 enum mtk_dpi_out_color_format color_format; 80 enum mtk_dpi_out_yc_map yc_map; 81 enum mtk_dpi_out_bit_num bit_num; 82 enum mtk_dpi_out_channel_swap channel_swap; 83 struct pinctrl *pinctrl; 84 struct pinctrl_state *pins_gpio; 85 struct pinctrl_state *pins_dpi; 86 u32 output_fmt; 87 int refcount; 88 }; 89 90 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b) 91 { 92 return container_of(b, struct mtk_dpi, bridge); 93 } 94 95 enum mtk_dpi_polarity { 96 MTK_DPI_POLARITY_RISING, 97 MTK_DPI_POLARITY_FALLING, 98 }; 99 100 struct mtk_dpi_polarities { 101 enum mtk_dpi_polarity de_pol; 102 enum mtk_dpi_polarity ck_pol; 103 enum mtk_dpi_polarity hsync_pol; 104 enum mtk_dpi_polarity vsync_pol; 105 }; 106 107 struct mtk_dpi_sync_param { 108 u32 sync_width; 109 u32 front_porch; 110 u32 back_porch; 111 bool shift_half_line; 112 }; 113 114 struct mtk_dpi_yc_limit { 115 u16 y_top; 116 u16 y_bottom; 117 u16 c_top; 118 u16 c_bottom; 119 }; 120 121 struct mtk_dpi_conf { 122 unsigned int (*cal_factor)(int clock); 123 u32 reg_h_fre_con; 124 u32 max_clock_khz; 125 bool edge_sel_en; 126 const u32 *output_fmts; 127 u32 num_output_fmts; 128 }; 129 130 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) 131 { 132 u32 tmp = readl(dpi->regs + offset) & ~mask; 133 134 tmp |= (val & mask); 135 writel(tmp, dpi->regs + offset); 136 } 137 138 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset) 139 { 140 mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST); 141 } 142 143 static void mtk_dpi_enable(struct mtk_dpi *dpi) 144 { 145 mtk_dpi_mask(dpi, DPI_EN, EN, EN); 146 } 147 148 static void mtk_dpi_disable(struct mtk_dpi *dpi) 149 { 150 mtk_dpi_mask(dpi, DPI_EN, 0, EN); 151 } 152 153 static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, 154 struct mtk_dpi_sync_param *sync) 155 { 156 mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, 157 sync->sync_width << HPW, HPW_MASK); 158 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, 159 sync->back_porch << HBP, HBP_MASK); 160 mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, 161 HFP_MASK); 162 } 163 164 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, 165 struct mtk_dpi_sync_param *sync, 166 u32 width_addr, u32 porch_addr) 167 { 168 mtk_dpi_mask(dpi, width_addr, 169 sync->sync_width << VSYNC_WIDTH_SHIFT, 170 VSYNC_WIDTH_MASK); 171 mtk_dpi_mask(dpi, width_addr, 172 sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, 173 VSYNC_HALF_LINE_MASK); 174 mtk_dpi_mask(dpi, porch_addr, 175 sync->back_porch << VSYNC_BACK_PORCH_SHIFT, 176 VSYNC_BACK_PORCH_MASK); 177 mtk_dpi_mask(dpi, porch_addr, 178 sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, 179 VSYNC_FRONT_PORCH_MASK); 180 } 181 182 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, 183 struct mtk_dpi_sync_param *sync) 184 { 185 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); 186 } 187 188 static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, 189 struct mtk_dpi_sync_param *sync) 190 { 191 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, 192 DPI_TGEN_VPORCH_LEVEN); 193 } 194 195 static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, 196 struct mtk_dpi_sync_param *sync) 197 { 198 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, 199 DPI_TGEN_VPORCH_RODD); 200 } 201 202 static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, 203 struct mtk_dpi_sync_param *sync) 204 { 205 mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, 206 DPI_TGEN_VPORCH_REVEN); 207 } 208 209 static void mtk_dpi_config_pol(struct mtk_dpi *dpi, 210 struct mtk_dpi_polarities *dpi_pol) 211 { 212 unsigned int pol; 213 214 pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | 215 (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | 216 (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | 217 (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); 218 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, 219 CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); 220 } 221 222 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) 223 { 224 mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN); 225 } 226 227 static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) 228 { 229 mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN); 230 } 231 232 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) 233 { 234 mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); 235 mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); 236 } 237 238 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, 239 struct mtk_dpi_yc_limit *limit) 240 { 241 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, 242 Y_LIMINT_BOT_MASK); 243 mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, 244 Y_LIMINT_TOP_MASK); 245 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, 246 C_LIMIT_BOT_MASK); 247 mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, 248 C_LIMIT_TOP_MASK); 249 } 250 251 static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi, 252 enum mtk_dpi_out_bit_num num) 253 { 254 u32 val; 255 256 switch (num) { 257 case MTK_DPI_OUT_BIT_NUM_8BITS: 258 val = OUT_BIT_8; 259 break; 260 case MTK_DPI_OUT_BIT_NUM_10BITS: 261 val = OUT_BIT_10; 262 break; 263 case MTK_DPI_OUT_BIT_NUM_12BITS: 264 val = OUT_BIT_12; 265 break; 266 case MTK_DPI_OUT_BIT_NUM_16BITS: 267 val = OUT_BIT_16; 268 break; 269 default: 270 val = OUT_BIT_8; 271 break; 272 } 273 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT, 274 OUT_BIT_MASK); 275 } 276 277 static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi, 278 enum mtk_dpi_out_yc_map map) 279 { 280 u32 val; 281 282 switch (map) { 283 case MTK_DPI_OUT_YC_MAP_RGB: 284 val = YC_MAP_RGB; 285 break; 286 case MTK_DPI_OUT_YC_MAP_CYCY: 287 val = YC_MAP_CYCY; 288 break; 289 case MTK_DPI_OUT_YC_MAP_YCYC: 290 val = YC_MAP_YCYC; 291 break; 292 case MTK_DPI_OUT_YC_MAP_CY: 293 val = YC_MAP_CY; 294 break; 295 case MTK_DPI_OUT_YC_MAP_YC: 296 val = YC_MAP_YC; 297 break; 298 default: 299 val = YC_MAP_RGB; 300 break; 301 } 302 303 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK); 304 } 305 306 static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, 307 enum mtk_dpi_out_channel_swap swap) 308 { 309 u32 val; 310 311 switch (swap) { 312 case MTK_DPI_OUT_CHANNEL_SWAP_RGB: 313 val = SWAP_RGB; 314 break; 315 case MTK_DPI_OUT_CHANNEL_SWAP_GBR: 316 val = SWAP_GBR; 317 break; 318 case MTK_DPI_OUT_CHANNEL_SWAP_BRG: 319 val = SWAP_BRG; 320 break; 321 case MTK_DPI_OUT_CHANNEL_SWAP_RBG: 322 val = SWAP_RBG; 323 break; 324 case MTK_DPI_OUT_CHANNEL_SWAP_GRB: 325 val = SWAP_GRB; 326 break; 327 case MTK_DPI_OUT_CHANNEL_SWAP_BGR: 328 val = SWAP_BGR; 329 break; 330 default: 331 val = SWAP_RGB; 332 break; 333 } 334 335 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); 336 } 337 338 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) 339 { 340 mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); 341 } 342 343 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) 344 { 345 mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); 346 } 347 348 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) 349 { 350 mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP); 351 } 352 353 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi) 354 { 355 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N); 356 } 357 358 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) 359 { 360 if (dpi->conf->edge_sel_en) 361 mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); 362 } 363 364 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, 365 enum mtk_dpi_out_color_format format) 366 { 367 if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) || 368 (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { 369 mtk_dpi_config_yuv422_enable(dpi, false); 370 mtk_dpi_config_csc_enable(dpi, true); 371 mtk_dpi_config_swap_input(dpi, false); 372 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); 373 } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || 374 (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { 375 mtk_dpi_config_yuv422_enable(dpi, true); 376 mtk_dpi_config_csc_enable(dpi, true); 377 mtk_dpi_config_swap_input(dpi, true); 378 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 379 } else { 380 mtk_dpi_config_yuv422_enable(dpi, false); 381 mtk_dpi_config_csc_enable(dpi, false); 382 mtk_dpi_config_swap_input(dpi, false); 383 mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); 384 } 385 } 386 387 static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) 388 { 389 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 390 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) { 391 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 392 DDR_EN | DDR_4PHASE); 393 mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, 394 dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE ? 395 EDGE_SEL : 0, EDGE_SEL); 396 } else { 397 mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0); 398 } 399 } 400 401 static void mtk_dpi_power_off(struct mtk_dpi *dpi) 402 { 403 if (WARN_ON(dpi->refcount == 0)) 404 return; 405 406 if (--dpi->refcount != 0) 407 return; 408 409 if (dpi->pinctrl && dpi->pins_gpio) 410 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 411 412 mtk_dpi_disable(dpi); 413 clk_disable_unprepare(dpi->pixel_clk); 414 clk_disable_unprepare(dpi->engine_clk); 415 } 416 417 static int mtk_dpi_power_on(struct mtk_dpi *dpi) 418 { 419 int ret; 420 421 if (++dpi->refcount != 1) 422 return 0; 423 424 ret = clk_prepare_enable(dpi->engine_clk); 425 if (ret) { 426 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 427 goto err_refcount; 428 } 429 430 ret = clk_prepare_enable(dpi->pixel_clk); 431 if (ret) { 432 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 433 goto err_pixel; 434 } 435 436 if (dpi->pinctrl && dpi->pins_dpi) 437 pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); 438 439 mtk_dpi_enable(dpi); 440 return 0; 441 442 err_pixel: 443 clk_disable_unprepare(dpi->engine_clk); 444 err_refcount: 445 dpi->refcount--; 446 return ret; 447 } 448 449 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 450 struct drm_display_mode *mode) 451 { 452 struct mtk_dpi_yc_limit limit; 453 struct mtk_dpi_polarities dpi_pol; 454 struct mtk_dpi_sync_param hsync; 455 struct mtk_dpi_sync_param vsync_lodd = { 0 }; 456 struct mtk_dpi_sync_param vsync_leven = { 0 }; 457 struct mtk_dpi_sync_param vsync_rodd = { 0 }; 458 struct mtk_dpi_sync_param vsync_reven = { 0 }; 459 struct videomode vm = { 0 }; 460 unsigned long pll_rate; 461 unsigned int factor; 462 463 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ 464 factor = dpi->conf->cal_factor(mode->clock); 465 drm_display_mode_to_videomode(mode, &vm); 466 pll_rate = vm.pixelclock * factor; 467 468 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 469 pll_rate, vm.pixelclock); 470 471 clk_set_rate(dpi->tvd_clk, pll_rate); 472 pll_rate = clk_get_rate(dpi->tvd_clk); 473 474 vm.pixelclock = pll_rate / factor; 475 if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || 476 (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) 477 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); 478 else 479 clk_set_rate(dpi->pixel_clk, vm.pixelclock); 480 481 482 vm.pixelclock = clk_get_rate(dpi->pixel_clk); 483 484 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 485 pll_rate, vm.pixelclock); 486 487 limit.c_bottom = 0x0010; 488 limit.c_top = 0x0FE0; 489 limit.y_bottom = 0x0010; 490 limit.y_top = 0x0FE0; 491 492 dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; 493 dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; 494 dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? 495 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 496 dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? 497 MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; 498 hsync.sync_width = vm.hsync_len; 499 hsync.back_porch = vm.hback_porch; 500 hsync.front_porch = vm.hfront_porch; 501 hsync.shift_half_line = false; 502 vsync_lodd.sync_width = vm.vsync_len; 503 vsync_lodd.back_porch = vm.vback_porch; 504 vsync_lodd.front_porch = vm.vfront_porch; 505 vsync_lodd.shift_half_line = false; 506 507 if (vm.flags & DISPLAY_FLAGS_INTERLACED && 508 mode->flags & DRM_MODE_FLAG_3D_MASK) { 509 vsync_leven = vsync_lodd; 510 vsync_rodd = vsync_lodd; 511 vsync_reven = vsync_lodd; 512 vsync_leven.shift_half_line = true; 513 vsync_reven.shift_half_line = true; 514 } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && 515 !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { 516 vsync_leven = vsync_lodd; 517 vsync_leven.shift_half_line = true; 518 } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && 519 mode->flags & DRM_MODE_FLAG_3D_MASK) { 520 vsync_rodd = vsync_lodd; 521 } 522 mtk_dpi_sw_reset(dpi, true); 523 mtk_dpi_config_pol(dpi, &dpi_pol); 524 525 mtk_dpi_config_hsync(dpi, &hsync); 526 mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); 527 mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); 528 mtk_dpi_config_vsync_leven(dpi, &vsync_leven); 529 mtk_dpi_config_vsync_reven(dpi, &vsync_reven); 530 531 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); 532 mtk_dpi_config_interface(dpi, !!(vm.flags & 533 DISPLAY_FLAGS_INTERLACED)); 534 if (vm.flags & DISPLAY_FLAGS_INTERLACED) 535 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); 536 else 537 mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); 538 539 mtk_dpi_config_channel_limit(dpi, &limit); 540 mtk_dpi_config_bit_num(dpi, dpi->bit_num); 541 mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); 542 mtk_dpi_config_yc_map(dpi, dpi->yc_map); 543 mtk_dpi_config_color_format(dpi, dpi->color_format); 544 mtk_dpi_config_2n_h_fre(dpi); 545 mtk_dpi_dual_edge(dpi); 546 mtk_dpi_config_disable_edge(dpi); 547 mtk_dpi_sw_reset(dpi, false); 548 549 return 0; 550 } 551 552 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 553 struct drm_bridge_state *bridge_state, 554 struct drm_crtc_state *crtc_state, 555 struct drm_connector_state *conn_state, 556 unsigned int *num_output_fmts) 557 { 558 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 559 u32 *output_fmts; 560 561 *num_output_fmts = 0; 562 563 if (!dpi->conf->output_fmts) { 564 dev_err(dpi->dev, "output_fmts should not be null\n"); 565 return NULL; 566 } 567 568 output_fmts = kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts), 569 GFP_KERNEL); 570 if (!output_fmts) 571 return NULL; 572 573 *num_output_fmts = dpi->conf->num_output_fmts; 574 575 memcpy(output_fmts, dpi->conf->output_fmts, 576 sizeof(*output_fmts) * dpi->conf->num_output_fmts); 577 578 return output_fmts; 579 } 580 581 static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 582 struct drm_bridge_state *bridge_state, 583 struct drm_crtc_state *crtc_state, 584 struct drm_connector_state *conn_state, 585 u32 output_fmt, 586 unsigned int *num_input_fmts) 587 { 588 u32 *input_fmts; 589 590 *num_input_fmts = 0; 591 592 input_fmts = kcalloc(1, sizeof(*input_fmts), 593 GFP_KERNEL); 594 if (!input_fmts) 595 return NULL; 596 597 *num_input_fmts = 1; 598 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 599 600 return input_fmts; 601 } 602 603 static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, 604 struct drm_bridge_state *bridge_state, 605 struct drm_crtc_state *crtc_state, 606 struct drm_connector_state *conn_state) 607 { 608 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 609 unsigned int out_bus_format; 610 611 out_bus_format = bridge_state->output_bus_cfg.format; 612 613 if (out_bus_format == MEDIA_BUS_FMT_FIXED) 614 if (dpi->conf->num_output_fmts) 615 out_bus_format = dpi->conf->output_fmts[0]; 616 617 dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", 618 bridge_state->input_bus_cfg.format, 619 bridge_state->output_bus_cfg.format); 620 621 dpi->output_fmt = out_bus_format; 622 dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; 623 dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; 624 dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; 625 dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; 626 627 return 0; 628 } 629 630 static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, 631 enum drm_bridge_attach_flags flags) 632 { 633 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 634 635 return drm_bridge_attach(bridge->encoder, dpi->next_bridge, 636 &dpi->bridge, flags); 637 } 638 639 static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, 640 const struct drm_display_mode *mode, 641 const struct drm_display_mode *adjusted_mode) 642 { 643 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 644 645 drm_mode_copy(&dpi->mode, adjusted_mode); 646 } 647 648 static void mtk_dpi_bridge_disable(struct drm_bridge *bridge) 649 { 650 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 651 652 mtk_dpi_power_off(dpi); 653 } 654 655 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) 656 { 657 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 658 659 mtk_dpi_power_on(dpi); 660 mtk_dpi_set_display_mode(dpi, &dpi->mode); 661 } 662 663 static enum drm_mode_status 664 mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, 665 const struct drm_display_info *info, 666 const struct drm_display_mode *mode) 667 { 668 struct mtk_dpi *dpi = bridge_to_dpi(bridge); 669 670 if (mode->clock > dpi->conf->max_clock_khz) 671 return MODE_CLOCK_HIGH; 672 673 return MODE_OK; 674 } 675 676 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { 677 .attach = mtk_dpi_bridge_attach, 678 .mode_set = mtk_dpi_bridge_mode_set, 679 .mode_valid = mtk_dpi_bridge_mode_valid, 680 .disable = mtk_dpi_bridge_disable, 681 .enable = mtk_dpi_bridge_enable, 682 .atomic_check = mtk_dpi_bridge_atomic_check, 683 .atomic_get_output_bus_fmts = mtk_dpi_bridge_atomic_get_output_bus_fmts, 684 .atomic_get_input_bus_fmts = mtk_dpi_bridge_atomic_get_input_bus_fmts, 685 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 686 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 687 .atomic_reset = drm_atomic_helper_bridge_reset, 688 }; 689 690 void mtk_dpi_start(struct device *dev) 691 { 692 struct mtk_dpi *dpi = dev_get_drvdata(dev); 693 694 mtk_dpi_power_on(dpi); 695 } 696 697 void mtk_dpi_stop(struct device *dev) 698 { 699 struct mtk_dpi *dpi = dev_get_drvdata(dev); 700 701 mtk_dpi_power_off(dpi); 702 } 703 704 static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) 705 { 706 struct mtk_dpi *dpi = dev_get_drvdata(dev); 707 struct drm_device *drm_dev = data; 708 int ret; 709 710 ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, 711 DRM_MODE_ENCODER_TMDS); 712 if (ret) { 713 dev_err(dev, "Failed to initialize decoder: %d\n", ret); 714 return ret; 715 } 716 717 dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev); 718 719 ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 720 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 721 if (ret) 722 goto err_cleanup; 723 724 dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder); 725 if (IS_ERR(dpi->connector)) { 726 dev_err(dev, "Unable to create bridge connector\n"); 727 ret = PTR_ERR(dpi->connector); 728 goto err_cleanup; 729 } 730 drm_connector_attach_encoder(dpi->connector, &dpi->encoder); 731 732 return 0; 733 734 err_cleanup: 735 drm_encoder_cleanup(&dpi->encoder); 736 return ret; 737 } 738 739 static void mtk_dpi_unbind(struct device *dev, struct device *master, 740 void *data) 741 { 742 struct mtk_dpi *dpi = dev_get_drvdata(dev); 743 744 drm_encoder_cleanup(&dpi->encoder); 745 } 746 747 static const struct component_ops mtk_dpi_component_ops = { 748 .bind = mtk_dpi_bind, 749 .unbind = mtk_dpi_unbind, 750 }; 751 752 static unsigned int mt8173_calculate_factor(int clock) 753 { 754 if (clock <= 27000) 755 return 3 << 4; 756 else if (clock <= 84000) 757 return 3 << 3; 758 else if (clock <= 167000) 759 return 3 << 2; 760 else 761 return 3 << 1; 762 } 763 764 static unsigned int mt2701_calculate_factor(int clock) 765 { 766 if (clock <= 64000) 767 return 4; 768 else if (clock <= 128000) 769 return 2; 770 else 771 return 1; 772 } 773 774 static unsigned int mt8183_calculate_factor(int clock) 775 { 776 if (clock <= 27000) 777 return 8; 778 else if (clock <= 167000) 779 return 4; 780 else 781 return 2; 782 } 783 784 static const u32 mt8173_output_fmts[] = { 785 MEDIA_BUS_FMT_RGB888_1X24, 786 }; 787 788 static const u32 mt8183_output_fmts[] = { 789 MEDIA_BUS_FMT_RGB888_2X12_LE, 790 MEDIA_BUS_FMT_RGB888_2X12_BE, 791 }; 792 793 static const struct mtk_dpi_conf mt8173_conf = { 794 .cal_factor = mt8173_calculate_factor, 795 .reg_h_fre_con = 0xe0, 796 .max_clock_khz = 300000, 797 .output_fmts = mt8173_output_fmts, 798 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 799 }; 800 801 static const struct mtk_dpi_conf mt2701_conf = { 802 .cal_factor = mt2701_calculate_factor, 803 .reg_h_fre_con = 0xb0, 804 .edge_sel_en = true, 805 .max_clock_khz = 150000, 806 .output_fmts = mt8173_output_fmts, 807 .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), 808 }; 809 810 static const struct mtk_dpi_conf mt8183_conf = { 811 .cal_factor = mt8183_calculate_factor, 812 .reg_h_fre_con = 0xe0, 813 .max_clock_khz = 100000, 814 .output_fmts = mt8183_output_fmts, 815 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 816 }; 817 818 static const struct mtk_dpi_conf mt8192_conf = { 819 .cal_factor = mt8183_calculate_factor, 820 .reg_h_fre_con = 0xe0, 821 .max_clock_khz = 150000, 822 .output_fmts = mt8183_output_fmts, 823 .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), 824 }; 825 826 static int mtk_dpi_probe(struct platform_device *pdev) 827 { 828 struct device *dev = &pdev->dev; 829 struct mtk_dpi *dpi; 830 struct resource *mem; 831 int ret; 832 833 dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); 834 if (!dpi) 835 return -ENOMEM; 836 837 dpi->dev = dev; 838 dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); 839 dpi->output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 840 841 dpi->pinctrl = devm_pinctrl_get(&pdev->dev); 842 if (IS_ERR(dpi->pinctrl)) { 843 dpi->pinctrl = NULL; 844 dev_dbg(&pdev->dev, "Cannot find pinctrl!\n"); 845 } 846 if (dpi->pinctrl) { 847 dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep"); 848 if (IS_ERR(dpi->pins_gpio)) { 849 dpi->pins_gpio = NULL; 850 dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n"); 851 } 852 if (dpi->pins_gpio) 853 pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); 854 855 dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default"); 856 if (IS_ERR(dpi->pins_dpi)) { 857 dpi->pins_dpi = NULL; 858 dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n"); 859 } 860 } 861 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 862 dpi->regs = devm_ioremap_resource(dev, mem); 863 if (IS_ERR(dpi->regs)) { 864 ret = PTR_ERR(dpi->regs); 865 dev_err(dev, "Failed to ioremap mem resource: %d\n", ret); 866 return ret; 867 } 868 869 dpi->engine_clk = devm_clk_get(dev, "engine"); 870 if (IS_ERR(dpi->engine_clk)) { 871 ret = PTR_ERR(dpi->engine_clk); 872 if (ret != -EPROBE_DEFER) 873 dev_err(dev, "Failed to get engine clock: %d\n", ret); 874 875 return ret; 876 } 877 878 dpi->pixel_clk = devm_clk_get(dev, "pixel"); 879 if (IS_ERR(dpi->pixel_clk)) { 880 ret = PTR_ERR(dpi->pixel_clk); 881 if (ret != -EPROBE_DEFER) 882 dev_err(dev, "Failed to get pixel clock: %d\n", ret); 883 884 return ret; 885 } 886 887 dpi->tvd_clk = devm_clk_get(dev, "pll"); 888 if (IS_ERR(dpi->tvd_clk)) { 889 ret = PTR_ERR(dpi->tvd_clk); 890 if (ret != -EPROBE_DEFER) 891 dev_err(dev, "Failed to get tvdpll clock: %d\n", ret); 892 893 return ret; 894 } 895 896 dpi->irq = platform_get_irq(pdev, 0); 897 if (dpi->irq <= 0) 898 return -EINVAL; 899 900 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, 901 NULL, &dpi->next_bridge); 902 if (ret) 903 return ret; 904 905 dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node); 906 907 platform_set_drvdata(pdev, dpi); 908 909 dpi->bridge.funcs = &mtk_dpi_bridge_funcs; 910 dpi->bridge.of_node = dev->of_node; 911 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI; 912 913 drm_bridge_add(&dpi->bridge); 914 915 ret = component_add(dev, &mtk_dpi_component_ops); 916 if (ret) { 917 drm_bridge_remove(&dpi->bridge); 918 dev_err(dev, "Failed to add component: %d\n", ret); 919 return ret; 920 } 921 922 return 0; 923 } 924 925 static int mtk_dpi_remove(struct platform_device *pdev) 926 { 927 struct mtk_dpi *dpi = platform_get_drvdata(pdev); 928 929 component_del(&pdev->dev, &mtk_dpi_component_ops); 930 drm_bridge_remove(&dpi->bridge); 931 932 return 0; 933 } 934 935 static const struct of_device_id mtk_dpi_of_ids[] = { 936 { .compatible = "mediatek,mt2701-dpi", 937 .data = &mt2701_conf, 938 }, 939 { .compatible = "mediatek,mt8173-dpi", 940 .data = &mt8173_conf, 941 }, 942 { .compatible = "mediatek,mt8183-dpi", 943 .data = &mt8183_conf, 944 }, 945 { .compatible = "mediatek,mt8192-dpi", 946 .data = &mt8192_conf, 947 }, 948 { }, 949 }; 950 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); 951 952 struct platform_driver mtk_dpi_driver = { 953 .probe = mtk_dpi_probe, 954 .remove = mtk_dpi_remove, 955 .driver = { 956 .name = "mediatek-dpi", 957 .of_match_table = mtk_dpi_of_ids, 958 }, 959 }; 960