1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/of_irq.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/soc/mediatek/mtk-cmdq.h> 14 15 #include "mtk_disp_drv.h" 16 #include "mtk_drm_crtc.h" 17 #include "mtk_drm_ddp_comp.h" 18 19 #define DISP_REG_RDMA_INT_ENABLE 0x0000 20 #define DISP_REG_RDMA_INT_STATUS 0x0004 21 #define RDMA_TARGET_LINE_INT BIT(5) 22 #define RDMA_FIFO_UNDERFLOW_INT BIT(4) 23 #define RDMA_EOF_ABNORMAL_INT BIT(3) 24 #define RDMA_FRAME_END_INT BIT(2) 25 #define RDMA_FRAME_START_INT BIT(1) 26 #define RDMA_REG_UPDATE_INT BIT(0) 27 #define DISP_REG_RDMA_GLOBAL_CON 0x0010 28 #define RDMA_ENGINE_EN BIT(0) 29 #define RDMA_MODE_MEMORY BIT(1) 30 #define DISP_REG_RDMA_SIZE_CON_0 0x0014 31 #define RDMA_MATRIX_ENABLE BIT(17) 32 #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20) 33 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20) 34 #define DISP_REG_RDMA_SIZE_CON_1 0x0018 35 #define DISP_REG_RDMA_TARGET_LINE 0x001c 36 #define DISP_RDMA_MEM_CON 0x0024 37 #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4) 38 #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4) 39 #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4) 40 #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4) 41 #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4) 42 #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4) 43 #define MEM_MODE_INPUT_SWAP BIT(8) 44 #define DISP_RDMA_MEM_SRC_PITCH 0x002c 45 #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030 46 #define DISP_REG_RDMA_FIFO_CON 0x0040 47 #define RDMA_FIFO_UNDERFLOW_EN BIT(31) 48 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) 49 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) 50 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) 51 #define DISP_RDMA_MEM_START_ADDR 0x0f00 52 53 #define RDMA_MEM_GMC 0x40402020 54 55 struct mtk_disp_rdma_data { 56 unsigned int fifo_size; 57 }; 58 59 /* 60 * struct mtk_disp_rdma - DISP_RDMA driver structure 61 * @data: local driver data 62 */ 63 struct mtk_disp_rdma { 64 struct clk *clk; 65 void __iomem *regs; 66 struct cmdq_client_reg cmdq_reg; 67 const struct mtk_disp_rdma_data *data; 68 void (*vblank_cb)(void *data); 69 void *vblank_cb_data; 70 u32 fifo_size; 71 }; 72 73 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) 74 { 75 struct mtk_disp_rdma *priv = dev_id; 76 77 /* Clear frame completion interrupt */ 78 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); 79 80 if (!priv->vblank_cb) 81 return IRQ_NONE; 82 83 priv->vblank_cb(priv->vblank_cb_data); 84 85 return IRQ_HANDLED; 86 } 87 88 static void rdma_update_bits(struct device *dev, unsigned int reg, 89 unsigned int mask, unsigned int val) 90 { 91 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); 92 unsigned int tmp = readl(rdma->regs + reg); 93 94 tmp = (tmp & ~mask) | (val & mask); 95 writel(tmp, rdma->regs + reg); 96 } 97 98 void mtk_rdma_enable_vblank(struct device *dev, 99 void (*vblank_cb)(void *), 100 void *vblank_cb_data) 101 { 102 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); 103 104 rdma->vblank_cb = vblank_cb; 105 rdma->vblank_cb_data = vblank_cb_data; 106 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 107 RDMA_FRAME_END_INT); 108 } 109 110 void mtk_rdma_disable_vblank(struct device *dev) 111 { 112 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); 113 114 rdma->vblank_cb = NULL; 115 rdma->vblank_cb_data = NULL; 116 rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); 117 } 118 119 int mtk_rdma_clk_enable(struct device *dev) 120 { 121 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); 122 123 return clk_prepare_enable(rdma->clk); 124 } 125 126 void mtk_rdma_clk_disable(struct device *dev) 127 { 128 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); 129 130 clk_disable_unprepare(rdma->clk); 131 } 132 133 void mtk_rdma_start(struct device *dev) 134 { 135 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 136 RDMA_ENGINE_EN); 137 } 138 139 void mtk_rdma_stop(struct device *dev) 140 { 141 rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); 142 } 143 144 void mtk_rdma_config(struct device *dev, unsigned int width, 145 unsigned int height, unsigned int vrefresh, 146 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 147 { 148 unsigned int threshold; 149 unsigned int reg; 150 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); 151 u32 rdma_fifo_size; 152 153 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, 154 DISP_REG_RDMA_SIZE_CON_0, 0xfff); 155 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, 156 DISP_REG_RDMA_SIZE_CON_1, 0xfffff); 157 158 if (rdma->fifo_size) 159 rdma_fifo_size = rdma->fifo_size; 160 else 161 rdma_fifo_size = RDMA_FIFO_SIZE(rdma); 162 163 /* 164 * Enable FIFO underflow since DSI and DPI can't be blocked. 165 * Keep the FIFO pseudo size reset default of 8 KiB. Set the 166 * output threshold to 70% of max fifo size to make sure the 167 * threhold will not overflow 168 */ 169 threshold = rdma_fifo_size * 7 / 10; 170 reg = RDMA_FIFO_UNDERFLOW_EN | 171 RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | 172 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); 173 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); 174 } 175 176 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, 177 unsigned int fmt) 178 { 179 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 180 * is defined in mediatek HW data sheet. 181 * The alphabet order in XXX is no relation to data 182 * arrangement in memory. 183 */ 184 switch (fmt) { 185 default: 186 case DRM_FORMAT_RGB565: 187 return MEM_MODE_INPUT_FORMAT_RGB565; 188 case DRM_FORMAT_BGR565: 189 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP; 190 case DRM_FORMAT_RGB888: 191 return MEM_MODE_INPUT_FORMAT_RGB888; 192 case DRM_FORMAT_BGR888: 193 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP; 194 case DRM_FORMAT_RGBX8888: 195 case DRM_FORMAT_RGBA8888: 196 return MEM_MODE_INPUT_FORMAT_ARGB8888; 197 case DRM_FORMAT_BGRX8888: 198 case DRM_FORMAT_BGRA8888: 199 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP; 200 case DRM_FORMAT_XRGB8888: 201 case DRM_FORMAT_ARGB8888: 202 return MEM_MODE_INPUT_FORMAT_RGBA8888; 203 case DRM_FORMAT_XBGR8888: 204 case DRM_FORMAT_ABGR8888: 205 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP; 206 case DRM_FORMAT_UYVY: 207 return MEM_MODE_INPUT_FORMAT_UYVY; 208 case DRM_FORMAT_YUYV: 209 return MEM_MODE_INPUT_FORMAT_YUYV; 210 } 211 } 212 213 unsigned int mtk_rdma_layer_nr(struct device *dev) 214 { 215 return 1; 216 } 217 218 void mtk_rdma_layer_config(struct device *dev, unsigned int idx, 219 struct mtk_plane_state *state, 220 struct cmdq_pkt *cmdq_pkt) 221 { 222 struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); 223 struct mtk_plane_pending_state *pending = &state->pending; 224 unsigned int addr = pending->addr; 225 unsigned int pitch = pending->pitch & 0xffff; 226 unsigned int fmt = pending->format; 227 unsigned int con; 228 229 con = rdma_fmt_convert(rdma, fmt); 230 mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON); 231 232 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { 233 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs, 234 DISP_REG_RDMA_SIZE_CON_0, 235 RDMA_MATRIX_ENABLE); 236 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, 237 &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, 238 RDMA_MATRIX_INT_MTX_SEL); 239 } else { 240 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs, 241 DISP_REG_RDMA_SIZE_CON_0, 242 RDMA_MATRIX_ENABLE); 243 } 244 mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs, 245 DISP_RDMA_MEM_START_ADDR); 246 mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs, 247 DISP_RDMA_MEM_SRC_PITCH); 248 mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs, 249 DISP_RDMA_MEM_GMC_SETTING_0); 250 mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs, 251 DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY); 252 253 } 254 255 static int mtk_disp_rdma_bind(struct device *dev, struct device *master, 256 void *data) 257 { 258 return 0; 259 260 } 261 262 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master, 263 void *data) 264 { 265 } 266 267 static const struct component_ops mtk_disp_rdma_component_ops = { 268 .bind = mtk_disp_rdma_bind, 269 .unbind = mtk_disp_rdma_unbind, 270 }; 271 272 static int mtk_disp_rdma_probe(struct platform_device *pdev) 273 { 274 struct device *dev = &pdev->dev; 275 struct mtk_disp_rdma *priv; 276 struct resource *res; 277 int irq; 278 int ret; 279 280 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 281 if (!priv) 282 return -ENOMEM; 283 284 irq = platform_get_irq(pdev, 0); 285 if (irq < 0) 286 return irq; 287 288 priv->clk = devm_clk_get(dev, NULL); 289 if (IS_ERR(priv->clk)) { 290 dev_err(dev, "failed to get rdma clk\n"); 291 return PTR_ERR(priv->clk); 292 } 293 294 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 295 priv->regs = devm_ioremap_resource(dev, res); 296 if (IS_ERR(priv->regs)) { 297 dev_err(dev, "failed to ioremap rdma\n"); 298 return PTR_ERR(priv->regs); 299 } 300 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 301 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); 302 if (ret) 303 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); 304 #endif 305 306 if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) { 307 ret = of_property_read_u32(dev->of_node, 308 "mediatek,rdma-fifo-size", 309 &priv->fifo_size); 310 if (ret) { 311 dev_err(dev, "Failed to get rdma fifo size\n"); 312 return ret; 313 } 314 } 315 316 /* Disable and clear pending interrupts */ 317 writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE); 318 writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); 319 320 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler, 321 IRQF_TRIGGER_NONE, dev_name(dev), priv); 322 if (ret < 0) { 323 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 324 return ret; 325 } 326 327 priv->data = of_device_get_match_data(dev); 328 329 platform_set_drvdata(pdev, priv); 330 331 pm_runtime_enable(dev); 332 333 ret = component_add(dev, &mtk_disp_rdma_component_ops); 334 if (ret) { 335 pm_runtime_disable(dev); 336 dev_err(dev, "Failed to add component: %d\n", ret); 337 } 338 339 return ret; 340 } 341 342 static int mtk_disp_rdma_remove(struct platform_device *pdev) 343 { 344 component_del(&pdev->dev, &mtk_disp_rdma_component_ops); 345 346 pm_runtime_disable(&pdev->dev); 347 348 return 0; 349 } 350 351 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { 352 .fifo_size = SZ_4K, 353 }; 354 355 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { 356 .fifo_size = SZ_8K, 357 }; 358 359 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { 360 .fifo_size = 5 * SZ_1K, 361 }; 362 363 static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { 364 .fifo_size = 5 * SZ_1K, 365 }; 366 367 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { 368 { .compatible = "mediatek,mt2701-disp-rdma", 369 .data = &mt2701_rdma_driver_data}, 370 { .compatible = "mediatek,mt8173-disp-rdma", 371 .data = &mt8173_rdma_driver_data}, 372 { .compatible = "mediatek,mt8183-disp-rdma", 373 .data = &mt8183_rdma_driver_data}, 374 { .compatible = "mediatek,mt8192-disp-rdma", 375 .data = &mt8192_rdma_driver_data}, 376 {}, 377 }; 378 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); 379 380 struct platform_driver mtk_disp_rdma_driver = { 381 .probe = mtk_disp_rdma_probe, 382 .remove = mtk_disp_rdma_remove, 383 .driver = { 384 .name = "mediatek-disp-rdma", 385 .owner = THIS_MODULE, 386 .of_match_table = mtk_disp_rdma_driver_dt_match, 387 }, 388 }; 389