1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/of_irq.h> 11 #include <linux/platform_device.h> 12 #include <linux/soc/mediatek/mtk-cmdq.h> 13 14 #include "mtk_drm_crtc.h" 15 #include "mtk_drm_ddp_comp.h" 16 17 #define DISP_REG_RDMA_INT_ENABLE 0x0000 18 #define DISP_REG_RDMA_INT_STATUS 0x0004 19 #define RDMA_TARGET_LINE_INT BIT(5) 20 #define RDMA_FIFO_UNDERFLOW_INT BIT(4) 21 #define RDMA_EOF_ABNORMAL_INT BIT(3) 22 #define RDMA_FRAME_END_INT BIT(2) 23 #define RDMA_FRAME_START_INT BIT(1) 24 #define RDMA_REG_UPDATE_INT BIT(0) 25 #define DISP_REG_RDMA_GLOBAL_CON 0x0010 26 #define RDMA_ENGINE_EN BIT(0) 27 #define RDMA_MODE_MEMORY BIT(1) 28 #define DISP_REG_RDMA_SIZE_CON_0 0x0014 29 #define RDMA_MATRIX_ENABLE BIT(17) 30 #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20) 31 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20) 32 #define DISP_REG_RDMA_SIZE_CON_1 0x0018 33 #define DISP_REG_RDMA_TARGET_LINE 0x001c 34 #define DISP_RDMA_MEM_CON 0x0024 35 #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4) 36 #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4) 37 #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4) 38 #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4) 39 #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4) 40 #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4) 41 #define MEM_MODE_INPUT_SWAP BIT(8) 42 #define DISP_RDMA_MEM_SRC_PITCH 0x002c 43 #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030 44 #define DISP_REG_RDMA_FIFO_CON 0x0040 45 #define RDMA_FIFO_UNDERFLOW_EN BIT(31) 46 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) 47 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) 48 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) 49 #define DISP_RDMA_MEM_START_ADDR 0x0f00 50 51 #define RDMA_MEM_GMC 0x40402020 52 53 struct mtk_disp_rdma_data { 54 unsigned int fifo_size; 55 }; 56 57 /** 58 * struct mtk_disp_rdma - DISP_RDMA driver structure 59 * @ddp_comp: structure containing type enum and hardware resources 60 * @crtc: associated crtc to report irq events to 61 * @data: local driver data 62 */ 63 struct mtk_disp_rdma { 64 struct mtk_ddp_comp ddp_comp; 65 struct drm_crtc *crtc; 66 const struct mtk_disp_rdma_data *data; 67 }; 68 69 static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) 70 { 71 return container_of(comp, struct mtk_disp_rdma, ddp_comp); 72 } 73 74 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) 75 { 76 struct mtk_disp_rdma *priv = dev_id; 77 struct mtk_ddp_comp *rdma = &priv->ddp_comp; 78 79 /* Clear frame completion interrupt */ 80 writel(0x0, rdma->regs + DISP_REG_RDMA_INT_STATUS); 81 82 if (!priv->crtc) 83 return IRQ_NONE; 84 85 mtk_crtc_ddp_irq(priv->crtc, rdma); 86 87 return IRQ_HANDLED; 88 } 89 90 static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg, 91 unsigned int mask, unsigned int val) 92 { 93 unsigned int tmp = readl(comp->regs + reg); 94 95 tmp = (tmp & ~mask) | (val & mask); 96 writel(tmp, comp->regs + reg); 97 } 98 99 static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp, 100 struct drm_crtc *crtc) 101 { 102 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 103 104 rdma->crtc = crtc; 105 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 106 RDMA_FRAME_END_INT); 107 } 108 109 static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp) 110 { 111 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 112 113 rdma->crtc = NULL; 114 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); 115 } 116 117 static void mtk_rdma_start(struct mtk_ddp_comp *comp) 118 { 119 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 120 RDMA_ENGINE_EN); 121 } 122 123 static void mtk_rdma_stop(struct mtk_ddp_comp *comp) 124 { 125 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); 126 } 127 128 static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, 129 unsigned int height, unsigned int vrefresh, 130 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 131 { 132 unsigned int threshold; 133 unsigned int reg; 134 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 135 136 mtk_ddp_write_mask(cmdq_pkt, width, comp, 137 DISP_REG_RDMA_SIZE_CON_0, 0xfff); 138 mtk_ddp_write_mask(cmdq_pkt, height, comp, 139 DISP_REG_RDMA_SIZE_CON_1, 0xfffff); 140 141 /* 142 * Enable FIFO underflow since DSI and DPI can't be blocked. 143 * Keep the FIFO pseudo size reset default of 8 KiB. Set the 144 * output threshold to 6 microseconds with 7/6 overhead to 145 * account for blanking, and with a pixel depth of 4 bytes: 146 */ 147 threshold = width * height * vrefresh * 4 * 7 / 1000000; 148 reg = RDMA_FIFO_UNDERFLOW_EN | 149 RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | 150 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); 151 mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); 152 } 153 154 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, 155 unsigned int fmt) 156 { 157 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 158 * is defined in mediatek HW data sheet. 159 * The alphabet order in XXX is no relation to data 160 * arrangement in memory. 161 */ 162 switch (fmt) { 163 default: 164 case DRM_FORMAT_RGB565: 165 return MEM_MODE_INPUT_FORMAT_RGB565; 166 case DRM_FORMAT_BGR565: 167 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP; 168 case DRM_FORMAT_RGB888: 169 return MEM_MODE_INPUT_FORMAT_RGB888; 170 case DRM_FORMAT_BGR888: 171 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP; 172 case DRM_FORMAT_RGBX8888: 173 case DRM_FORMAT_RGBA8888: 174 return MEM_MODE_INPUT_FORMAT_ARGB8888; 175 case DRM_FORMAT_BGRX8888: 176 case DRM_FORMAT_BGRA8888: 177 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP; 178 case DRM_FORMAT_XRGB8888: 179 case DRM_FORMAT_ARGB8888: 180 return MEM_MODE_INPUT_FORMAT_RGBA8888; 181 case DRM_FORMAT_XBGR8888: 182 case DRM_FORMAT_ABGR8888: 183 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP; 184 case DRM_FORMAT_UYVY: 185 return MEM_MODE_INPUT_FORMAT_UYVY; 186 case DRM_FORMAT_YUYV: 187 return MEM_MODE_INPUT_FORMAT_YUYV; 188 } 189 } 190 191 static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) 192 { 193 return 1; 194 } 195 196 static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 197 struct mtk_plane_state *state, 198 struct cmdq_pkt *cmdq_pkt) 199 { 200 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 201 struct mtk_plane_pending_state *pending = &state->pending; 202 unsigned int addr = pending->addr; 203 unsigned int pitch = pending->pitch & 0xffff; 204 unsigned int fmt = pending->format; 205 unsigned int con; 206 207 con = rdma_fmt_convert(rdma, fmt); 208 mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON); 209 210 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { 211 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp, 212 DISP_REG_RDMA_SIZE_CON_0, 213 RDMA_MATRIX_ENABLE); 214 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, 215 comp, DISP_REG_RDMA_SIZE_CON_0, 216 RDMA_MATRIX_INT_MTX_SEL); 217 } else { 218 mtk_ddp_write_mask(cmdq_pkt, 0, comp, 219 DISP_REG_RDMA_SIZE_CON_0, 220 RDMA_MATRIX_ENABLE); 221 } 222 mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR); 223 mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH); 224 mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp, 225 DISP_RDMA_MEM_GMC_SETTING_0); 226 mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp, 227 DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY); 228 229 } 230 231 static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { 232 .config = mtk_rdma_config, 233 .start = mtk_rdma_start, 234 .stop = mtk_rdma_stop, 235 .enable_vblank = mtk_rdma_enable_vblank, 236 .disable_vblank = mtk_rdma_disable_vblank, 237 .layer_nr = mtk_rdma_layer_nr, 238 .layer_config = mtk_rdma_layer_config, 239 }; 240 241 static int mtk_disp_rdma_bind(struct device *dev, struct device *master, 242 void *data) 243 { 244 struct mtk_disp_rdma *priv = dev_get_drvdata(dev); 245 struct drm_device *drm_dev = data; 246 int ret; 247 248 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); 249 if (ret < 0) { 250 dev_err(dev, "Failed to register component %pOF: %d\n", 251 dev->of_node, ret); 252 return ret; 253 } 254 255 return 0; 256 257 } 258 259 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master, 260 void *data) 261 { 262 struct mtk_disp_rdma *priv = dev_get_drvdata(dev); 263 struct drm_device *drm_dev = data; 264 265 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); 266 } 267 268 static const struct component_ops mtk_disp_rdma_component_ops = { 269 .bind = mtk_disp_rdma_bind, 270 .unbind = mtk_disp_rdma_unbind, 271 }; 272 273 static int mtk_disp_rdma_probe(struct platform_device *pdev) 274 { 275 struct device *dev = &pdev->dev; 276 struct mtk_disp_rdma *priv; 277 int comp_id; 278 int irq; 279 int ret; 280 281 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 282 if (!priv) 283 return -ENOMEM; 284 285 irq = platform_get_irq(pdev, 0); 286 if (irq < 0) 287 return irq; 288 289 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); 290 if (comp_id < 0) { 291 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 292 return comp_id; 293 } 294 295 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, 296 &mtk_disp_rdma_funcs); 297 if (ret) { 298 if (ret != -EPROBE_DEFER) 299 dev_err(dev, "Failed to initialize component: %d\n", 300 ret); 301 302 return ret; 303 } 304 305 /* Disable and clear pending interrupts */ 306 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_ENABLE); 307 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_STATUS); 308 309 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler, 310 IRQF_TRIGGER_NONE, dev_name(dev), priv); 311 if (ret < 0) { 312 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 313 return ret; 314 } 315 316 priv->data = of_device_get_match_data(dev); 317 318 platform_set_drvdata(pdev, priv); 319 320 ret = component_add(dev, &mtk_disp_rdma_component_ops); 321 if (ret) 322 dev_err(dev, "Failed to add component: %d\n", ret); 323 324 return ret; 325 } 326 327 static int mtk_disp_rdma_remove(struct platform_device *pdev) 328 { 329 component_del(&pdev->dev, &mtk_disp_rdma_component_ops); 330 331 return 0; 332 } 333 334 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { 335 .fifo_size = SZ_4K, 336 }; 337 338 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { 339 .fifo_size = SZ_8K, 340 }; 341 342 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { 343 { .compatible = "mediatek,mt2701-disp-rdma", 344 .data = &mt2701_rdma_driver_data}, 345 { .compatible = "mediatek,mt8173-disp-rdma", 346 .data = &mt8173_rdma_driver_data}, 347 {}, 348 }; 349 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); 350 351 struct platform_driver mtk_disp_rdma_driver = { 352 .probe = mtk_disp_rdma_probe, 353 .remove = mtk_disp_rdma_remove, 354 .driver = { 355 .name = "mediatek-disp-rdma", 356 .owner = THIS_MODULE, 357 .of_match_table = mtk_disp_rdma_driver_dt_match, 358 }, 359 }; 360