1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <drm/drmP.h> 15 #include <linux/clk.h> 16 #include <linux/component.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 21 #include "mtk_drm_crtc.h" 22 #include "mtk_drm_ddp_comp.h" 23 24 #define DISP_REG_RDMA_INT_ENABLE 0x0000 25 #define DISP_REG_RDMA_INT_STATUS 0x0004 26 #define RDMA_TARGET_LINE_INT BIT(5) 27 #define RDMA_FIFO_UNDERFLOW_INT BIT(4) 28 #define RDMA_EOF_ABNORMAL_INT BIT(3) 29 #define RDMA_FRAME_END_INT BIT(2) 30 #define RDMA_FRAME_START_INT BIT(1) 31 #define RDMA_REG_UPDATE_INT BIT(0) 32 #define DISP_REG_RDMA_GLOBAL_CON 0x0010 33 #define RDMA_ENGINE_EN BIT(0) 34 #define RDMA_MODE_MEMORY BIT(1) 35 #define DISP_REG_RDMA_SIZE_CON_0 0x0014 36 #define RDMA_MATRIX_ENABLE BIT(17) 37 #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20) 38 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20) 39 #define DISP_REG_RDMA_SIZE_CON_1 0x0018 40 #define DISP_REG_RDMA_TARGET_LINE 0x001c 41 #define DISP_RDMA_MEM_CON 0x0024 42 #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4) 43 #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4) 44 #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4) 45 #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4) 46 #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4) 47 #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4) 48 #define MEM_MODE_INPUT_SWAP BIT(8) 49 #define DISP_RDMA_MEM_SRC_PITCH 0x002c 50 #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030 51 #define DISP_REG_RDMA_FIFO_CON 0x0040 52 #define RDMA_FIFO_UNDERFLOW_EN BIT(31) 53 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) 54 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) 55 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) 56 #define DISP_RDMA_MEM_START_ADDR 0x0f00 57 58 #define RDMA_MEM_GMC 0x40402020 59 60 struct mtk_disp_rdma_data { 61 unsigned int fifo_size; 62 }; 63 64 /** 65 * struct mtk_disp_rdma - DISP_RDMA driver structure 66 * @ddp_comp - structure containing type enum and hardware resources 67 * @crtc - associated crtc to report irq events to 68 */ 69 struct mtk_disp_rdma { 70 struct mtk_ddp_comp ddp_comp; 71 struct drm_crtc *crtc; 72 const struct mtk_disp_rdma_data *data; 73 }; 74 75 static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) 76 { 77 return container_of(comp, struct mtk_disp_rdma, ddp_comp); 78 } 79 80 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) 81 { 82 struct mtk_disp_rdma *priv = dev_id; 83 struct mtk_ddp_comp *rdma = &priv->ddp_comp; 84 85 /* Clear frame completion interrupt */ 86 writel(0x0, rdma->regs + DISP_REG_RDMA_INT_STATUS); 87 88 if (!priv->crtc) 89 return IRQ_NONE; 90 91 mtk_crtc_ddp_irq(priv->crtc, rdma); 92 93 return IRQ_HANDLED; 94 } 95 96 static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg, 97 unsigned int mask, unsigned int val) 98 { 99 unsigned int tmp = readl(comp->regs + reg); 100 101 tmp = (tmp & ~mask) | (val & mask); 102 writel(tmp, comp->regs + reg); 103 } 104 105 static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp, 106 struct drm_crtc *crtc) 107 { 108 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 109 110 rdma->crtc = crtc; 111 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 112 RDMA_FRAME_END_INT); 113 } 114 115 static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp) 116 { 117 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 118 119 rdma->crtc = NULL; 120 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); 121 } 122 123 static void mtk_rdma_start(struct mtk_ddp_comp *comp) 124 { 125 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 126 RDMA_ENGINE_EN); 127 } 128 129 static void mtk_rdma_stop(struct mtk_ddp_comp *comp) 130 { 131 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); 132 } 133 134 static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, 135 unsigned int height, unsigned int vrefresh, 136 unsigned int bpc) 137 { 138 unsigned int threshold; 139 unsigned int reg; 140 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 141 142 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); 143 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); 144 145 /* 146 * Enable FIFO underflow since DSI and DPI can't be blocked. 147 * Keep the FIFO pseudo size reset default of 8 KiB. Set the 148 * output threshold to 6 microseconds with 7/6 overhead to 149 * account for blanking, and with a pixel depth of 4 bytes: 150 */ 151 threshold = width * height * vrefresh * 4 * 7 / 1000000; 152 reg = RDMA_FIFO_UNDERFLOW_EN | 153 RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | 154 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); 155 writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); 156 } 157 158 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, 159 unsigned int fmt) 160 { 161 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 162 * is defined in mediatek HW data sheet. 163 * The alphabet order in XXX is no relation to data 164 * arrangement in memory. 165 */ 166 switch (fmt) { 167 default: 168 case DRM_FORMAT_RGB565: 169 return MEM_MODE_INPUT_FORMAT_RGB565; 170 case DRM_FORMAT_BGR565: 171 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP; 172 case DRM_FORMAT_RGB888: 173 return MEM_MODE_INPUT_FORMAT_RGB888; 174 case DRM_FORMAT_BGR888: 175 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP; 176 case DRM_FORMAT_RGBX8888: 177 case DRM_FORMAT_RGBA8888: 178 return MEM_MODE_INPUT_FORMAT_ARGB8888; 179 case DRM_FORMAT_BGRX8888: 180 case DRM_FORMAT_BGRA8888: 181 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP; 182 case DRM_FORMAT_XRGB8888: 183 case DRM_FORMAT_ARGB8888: 184 return MEM_MODE_INPUT_FORMAT_RGBA8888; 185 case DRM_FORMAT_XBGR8888: 186 case DRM_FORMAT_ABGR8888: 187 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP; 188 case DRM_FORMAT_UYVY: 189 return MEM_MODE_INPUT_FORMAT_UYVY; 190 case DRM_FORMAT_YUYV: 191 return MEM_MODE_INPUT_FORMAT_YUYV; 192 } 193 } 194 195 static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) 196 { 197 return 1; 198 } 199 200 static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 201 struct mtk_plane_state *state) 202 { 203 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 204 struct mtk_plane_pending_state *pending = &state->pending; 205 unsigned int addr = pending->addr; 206 unsigned int pitch = pending->pitch & 0xffff; 207 unsigned int fmt = pending->format; 208 unsigned int con; 209 210 con = rdma_fmt_convert(rdma, fmt); 211 writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON); 212 213 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { 214 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 215 RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE); 216 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 217 RDMA_MATRIX_INT_MTX_SEL, 218 RDMA_MATRIX_INT_MTX_BT601_to_RGB); 219 } else { 220 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 221 RDMA_MATRIX_ENABLE, 0); 222 } 223 224 writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR); 225 writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH); 226 writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0); 227 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, 228 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY); 229 } 230 231 static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { 232 .config = mtk_rdma_config, 233 .start = mtk_rdma_start, 234 .stop = mtk_rdma_stop, 235 .enable_vblank = mtk_rdma_enable_vblank, 236 .disable_vblank = mtk_rdma_disable_vblank, 237 .layer_nr = mtk_rdma_layer_nr, 238 .layer_config = mtk_rdma_layer_config, 239 }; 240 241 static int mtk_disp_rdma_bind(struct device *dev, struct device *master, 242 void *data) 243 { 244 struct mtk_disp_rdma *priv = dev_get_drvdata(dev); 245 struct drm_device *drm_dev = data; 246 int ret; 247 248 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); 249 if (ret < 0) { 250 dev_err(dev, "Failed to register component %pOF: %d\n", 251 dev->of_node, ret); 252 return ret; 253 } 254 255 return 0; 256 257 } 258 259 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master, 260 void *data) 261 { 262 struct mtk_disp_rdma *priv = dev_get_drvdata(dev); 263 struct drm_device *drm_dev = data; 264 265 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); 266 } 267 268 static const struct component_ops mtk_disp_rdma_component_ops = { 269 .bind = mtk_disp_rdma_bind, 270 .unbind = mtk_disp_rdma_unbind, 271 }; 272 273 static int mtk_disp_rdma_probe(struct platform_device *pdev) 274 { 275 struct device *dev = &pdev->dev; 276 struct mtk_disp_rdma *priv; 277 int comp_id; 278 int irq; 279 int ret; 280 281 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 282 if (!priv) 283 return -ENOMEM; 284 285 irq = platform_get_irq(pdev, 0); 286 if (irq < 0) 287 return irq; 288 289 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); 290 if (comp_id < 0) { 291 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 292 return comp_id; 293 } 294 295 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, 296 &mtk_disp_rdma_funcs); 297 if (ret) { 298 dev_err(dev, "Failed to initialize component: %d\n", ret); 299 return ret; 300 } 301 302 /* Disable and clear pending interrupts */ 303 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_ENABLE); 304 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_STATUS); 305 306 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler, 307 IRQF_TRIGGER_NONE, dev_name(dev), priv); 308 if (ret < 0) { 309 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 310 return ret; 311 } 312 313 priv->data = of_device_get_match_data(dev); 314 315 platform_set_drvdata(pdev, priv); 316 317 ret = component_add(dev, &mtk_disp_rdma_component_ops); 318 if (ret) 319 dev_err(dev, "Failed to add component: %d\n", ret); 320 321 return ret; 322 } 323 324 static int mtk_disp_rdma_remove(struct platform_device *pdev) 325 { 326 component_del(&pdev->dev, &mtk_disp_rdma_component_ops); 327 328 return 0; 329 } 330 331 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { 332 .fifo_size = SZ_4K, 333 }; 334 335 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { 336 .fifo_size = SZ_8K, 337 }; 338 339 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { 340 { .compatible = "mediatek,mt2701-disp-rdma", 341 .data = &mt2701_rdma_driver_data}, 342 { .compatible = "mediatek,mt8173-disp-rdma", 343 .data = &mt8173_rdma_driver_data}, 344 {}, 345 }; 346 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); 347 348 struct platform_driver mtk_disp_rdma_driver = { 349 .probe = mtk_disp_rdma_probe, 350 .remove = mtk_disp_rdma_remove, 351 .driver = { 352 .name = "mediatek-disp-rdma", 353 .owner = THIS_MODULE, 354 .of_match_table = mtk_disp_rdma_driver_dt_match, 355 }, 356 }; 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