1 /* 2 * Copyright (c) 2015 MediaTek Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <drm/drmP.h> 15 #include <linux/clk.h> 16 #include <linux/component.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 21 #include "mtk_drm_crtc.h" 22 #include "mtk_drm_ddp_comp.h" 23 24 #define DISP_REG_OVL_INTEN 0x0004 25 #define OVL_FME_CPL_INT BIT(1) 26 #define DISP_REG_OVL_INTSTA 0x0008 27 #define DISP_REG_OVL_EN 0x000c 28 #define DISP_REG_OVL_RST 0x0014 29 #define DISP_REG_OVL_ROI_SIZE 0x0020 30 #define DISP_REG_OVL_ROI_BGCLR 0x0028 31 #define DISP_REG_OVL_SRC_CON 0x002c 32 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) 33 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) 34 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) 35 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) 36 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) 37 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) 38 #define DISP_REG_OVL_ADDR(n) (0x0f40 + 0x20 * (n)) 39 40 #define OVL_RDMA_MEM_GMC 0x40402020 41 42 #define OVL_CON_BYTE_SWAP BIT(24) 43 #define OVL_CON_CLRFMT_RGB565 (0 << 12) 44 #define OVL_CON_CLRFMT_RGB888 (1 << 12) 45 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) 46 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) 47 #define OVL_CON_AEN BIT(8) 48 #define OVL_CON_ALPHA 0xff 49 50 /** 51 * struct mtk_disp_ovl - DISP_OVL driver structure 52 * @ddp_comp - structure containing type enum and hardware resources 53 * @crtc - associated crtc to report vblank events to 54 */ 55 struct mtk_disp_ovl { 56 struct mtk_ddp_comp ddp_comp; 57 struct drm_crtc *crtc; 58 }; 59 60 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) 61 { 62 struct mtk_disp_ovl *priv = dev_id; 63 struct mtk_ddp_comp *ovl = &priv->ddp_comp; 64 65 /* Clear frame completion interrupt */ 66 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); 67 68 if (!priv->crtc) 69 return IRQ_NONE; 70 71 mtk_crtc_ddp_irq(priv->crtc, ovl); 72 73 return IRQ_HANDLED; 74 } 75 76 static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, 77 struct drm_crtc *crtc) 78 { 79 struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl, 80 ddp_comp); 81 82 priv->crtc = crtc; 83 writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN); 84 } 85 86 static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) 87 { 88 struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl, 89 ddp_comp); 90 91 priv->crtc = NULL; 92 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN); 93 } 94 95 static void mtk_ovl_start(struct mtk_ddp_comp *comp) 96 { 97 writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); 98 } 99 100 static void mtk_ovl_stop(struct mtk_ddp_comp *comp) 101 { 102 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); 103 } 104 105 static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, 106 unsigned int h, unsigned int vrefresh, 107 unsigned int bpc) 108 { 109 if (w != 0 && h != 0) 110 writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE); 111 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR); 112 113 writel(0x1, comp->regs + DISP_REG_OVL_RST); 114 writel(0x0, comp->regs + DISP_REG_OVL_RST); 115 } 116 117 static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) 118 { 119 unsigned int reg; 120 121 writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 122 writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); 123 124 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 125 reg = reg | BIT(idx); 126 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 127 } 128 129 static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) 130 { 131 unsigned int reg; 132 133 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 134 reg = reg & ~BIT(idx); 135 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 136 137 writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 138 } 139 140 static unsigned int ovl_fmt_convert(unsigned int fmt) 141 { 142 switch (fmt) { 143 default: 144 case DRM_FORMAT_RGB565: 145 return OVL_CON_CLRFMT_RGB565; 146 case DRM_FORMAT_BGR565: 147 return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP; 148 case DRM_FORMAT_RGB888: 149 return OVL_CON_CLRFMT_RGB888; 150 case DRM_FORMAT_BGR888: 151 return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP; 152 case DRM_FORMAT_RGBX8888: 153 case DRM_FORMAT_RGBA8888: 154 return OVL_CON_CLRFMT_ARGB8888; 155 case DRM_FORMAT_BGRX8888: 156 case DRM_FORMAT_BGRA8888: 157 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; 158 case DRM_FORMAT_XRGB8888: 159 case DRM_FORMAT_ARGB8888: 160 return OVL_CON_CLRFMT_RGBA8888; 161 case DRM_FORMAT_XBGR8888: 162 case DRM_FORMAT_ABGR8888: 163 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; 164 } 165 } 166 167 static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 168 struct mtk_plane_state *state) 169 { 170 struct mtk_plane_pending_state *pending = &state->pending; 171 unsigned int addr = pending->addr; 172 unsigned int pitch = pending->pitch & 0xffff; 173 unsigned int fmt = pending->format; 174 unsigned int offset = (pending->y << 16) | pending->x; 175 unsigned int src_size = (pending->height << 16) | pending->width; 176 unsigned int con; 177 178 if (!pending->enable) 179 mtk_ovl_layer_off(comp, idx); 180 181 con = ovl_fmt_convert(fmt); 182 if (idx != 0) 183 con |= OVL_CON_AEN | OVL_CON_ALPHA; 184 185 writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); 186 writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); 187 writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); 188 writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx)); 189 writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx)); 190 191 if (pending->enable) 192 mtk_ovl_layer_on(comp, idx); 193 } 194 195 static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { 196 .config = mtk_ovl_config, 197 .start = mtk_ovl_start, 198 .stop = mtk_ovl_stop, 199 .enable_vblank = mtk_ovl_enable_vblank, 200 .disable_vblank = mtk_ovl_disable_vblank, 201 .layer_on = mtk_ovl_layer_on, 202 .layer_off = mtk_ovl_layer_off, 203 .layer_config = mtk_ovl_layer_config, 204 }; 205 206 static int mtk_disp_ovl_bind(struct device *dev, struct device *master, 207 void *data) 208 { 209 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 210 struct drm_device *drm_dev = data; 211 int ret; 212 213 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); 214 if (ret < 0) { 215 dev_err(dev, "Failed to register component %s: %d\n", 216 dev->of_node->full_name, ret); 217 return ret; 218 } 219 220 return 0; 221 } 222 223 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, 224 void *data) 225 { 226 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 227 struct drm_device *drm_dev = data; 228 229 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); 230 } 231 232 static const struct component_ops mtk_disp_ovl_component_ops = { 233 .bind = mtk_disp_ovl_bind, 234 .unbind = mtk_disp_ovl_unbind, 235 }; 236 237 static int mtk_disp_ovl_probe(struct platform_device *pdev) 238 { 239 struct device *dev = &pdev->dev; 240 struct mtk_disp_ovl *priv; 241 int comp_id; 242 int irq; 243 int ret; 244 245 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 246 if (!priv) 247 return -ENOMEM; 248 249 irq = platform_get_irq(pdev, 0); 250 if (irq < 0) 251 return irq; 252 253 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, 254 IRQF_TRIGGER_NONE, dev_name(dev), priv); 255 if (ret < 0) { 256 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 257 return ret; 258 } 259 260 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL); 261 if (comp_id < 0) { 262 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 263 return comp_id; 264 } 265 266 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, 267 &mtk_disp_ovl_funcs); 268 if (ret) { 269 dev_err(dev, "Failed to initialize component: %d\n", ret); 270 return ret; 271 } 272 273 platform_set_drvdata(pdev, priv); 274 275 ret = component_add(dev, &mtk_disp_ovl_component_ops); 276 if (ret) 277 dev_err(dev, "Failed to add component: %d\n", ret); 278 279 return ret; 280 } 281 282 static int mtk_disp_ovl_remove(struct platform_device *pdev) 283 { 284 component_del(&pdev->dev, &mtk_disp_ovl_component_ops); 285 286 return 0; 287 } 288 289 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 290 { .compatible = "mediatek,mt8173-disp-ovl", }, 291 {}, 292 }; 293 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); 294 295 struct platform_driver mtk_disp_ovl_driver = { 296 .probe = mtk_disp_ovl_probe, 297 .remove = mtk_disp_ovl_remove, 298 .driver = { 299 .name = "mediatek-disp-ovl", 300 .owner = THIS_MODULE, 301 .of_match_table = mtk_disp_ovl_driver_dt_match, 302 }, 303 }; 304