1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <drm/drm_fourcc.h> 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/of_irq.h> 13 #include <linux/platform_device.h> 14 15 #include "mtk_drm_crtc.h" 16 #include "mtk_drm_ddp_comp.h" 17 18 #define DISP_REG_OVL_INTEN 0x0004 19 #define OVL_FME_CPL_INT BIT(1) 20 #define DISP_REG_OVL_INTSTA 0x0008 21 #define DISP_REG_OVL_EN 0x000c 22 #define DISP_REG_OVL_RST 0x0014 23 #define DISP_REG_OVL_ROI_SIZE 0x0020 24 #define DISP_REG_OVL_DATAPATH_CON 0x0024 25 #define OVL_BGCLR_SEL_IN BIT(2) 26 #define DISP_REG_OVL_ROI_BGCLR 0x0028 27 #define DISP_REG_OVL_SRC_CON 0x002c 28 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) 29 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) 30 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) 31 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) 32 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) 33 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) 34 #define DISP_REG_OVL_ADDR_MT2701 0x0040 35 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 36 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) 37 38 #define GMC_THRESHOLD_BITS 16 39 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) 40 #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) 41 42 #define OVL_CON_BYTE_SWAP BIT(24) 43 #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) 44 #define OVL_CON_CLRFMT_RGB (1 << 12) 45 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) 46 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) 47 #define OVL_CON_CLRFMT_UYVY (4 << 12) 48 #define OVL_CON_CLRFMT_YUYV (5 << 12) 49 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 50 0 : OVL_CON_CLRFMT_RGB) 51 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 52 OVL_CON_CLRFMT_RGB : 0) 53 #define OVL_CON_AEN BIT(8) 54 #define OVL_CON_ALPHA 0xff 55 #define OVL_CON_VIRT_FLIP BIT(9) 56 #define OVL_CON_HORZ_FLIP BIT(10) 57 58 struct mtk_disp_ovl_data { 59 unsigned int addr; 60 unsigned int gmc_bits; 61 unsigned int layer_nr; 62 bool fmt_rgb565_is_0; 63 }; 64 65 /** 66 * struct mtk_disp_ovl - DISP_OVL driver structure 67 * @ddp_comp - structure containing type enum and hardware resources 68 * @crtc - associated crtc to report vblank events to 69 */ 70 struct mtk_disp_ovl { 71 struct mtk_ddp_comp ddp_comp; 72 struct drm_crtc *crtc; 73 const struct mtk_disp_ovl_data *data; 74 }; 75 76 static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp) 77 { 78 return container_of(comp, struct mtk_disp_ovl, ddp_comp); 79 } 80 81 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) 82 { 83 struct mtk_disp_ovl *priv = dev_id; 84 struct mtk_ddp_comp *ovl = &priv->ddp_comp; 85 86 /* Clear frame completion interrupt */ 87 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); 88 89 if (!priv->crtc) 90 return IRQ_NONE; 91 92 mtk_crtc_ddp_irq(priv->crtc, ovl); 93 94 return IRQ_HANDLED; 95 } 96 97 static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, 98 struct drm_crtc *crtc) 99 { 100 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 101 102 ovl->crtc = crtc; 103 writel(0x0, comp->regs + DISP_REG_OVL_INTSTA); 104 writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN); 105 } 106 107 static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) 108 { 109 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 110 111 ovl->crtc = NULL; 112 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN); 113 } 114 115 static void mtk_ovl_start(struct mtk_ddp_comp *comp) 116 { 117 writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); 118 } 119 120 static void mtk_ovl_stop(struct mtk_ddp_comp *comp) 121 { 122 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); 123 } 124 125 static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, 126 unsigned int h, unsigned int vrefresh, 127 unsigned int bpc) 128 { 129 if (w != 0 && h != 0) 130 writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE); 131 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR); 132 133 writel(0x1, comp->regs + DISP_REG_OVL_RST); 134 writel(0x0, comp->regs + DISP_REG_OVL_RST); 135 } 136 137 static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) 138 { 139 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 140 141 return ovl->data->layer_nr; 142 } 143 144 static unsigned int mtk_ovl_supported_rotations(struct mtk_ddp_comp *comp) 145 { 146 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 147 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 148 } 149 150 static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx, 151 struct mtk_plane_state *mtk_state) 152 { 153 struct drm_plane_state *state = &mtk_state->base; 154 unsigned int rotation = 0; 155 156 rotation = drm_rotation_simplify(state->rotation, 157 DRM_MODE_ROTATE_0 | 158 DRM_MODE_REFLECT_X | 159 DRM_MODE_REFLECT_Y); 160 rotation &= ~DRM_MODE_ROTATE_0; 161 162 /* We can only do reflection, not rotation */ 163 if ((rotation & DRM_MODE_ROTATE_MASK) != 0) 164 return -EINVAL; 165 166 /* 167 * TODO: Rotating/reflecting YUV buffers is not supported at this time. 168 * Only RGB[AX] variants are supported. 169 */ 170 if (state->fb->format->is_yuv && rotation != 0) 171 return -EINVAL; 172 173 state->rotation = rotation; 174 175 return 0; 176 } 177 178 static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) 179 { 180 unsigned int reg; 181 unsigned int gmc_thrshd_l; 182 unsigned int gmc_thrshd_h; 183 unsigned int gmc_value; 184 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 185 186 writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 187 188 gmc_thrshd_l = GMC_THRESHOLD_LOW >> 189 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 190 gmc_thrshd_h = GMC_THRESHOLD_HIGH >> 191 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 192 if (ovl->data->gmc_bits == 10) 193 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16; 194 else 195 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | 196 gmc_thrshd_h << 16 | gmc_thrshd_h << 24; 197 writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); 198 199 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 200 reg = reg | BIT(idx); 201 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 202 } 203 204 static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) 205 { 206 unsigned int reg; 207 208 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 209 reg = reg & ~BIT(idx); 210 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 211 212 writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 213 } 214 215 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 216 { 217 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 218 * is defined in mediatek HW data sheet. 219 * The alphabet order in XXX is no relation to data 220 * arrangement in memory. 221 */ 222 switch (fmt) { 223 default: 224 case DRM_FORMAT_RGB565: 225 return OVL_CON_CLRFMT_RGB565(ovl); 226 case DRM_FORMAT_BGR565: 227 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; 228 case DRM_FORMAT_RGB888: 229 return OVL_CON_CLRFMT_RGB888(ovl); 230 case DRM_FORMAT_BGR888: 231 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; 232 case DRM_FORMAT_RGBX8888: 233 case DRM_FORMAT_RGBA8888: 234 return OVL_CON_CLRFMT_ARGB8888; 235 case DRM_FORMAT_BGRX8888: 236 case DRM_FORMAT_BGRA8888: 237 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; 238 case DRM_FORMAT_XRGB8888: 239 case DRM_FORMAT_ARGB8888: 240 return OVL_CON_CLRFMT_RGBA8888; 241 case DRM_FORMAT_XBGR8888: 242 case DRM_FORMAT_ABGR8888: 243 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; 244 case DRM_FORMAT_UYVY: 245 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; 246 case DRM_FORMAT_YUYV: 247 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; 248 } 249 } 250 251 static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 252 struct mtk_plane_state *state) 253 { 254 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 255 struct mtk_plane_pending_state *pending = &state->pending; 256 unsigned int addr = pending->addr; 257 unsigned int pitch = pending->pitch & 0xffff; 258 unsigned int fmt = pending->format; 259 unsigned int offset = (pending->y << 16) | pending->x; 260 unsigned int src_size = (pending->height << 16) | pending->width; 261 unsigned int con; 262 263 if (!pending->enable) 264 mtk_ovl_layer_off(comp, idx); 265 266 con = ovl_fmt_convert(ovl, fmt); 267 if (idx != 0) 268 con |= OVL_CON_AEN | OVL_CON_ALPHA; 269 270 if (pending->rotation & DRM_MODE_REFLECT_Y) { 271 con |= OVL_CON_VIRT_FLIP; 272 addr += (pending->height - 1) * pending->pitch; 273 } 274 275 if (pending->rotation & DRM_MODE_REFLECT_X) { 276 con |= OVL_CON_HORZ_FLIP; 277 addr += pending->pitch - 1; 278 } 279 280 writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); 281 writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); 282 writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); 283 writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx)); 284 writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx)); 285 286 if (pending->enable) 287 mtk_ovl_layer_on(comp, idx); 288 } 289 290 static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) 291 { 292 unsigned int reg; 293 294 reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON); 295 reg = reg | OVL_BGCLR_SEL_IN; 296 writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON); 297 } 298 299 static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp) 300 { 301 unsigned int reg; 302 303 reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON); 304 reg = reg & ~OVL_BGCLR_SEL_IN; 305 writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON); 306 } 307 308 static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { 309 .config = mtk_ovl_config, 310 .start = mtk_ovl_start, 311 .stop = mtk_ovl_stop, 312 .enable_vblank = mtk_ovl_enable_vblank, 313 .disable_vblank = mtk_ovl_disable_vblank, 314 .supported_rotations = mtk_ovl_supported_rotations, 315 .layer_nr = mtk_ovl_layer_nr, 316 .layer_on = mtk_ovl_layer_on, 317 .layer_off = mtk_ovl_layer_off, 318 .layer_check = mtk_ovl_layer_check, 319 .layer_config = mtk_ovl_layer_config, 320 .bgclr_in_on = mtk_ovl_bgclr_in_on, 321 .bgclr_in_off = mtk_ovl_bgclr_in_off, 322 }; 323 324 static int mtk_disp_ovl_bind(struct device *dev, struct device *master, 325 void *data) 326 { 327 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 328 struct drm_device *drm_dev = data; 329 int ret; 330 331 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); 332 if (ret < 0) { 333 dev_err(dev, "Failed to register component %pOF: %d\n", 334 dev->of_node, ret); 335 return ret; 336 } 337 338 return 0; 339 } 340 341 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, 342 void *data) 343 { 344 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 345 struct drm_device *drm_dev = data; 346 347 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); 348 } 349 350 static const struct component_ops mtk_disp_ovl_component_ops = { 351 .bind = mtk_disp_ovl_bind, 352 .unbind = mtk_disp_ovl_unbind, 353 }; 354 355 static int mtk_disp_ovl_probe(struct platform_device *pdev) 356 { 357 struct device *dev = &pdev->dev; 358 struct mtk_disp_ovl *priv; 359 int comp_id; 360 int irq; 361 int ret; 362 363 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 364 if (!priv) 365 return -ENOMEM; 366 367 irq = platform_get_irq(pdev, 0); 368 if (irq < 0) 369 return irq; 370 371 priv->data = of_device_get_match_data(dev); 372 373 comp_id = mtk_ddp_comp_get_id(dev->of_node, 374 priv->data->layer_nr == 4 ? 375 MTK_DISP_OVL : 376 MTK_DISP_OVL_2L); 377 if (comp_id < 0) { 378 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 379 return comp_id; 380 } 381 382 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, 383 &mtk_disp_ovl_funcs); 384 if (ret) { 385 dev_err(dev, "Failed to initialize component: %d\n", ret); 386 return ret; 387 } 388 389 platform_set_drvdata(pdev, priv); 390 391 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, 392 IRQF_TRIGGER_NONE, dev_name(dev), priv); 393 if (ret < 0) { 394 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 395 return ret; 396 } 397 398 ret = component_add(dev, &mtk_disp_ovl_component_ops); 399 if (ret) 400 dev_err(dev, "Failed to add component: %d\n", ret); 401 402 return ret; 403 } 404 405 static int mtk_disp_ovl_remove(struct platform_device *pdev) 406 { 407 component_del(&pdev->dev, &mtk_disp_ovl_component_ops); 408 409 return 0; 410 } 411 412 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { 413 .addr = DISP_REG_OVL_ADDR_MT2701, 414 .gmc_bits = 8, 415 .layer_nr = 4, 416 .fmt_rgb565_is_0 = false, 417 }; 418 419 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { 420 .addr = DISP_REG_OVL_ADDR_MT8173, 421 .gmc_bits = 8, 422 .layer_nr = 4, 423 .fmt_rgb565_is_0 = true, 424 }; 425 426 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 427 { .compatible = "mediatek,mt2701-disp-ovl", 428 .data = &mt2701_ovl_driver_data}, 429 { .compatible = "mediatek,mt8173-disp-ovl", 430 .data = &mt8173_ovl_driver_data}, 431 {}, 432 }; 433 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); 434 435 struct platform_driver mtk_disp_ovl_driver = { 436 .probe = mtk_disp_ovl_probe, 437 .remove = mtk_disp_ovl_remove, 438 .driver = { 439 .name = "mediatek-disp-ovl", 440 .owner = THIS_MODULE, 441 .of_match_table = mtk_disp_ovl_driver_dt_match, 442 }, 443 }; 444