1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <drm/drm_fourcc.h> 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/of_irq.h> 13 #include <linux/platform_device.h> 14 #include <linux/soc/mediatek/mtk-cmdq.h> 15 16 #include "mtk_disp_drv.h" 17 #include "mtk_drm_crtc.h" 18 #include "mtk_drm_ddp_comp.h" 19 20 #define DISP_REG_OVL_INTEN 0x0004 21 #define OVL_FME_CPL_INT BIT(1) 22 #define DISP_REG_OVL_INTSTA 0x0008 23 #define DISP_REG_OVL_EN 0x000c 24 #define DISP_REG_OVL_RST 0x0014 25 #define DISP_REG_OVL_ROI_SIZE 0x0020 26 #define DISP_REG_OVL_DATAPATH_CON 0x0024 27 #define OVL_LAYER_SMI_ID_EN BIT(0) 28 #define OVL_BGCLR_SEL_IN BIT(2) 29 #define DISP_REG_OVL_ROI_BGCLR 0x0028 30 #define DISP_REG_OVL_SRC_CON 0x002c 31 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) 32 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) 33 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) 34 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) 35 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) 36 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) 37 #define DISP_REG_OVL_ADDR_MT2701 0x0040 38 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 39 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) 40 41 #define GMC_THRESHOLD_BITS 16 42 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) 43 #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) 44 45 #define OVL_CON_BYTE_SWAP BIT(24) 46 #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) 47 #define OVL_CON_CLRFMT_RGB (1 << 12) 48 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) 49 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) 50 #define OVL_CON_CLRFMT_UYVY (4 << 12) 51 #define OVL_CON_CLRFMT_YUYV (5 << 12) 52 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 53 0 : OVL_CON_CLRFMT_RGB) 54 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 55 OVL_CON_CLRFMT_RGB : 0) 56 #define OVL_CON_AEN BIT(8) 57 #define OVL_CON_ALPHA 0xff 58 #define OVL_CON_VIRT_FLIP BIT(9) 59 #define OVL_CON_HORZ_FLIP BIT(10) 60 61 struct mtk_disp_ovl_data { 62 unsigned int addr; 63 unsigned int gmc_bits; 64 unsigned int layer_nr; 65 bool fmt_rgb565_is_0; 66 bool smi_id_en; 67 }; 68 69 /** 70 * struct mtk_disp_ovl - DISP_OVL driver structure 71 * @ddp_comp: structure containing type enum and hardware resources 72 * @crtc: associated crtc to report vblank events to 73 * @data: platform data 74 */ 75 struct mtk_disp_ovl { 76 struct drm_crtc *crtc; 77 struct clk *clk; 78 void __iomem *regs; 79 struct cmdq_client_reg cmdq_reg; 80 const struct mtk_disp_ovl_data *data; 81 void (*vblank_cb)(void *data); 82 void *vblank_cb_data; 83 }; 84 85 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) 86 { 87 struct mtk_disp_ovl *priv = dev_id; 88 89 /* Clear frame completion interrupt */ 90 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); 91 92 if (!priv->vblank_cb) 93 return IRQ_NONE; 94 95 priv->vblank_cb(priv->vblank_cb_data); 96 97 return IRQ_HANDLED; 98 } 99 100 void mtk_ovl_enable_vblank(struct device *dev, 101 void (*vblank_cb)(void *), 102 void *vblank_cb_data) 103 { 104 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 105 106 ovl->vblank_cb = vblank_cb; 107 ovl->vblank_cb_data = vblank_cb_data; 108 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); 109 writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); 110 } 111 112 void mtk_ovl_disable_vblank(struct device *dev) 113 { 114 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 115 116 ovl->vblank_cb = NULL; 117 ovl->vblank_cb_data = NULL; 118 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); 119 } 120 121 int mtk_ovl_clk_enable(struct device *dev) 122 { 123 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 124 125 return clk_prepare_enable(ovl->clk); 126 } 127 128 void mtk_ovl_clk_disable(struct device *dev) 129 { 130 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 131 132 clk_disable_unprepare(ovl->clk); 133 } 134 135 void mtk_ovl_start(struct device *dev) 136 { 137 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 138 139 if (ovl->data->smi_id_en) { 140 unsigned int reg; 141 142 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 143 reg = reg | OVL_LAYER_SMI_ID_EN; 144 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 145 } 146 writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); 147 } 148 149 void mtk_ovl_stop(struct device *dev) 150 { 151 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 152 153 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); 154 if (ovl->data->smi_id_en) { 155 unsigned int reg; 156 157 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 158 reg = reg & ~OVL_LAYER_SMI_ID_EN; 159 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 160 } 161 162 } 163 164 void mtk_ovl_config(struct device *dev, unsigned int w, 165 unsigned int h, unsigned int vrefresh, 166 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 167 { 168 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 169 170 if (w != 0 && h != 0) 171 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, 172 DISP_REG_OVL_ROI_SIZE); 173 mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR); 174 175 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); 176 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); 177 } 178 179 unsigned int mtk_ovl_layer_nr(struct device *dev) 180 { 181 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 182 183 return ovl->data->layer_nr; 184 } 185 186 unsigned int mtk_ovl_supported_rotations(struct device *dev) 187 { 188 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 189 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 190 } 191 192 int mtk_ovl_layer_check(struct device *dev, unsigned int idx, 193 struct mtk_plane_state *mtk_state) 194 { 195 struct drm_plane_state *state = &mtk_state->base; 196 unsigned int rotation = 0; 197 198 rotation = drm_rotation_simplify(state->rotation, 199 DRM_MODE_ROTATE_0 | 200 DRM_MODE_REFLECT_X | 201 DRM_MODE_REFLECT_Y); 202 rotation &= ~DRM_MODE_ROTATE_0; 203 204 /* We can only do reflection, not rotation */ 205 if ((rotation & DRM_MODE_ROTATE_MASK) != 0) 206 return -EINVAL; 207 208 /* 209 * TODO: Rotating/reflecting YUV buffers is not supported at this time. 210 * Only RGB[AX] variants are supported. 211 */ 212 if (state->fb->format->is_yuv && rotation != 0) 213 return -EINVAL; 214 215 state->rotation = rotation; 216 217 return 0; 218 } 219 220 void mtk_ovl_layer_on(struct device *dev, unsigned int idx, 221 struct cmdq_pkt *cmdq_pkt) 222 { 223 unsigned int gmc_thrshd_l; 224 unsigned int gmc_thrshd_h; 225 unsigned int gmc_value; 226 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 227 228 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, 229 DISP_REG_OVL_RDMA_CTRL(idx)); 230 gmc_thrshd_l = GMC_THRESHOLD_LOW >> 231 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 232 gmc_thrshd_h = GMC_THRESHOLD_HIGH >> 233 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 234 if (ovl->data->gmc_bits == 10) 235 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16; 236 else 237 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | 238 gmc_thrshd_h << 16 | gmc_thrshd_h << 24; 239 mtk_ddp_write(cmdq_pkt, gmc_value, 240 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); 241 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, 242 DISP_REG_OVL_SRC_CON, BIT(idx)); 243 } 244 245 void mtk_ovl_layer_off(struct device *dev, unsigned int idx, 246 struct cmdq_pkt *cmdq_pkt) 247 { 248 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 249 250 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, 251 DISP_REG_OVL_SRC_CON, BIT(idx)); 252 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, 253 DISP_REG_OVL_RDMA_CTRL(idx)); 254 } 255 256 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 257 { 258 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 259 * is defined in mediatek HW data sheet. 260 * The alphabet order in XXX is no relation to data 261 * arrangement in memory. 262 */ 263 switch (fmt) { 264 default: 265 case DRM_FORMAT_RGB565: 266 return OVL_CON_CLRFMT_RGB565(ovl); 267 case DRM_FORMAT_BGR565: 268 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; 269 case DRM_FORMAT_RGB888: 270 return OVL_CON_CLRFMT_RGB888(ovl); 271 case DRM_FORMAT_BGR888: 272 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; 273 case DRM_FORMAT_RGBX8888: 274 case DRM_FORMAT_RGBA8888: 275 return OVL_CON_CLRFMT_ARGB8888; 276 case DRM_FORMAT_BGRX8888: 277 case DRM_FORMAT_BGRA8888: 278 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; 279 case DRM_FORMAT_XRGB8888: 280 case DRM_FORMAT_ARGB8888: 281 return OVL_CON_CLRFMT_RGBA8888; 282 case DRM_FORMAT_XBGR8888: 283 case DRM_FORMAT_ABGR8888: 284 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; 285 case DRM_FORMAT_UYVY: 286 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; 287 case DRM_FORMAT_YUYV: 288 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; 289 } 290 } 291 292 void mtk_ovl_layer_config(struct device *dev, unsigned int idx, 293 struct mtk_plane_state *state, 294 struct cmdq_pkt *cmdq_pkt) 295 { 296 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 297 struct mtk_plane_pending_state *pending = &state->pending; 298 unsigned int addr = pending->addr; 299 unsigned int pitch = pending->pitch & 0xffff; 300 unsigned int fmt = pending->format; 301 unsigned int offset = (pending->y << 16) | pending->x; 302 unsigned int src_size = (pending->height << 16) | pending->width; 303 unsigned int con; 304 305 if (!pending->enable) { 306 mtk_ovl_layer_off(dev, idx, cmdq_pkt); 307 return; 308 } 309 310 con = ovl_fmt_convert(ovl, fmt); 311 if (state->base.fb && state->base.fb->format->has_alpha) 312 con |= OVL_CON_AEN | OVL_CON_ALPHA; 313 314 if (pending->rotation & DRM_MODE_REFLECT_Y) { 315 con |= OVL_CON_VIRT_FLIP; 316 addr += (pending->height - 1) * pending->pitch; 317 } 318 319 if (pending->rotation & DRM_MODE_REFLECT_X) { 320 con |= OVL_CON_HORZ_FLIP; 321 addr += pending->pitch - 1; 322 } 323 324 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, 325 DISP_REG_OVL_CON(idx)); 326 mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs, 327 DISP_REG_OVL_PITCH(idx)); 328 mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, 329 DISP_REG_OVL_SRC_SIZE(idx)); 330 mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, 331 DISP_REG_OVL_OFFSET(idx)); 332 mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, 333 DISP_REG_OVL_ADDR(ovl, idx)); 334 335 mtk_ovl_layer_on(dev, idx, cmdq_pkt); 336 } 337 338 void mtk_ovl_bgclr_in_on(struct device *dev) 339 { 340 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 341 unsigned int reg; 342 343 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 344 reg = reg | OVL_BGCLR_SEL_IN; 345 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 346 } 347 348 void mtk_ovl_bgclr_in_off(struct device *dev) 349 { 350 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 351 unsigned int reg; 352 353 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 354 reg = reg & ~OVL_BGCLR_SEL_IN; 355 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 356 } 357 358 static int mtk_disp_ovl_bind(struct device *dev, struct device *master, 359 void *data) 360 { 361 return 0; 362 } 363 364 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, 365 void *data) 366 { 367 } 368 369 static const struct component_ops mtk_disp_ovl_component_ops = { 370 .bind = mtk_disp_ovl_bind, 371 .unbind = mtk_disp_ovl_unbind, 372 }; 373 374 static int mtk_disp_ovl_probe(struct platform_device *pdev) 375 { 376 struct device *dev = &pdev->dev; 377 struct mtk_disp_ovl *priv; 378 struct resource *res; 379 int irq; 380 int ret; 381 382 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 383 if (!priv) 384 return -ENOMEM; 385 386 irq = platform_get_irq(pdev, 0); 387 if (irq < 0) 388 return irq; 389 390 priv->clk = devm_clk_get(dev, NULL); 391 if (IS_ERR(priv->clk)) { 392 dev_err(dev, "failed to get ovl clk\n"); 393 return PTR_ERR(priv->clk); 394 } 395 396 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 397 priv->regs = devm_ioremap_resource(dev, res); 398 if (IS_ERR(priv->regs)) { 399 dev_err(dev, "failed to ioremap ovl\n"); 400 return PTR_ERR(priv->regs); 401 } 402 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 403 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); 404 if (ret) 405 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); 406 #endif 407 408 priv->data = of_device_get_match_data(dev); 409 platform_set_drvdata(pdev, priv); 410 411 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, 412 IRQF_TRIGGER_NONE, dev_name(dev), priv); 413 if (ret < 0) { 414 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 415 return ret; 416 } 417 418 ret = component_add(dev, &mtk_disp_ovl_component_ops); 419 if (ret) 420 dev_err(dev, "Failed to add component: %d\n", ret); 421 422 return ret; 423 } 424 425 static int mtk_disp_ovl_remove(struct platform_device *pdev) 426 { 427 return 0; 428 } 429 430 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { 431 .addr = DISP_REG_OVL_ADDR_MT2701, 432 .gmc_bits = 8, 433 .layer_nr = 4, 434 .fmt_rgb565_is_0 = false, 435 }; 436 437 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { 438 .addr = DISP_REG_OVL_ADDR_MT8173, 439 .gmc_bits = 8, 440 .layer_nr = 4, 441 .fmt_rgb565_is_0 = true, 442 }; 443 444 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { 445 .addr = DISP_REG_OVL_ADDR_MT8173, 446 .gmc_bits = 10, 447 .layer_nr = 4, 448 .fmt_rgb565_is_0 = true, 449 }; 450 451 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { 452 .addr = DISP_REG_OVL_ADDR_MT8173, 453 .gmc_bits = 10, 454 .layer_nr = 2, 455 .fmt_rgb565_is_0 = true, 456 }; 457 458 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 459 { .compatible = "mediatek,mt2701-disp-ovl", 460 .data = &mt2701_ovl_driver_data}, 461 { .compatible = "mediatek,mt8173-disp-ovl", 462 .data = &mt8173_ovl_driver_data}, 463 { .compatible = "mediatek,mt8183-disp-ovl", 464 .data = &mt8183_ovl_driver_data}, 465 { .compatible = "mediatek,mt8183-disp-ovl-2l", 466 .data = &mt8183_ovl_2l_driver_data}, 467 {}, 468 }; 469 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); 470 471 struct platform_driver mtk_disp_ovl_driver = { 472 .probe = mtk_disp_ovl_probe, 473 .remove = mtk_disp_ovl_remove, 474 .driver = { 475 .name = "mediatek-disp-ovl", 476 .owner = THIS_MODULE, 477 .of_match_table = mtk_disp_ovl_driver_dt_match, 478 }, 479 }; 480