1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of_device.h> 10 #include <linux/of_irq.h> 11 #include <linux/platform_device.h> 12 13 #include "mtk_drm_crtc.h" 14 #include "mtk_drm_ddp_comp.h" 15 16 #define DISP_REG_OVL_INTEN 0x0004 17 #define OVL_FME_CPL_INT BIT(1) 18 #define DISP_REG_OVL_INTSTA 0x0008 19 #define DISP_REG_OVL_EN 0x000c 20 #define DISP_REG_OVL_RST 0x0014 21 #define DISP_REG_OVL_ROI_SIZE 0x0020 22 #define DISP_REG_OVL_DATAPATH_CON 0x0024 23 #define OVL_BGCLR_SEL_IN BIT(2) 24 #define DISP_REG_OVL_ROI_BGCLR 0x0028 25 #define DISP_REG_OVL_SRC_CON 0x002c 26 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) 27 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) 28 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) 29 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) 30 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) 31 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) 32 #define DISP_REG_OVL_ADDR_MT2701 0x0040 33 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 34 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) 35 36 #define GMC_THRESHOLD_BITS 16 37 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) 38 #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) 39 40 #define OVL_CON_BYTE_SWAP BIT(24) 41 #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) 42 #define OVL_CON_CLRFMT_RGB (1 << 12) 43 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) 44 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) 45 #define OVL_CON_CLRFMT_UYVY (4 << 12) 46 #define OVL_CON_CLRFMT_YUYV (5 << 12) 47 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 48 0 : OVL_CON_CLRFMT_RGB) 49 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 50 OVL_CON_CLRFMT_RGB : 0) 51 #define OVL_CON_AEN BIT(8) 52 #define OVL_CON_ALPHA 0xff 53 54 struct mtk_disp_ovl_data { 55 unsigned int addr; 56 unsigned int gmc_bits; 57 unsigned int layer_nr; 58 bool fmt_rgb565_is_0; 59 }; 60 61 /** 62 * struct mtk_disp_ovl - DISP_OVL driver structure 63 * @ddp_comp - structure containing type enum and hardware resources 64 * @crtc - associated crtc to report vblank events to 65 */ 66 struct mtk_disp_ovl { 67 struct mtk_ddp_comp ddp_comp; 68 struct drm_crtc *crtc; 69 const struct mtk_disp_ovl_data *data; 70 }; 71 72 static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp) 73 { 74 return container_of(comp, struct mtk_disp_ovl, ddp_comp); 75 } 76 77 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) 78 { 79 struct mtk_disp_ovl *priv = dev_id; 80 struct mtk_ddp_comp *ovl = &priv->ddp_comp; 81 82 /* Clear frame completion interrupt */ 83 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); 84 85 if (!priv->crtc) 86 return IRQ_NONE; 87 88 mtk_crtc_ddp_irq(priv->crtc, ovl); 89 90 return IRQ_HANDLED; 91 } 92 93 static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, 94 struct drm_crtc *crtc) 95 { 96 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 97 98 ovl->crtc = crtc; 99 writel(0x0, comp->regs + DISP_REG_OVL_INTSTA); 100 writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN); 101 } 102 103 static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) 104 { 105 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 106 107 ovl->crtc = NULL; 108 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN); 109 } 110 111 static void mtk_ovl_start(struct mtk_ddp_comp *comp) 112 { 113 writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); 114 } 115 116 static void mtk_ovl_stop(struct mtk_ddp_comp *comp) 117 { 118 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); 119 } 120 121 static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, 122 unsigned int h, unsigned int vrefresh, 123 unsigned int bpc) 124 { 125 if (w != 0 && h != 0) 126 writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE); 127 writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR); 128 129 writel(0x1, comp->regs + DISP_REG_OVL_RST); 130 writel(0x0, comp->regs + DISP_REG_OVL_RST); 131 } 132 133 static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) 134 { 135 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 136 137 return ovl->data->layer_nr; 138 } 139 140 static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) 141 { 142 unsigned int reg; 143 unsigned int gmc_thrshd_l; 144 unsigned int gmc_thrshd_h; 145 unsigned int gmc_value; 146 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 147 148 writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 149 150 gmc_thrshd_l = GMC_THRESHOLD_LOW >> 151 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 152 gmc_thrshd_h = GMC_THRESHOLD_HIGH >> 153 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 154 if (ovl->data->gmc_bits == 10) 155 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16; 156 else 157 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | 158 gmc_thrshd_h << 16 | gmc_thrshd_h << 24; 159 writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); 160 161 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 162 reg = reg | BIT(idx); 163 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 164 } 165 166 static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) 167 { 168 unsigned int reg; 169 170 reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); 171 reg = reg & ~BIT(idx); 172 writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); 173 174 writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); 175 } 176 177 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 178 { 179 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 180 * is defined in mediatek HW data sheet. 181 * The alphabet order in XXX is no relation to data 182 * arrangement in memory. 183 */ 184 switch (fmt) { 185 default: 186 case DRM_FORMAT_RGB565: 187 return OVL_CON_CLRFMT_RGB565(ovl); 188 case DRM_FORMAT_BGR565: 189 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; 190 case DRM_FORMAT_RGB888: 191 return OVL_CON_CLRFMT_RGB888(ovl); 192 case DRM_FORMAT_BGR888: 193 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; 194 case DRM_FORMAT_RGBX8888: 195 case DRM_FORMAT_RGBA8888: 196 return OVL_CON_CLRFMT_ARGB8888; 197 case DRM_FORMAT_BGRX8888: 198 case DRM_FORMAT_BGRA8888: 199 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; 200 case DRM_FORMAT_XRGB8888: 201 case DRM_FORMAT_ARGB8888: 202 return OVL_CON_CLRFMT_RGBA8888; 203 case DRM_FORMAT_XBGR8888: 204 case DRM_FORMAT_ABGR8888: 205 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; 206 case DRM_FORMAT_UYVY: 207 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; 208 case DRM_FORMAT_YUYV: 209 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; 210 } 211 } 212 213 static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 214 struct mtk_plane_state *state) 215 { 216 struct mtk_disp_ovl *ovl = comp_to_ovl(comp); 217 struct mtk_plane_pending_state *pending = &state->pending; 218 unsigned int addr = pending->addr; 219 unsigned int pitch = pending->pitch & 0xffff; 220 unsigned int fmt = pending->format; 221 unsigned int offset = (pending->y << 16) | pending->x; 222 unsigned int src_size = (pending->height << 16) | pending->width; 223 unsigned int con; 224 225 if (!pending->enable) 226 mtk_ovl_layer_off(comp, idx); 227 228 con = ovl_fmt_convert(ovl, fmt); 229 if (idx != 0) 230 con |= OVL_CON_AEN | OVL_CON_ALPHA; 231 232 writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); 233 writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); 234 writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); 235 writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx)); 236 writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx)); 237 238 if (pending->enable) 239 mtk_ovl_layer_on(comp, idx); 240 } 241 242 static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) 243 { 244 unsigned int reg; 245 246 reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON); 247 reg = reg | OVL_BGCLR_SEL_IN; 248 writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON); 249 } 250 251 static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp) 252 { 253 unsigned int reg; 254 255 reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON); 256 reg = reg & ~OVL_BGCLR_SEL_IN; 257 writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON); 258 } 259 260 static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { 261 .config = mtk_ovl_config, 262 .start = mtk_ovl_start, 263 .stop = mtk_ovl_stop, 264 .enable_vblank = mtk_ovl_enable_vblank, 265 .disable_vblank = mtk_ovl_disable_vblank, 266 .layer_nr = mtk_ovl_layer_nr, 267 .layer_on = mtk_ovl_layer_on, 268 .layer_off = mtk_ovl_layer_off, 269 .layer_config = mtk_ovl_layer_config, 270 .bgclr_in_on = mtk_ovl_bgclr_in_on, 271 .bgclr_in_off = mtk_ovl_bgclr_in_off, 272 }; 273 274 static int mtk_disp_ovl_bind(struct device *dev, struct device *master, 275 void *data) 276 { 277 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 278 struct drm_device *drm_dev = data; 279 int ret; 280 281 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); 282 if (ret < 0) { 283 dev_err(dev, "Failed to register component %pOF: %d\n", 284 dev->of_node, ret); 285 return ret; 286 } 287 288 return 0; 289 } 290 291 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, 292 void *data) 293 { 294 struct mtk_disp_ovl *priv = dev_get_drvdata(dev); 295 struct drm_device *drm_dev = data; 296 297 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); 298 } 299 300 static const struct component_ops mtk_disp_ovl_component_ops = { 301 .bind = mtk_disp_ovl_bind, 302 .unbind = mtk_disp_ovl_unbind, 303 }; 304 305 static int mtk_disp_ovl_probe(struct platform_device *pdev) 306 { 307 struct device *dev = &pdev->dev; 308 struct mtk_disp_ovl *priv; 309 int comp_id; 310 int irq; 311 int ret; 312 313 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 314 if (!priv) 315 return -ENOMEM; 316 317 irq = platform_get_irq(pdev, 0); 318 if (irq < 0) 319 return irq; 320 321 priv->data = of_device_get_match_data(dev); 322 323 comp_id = mtk_ddp_comp_get_id(dev->of_node, 324 priv->data->layer_nr == 4 ? 325 MTK_DISP_OVL : 326 MTK_DISP_OVL_2L); 327 if (comp_id < 0) { 328 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 329 return comp_id; 330 } 331 332 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, 333 &mtk_disp_ovl_funcs); 334 if (ret) { 335 dev_err(dev, "Failed to initialize component: %d\n", ret); 336 return ret; 337 } 338 339 platform_set_drvdata(pdev, priv); 340 341 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, 342 IRQF_TRIGGER_NONE, dev_name(dev), priv); 343 if (ret < 0) { 344 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 345 return ret; 346 } 347 348 ret = component_add(dev, &mtk_disp_ovl_component_ops); 349 if (ret) 350 dev_err(dev, "Failed to add component: %d\n", ret); 351 352 return ret; 353 } 354 355 static int mtk_disp_ovl_remove(struct platform_device *pdev) 356 { 357 component_del(&pdev->dev, &mtk_disp_ovl_component_ops); 358 359 return 0; 360 } 361 362 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { 363 .addr = DISP_REG_OVL_ADDR_MT2701, 364 .gmc_bits = 8, 365 .layer_nr = 4, 366 .fmt_rgb565_is_0 = false, 367 }; 368 369 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { 370 .addr = DISP_REG_OVL_ADDR_MT8173, 371 .gmc_bits = 8, 372 .layer_nr = 4, 373 .fmt_rgb565_is_0 = true, 374 }; 375 376 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 377 { .compatible = "mediatek,mt2701-disp-ovl", 378 .data = &mt2701_ovl_driver_data}, 379 { .compatible = "mediatek,mt8173-disp-ovl", 380 .data = &mt8173_ovl_driver_data}, 381 {}, 382 }; 383 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); 384 385 struct platform_driver mtk_disp_ovl_driver = { 386 .probe = mtk_disp_ovl_probe, 387 .remove = mtk_disp_ovl_remove, 388 .driver = { 389 .name = "mediatek-disp-ovl", 390 .owner = THIS_MODULE, 391 .of_match_table = mtk_disp_ovl_driver_dt_match, 392 }, 393 }; 394