1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <drm/drm_blend.h> 7 #include <drm/drm_fourcc.h> 8 #include <drm/drm_framebuffer.h> 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/soc/mediatek/mtk-cmdq.h> 18 19 #include "mtk_disp_drv.h" 20 #include "mtk_drm_crtc.h" 21 #include "mtk_drm_ddp_comp.h" 22 #include "mtk_drm_drv.h" 23 24 #define DISP_REG_OVL_INTEN 0x0004 25 #define OVL_FME_CPL_INT BIT(1) 26 #define DISP_REG_OVL_INTSTA 0x0008 27 #define DISP_REG_OVL_EN 0x000c 28 #define DISP_REG_OVL_RST 0x0014 29 #define DISP_REG_OVL_ROI_SIZE 0x0020 30 #define DISP_REG_OVL_DATAPATH_CON 0x0024 31 #define OVL_LAYER_SMI_ID_EN BIT(0) 32 #define OVL_BGCLR_SEL_IN BIT(2) 33 #define OVL_LAYER_AFBC_EN(n) BIT(4+n) 34 #define DISP_REG_OVL_ROI_BGCLR 0x0028 35 #define DISP_REG_OVL_SRC_CON 0x002c 36 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n)) 37 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n)) 38 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n)) 39 #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) 40 #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) 41 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) 42 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) 43 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) 44 #define DISP_REG_OVL_ADDR_MT2701 0x0040 45 #define DISP_REG_OVL_CLRFMT_EXT 0x02D0 46 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 47 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) 48 #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) 49 #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08) 50 51 #define GMC_THRESHOLD_BITS 16 52 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) 53 #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) 54 55 #define OVL_CON_BYTE_SWAP BIT(24) 56 #define OVL_CON_MTX_YUV_TO_RGB (6 << 16) 57 #define OVL_CON_CLRFMT_RGB (1 << 12) 58 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) 59 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) 60 #define OVL_CON_CLRFMT_UYVY (4 << 12) 61 #define OVL_CON_CLRFMT_YUYV (5 << 12) 62 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 63 0 : OVL_CON_CLRFMT_RGB) 64 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 65 OVL_CON_CLRFMT_RGB : 0) 66 #define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) 67 #define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) 68 #define OVL_CON_CLRFMT_8_BIT 0x00 69 #define OVL_CON_CLRFMT_10_BIT 0x01 70 #define OVL_CON_AEN BIT(8) 71 #define OVL_CON_ALPHA 0xff 72 #define OVL_CON_VIRT_FLIP BIT(9) 73 #define OVL_CON_HORZ_FLIP BIT(10) 74 75 static const u32 mt8173_formats[] = { 76 DRM_FORMAT_XRGB8888, 77 DRM_FORMAT_ARGB8888, 78 DRM_FORMAT_BGRX8888, 79 DRM_FORMAT_BGRA8888, 80 DRM_FORMAT_ABGR8888, 81 DRM_FORMAT_XBGR8888, 82 DRM_FORMAT_RGB888, 83 DRM_FORMAT_BGR888, 84 DRM_FORMAT_RGB565, 85 DRM_FORMAT_UYVY, 86 DRM_FORMAT_YUYV, 87 }; 88 89 static const u32 mt8195_formats[] = { 90 DRM_FORMAT_XRGB8888, 91 DRM_FORMAT_ARGB8888, 92 DRM_FORMAT_ARGB2101010, 93 DRM_FORMAT_BGRX8888, 94 DRM_FORMAT_BGRA8888, 95 DRM_FORMAT_BGRA1010102, 96 DRM_FORMAT_ABGR8888, 97 DRM_FORMAT_XBGR8888, 98 DRM_FORMAT_RGB888, 99 DRM_FORMAT_BGR888, 100 DRM_FORMAT_RGB565, 101 DRM_FORMAT_UYVY, 102 DRM_FORMAT_YUYV, 103 }; 104 105 struct mtk_disp_ovl_data { 106 unsigned int addr; 107 unsigned int gmc_bits; 108 unsigned int layer_nr; 109 bool fmt_rgb565_is_0; 110 bool smi_id_en; 111 bool supports_afbc; 112 const u32 *formats; 113 size_t num_formats; 114 bool supports_clrfmt_ext; 115 }; 116 117 /* 118 * struct mtk_disp_ovl - DISP_OVL driver structure 119 * @crtc: associated crtc to report vblank events to 120 * @data: platform data 121 */ 122 struct mtk_disp_ovl { 123 struct drm_crtc *crtc; 124 struct clk *clk; 125 void __iomem *regs; 126 struct cmdq_client_reg cmdq_reg; 127 const struct mtk_disp_ovl_data *data; 128 void (*vblank_cb)(void *data); 129 void *vblank_cb_data; 130 }; 131 132 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) 133 { 134 struct mtk_disp_ovl *priv = dev_id; 135 136 /* Clear frame completion interrupt */ 137 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); 138 139 if (!priv->vblank_cb) 140 return IRQ_NONE; 141 142 priv->vblank_cb(priv->vblank_cb_data); 143 144 return IRQ_HANDLED; 145 } 146 147 void mtk_ovl_register_vblank_cb(struct device *dev, 148 void (*vblank_cb)(void *), 149 void *vblank_cb_data) 150 { 151 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 152 153 ovl->vblank_cb = vblank_cb; 154 ovl->vblank_cb_data = vblank_cb_data; 155 } 156 157 void mtk_ovl_unregister_vblank_cb(struct device *dev) 158 { 159 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 160 161 ovl->vblank_cb = NULL; 162 ovl->vblank_cb_data = NULL; 163 } 164 165 void mtk_ovl_enable_vblank(struct device *dev) 166 { 167 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 168 169 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); 170 writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); 171 } 172 173 void mtk_ovl_disable_vblank(struct device *dev) 174 { 175 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 176 177 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); 178 } 179 180 const u32 *mtk_ovl_get_formats(struct device *dev) 181 { 182 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 183 184 return ovl->data->formats; 185 } 186 187 size_t mtk_ovl_get_num_formats(struct device *dev) 188 { 189 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 190 191 return ovl->data->num_formats; 192 } 193 194 int mtk_ovl_clk_enable(struct device *dev) 195 { 196 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 197 198 return clk_prepare_enable(ovl->clk); 199 } 200 201 void mtk_ovl_clk_disable(struct device *dev) 202 { 203 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 204 205 clk_disable_unprepare(ovl->clk); 206 } 207 208 void mtk_ovl_start(struct device *dev) 209 { 210 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 211 212 if (ovl->data->smi_id_en) { 213 unsigned int reg; 214 215 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 216 reg = reg | OVL_LAYER_SMI_ID_EN; 217 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 218 } 219 writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); 220 } 221 222 void mtk_ovl_stop(struct device *dev) 223 { 224 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 225 226 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); 227 if (ovl->data->smi_id_en) { 228 unsigned int reg; 229 230 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 231 reg = reg & ~OVL_LAYER_SMI_ID_EN; 232 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 233 } 234 } 235 236 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt, 237 int idx, bool enabled) 238 { 239 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0, 240 &ovl->cmdq_reg, ovl->regs, 241 DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); 242 } 243 244 static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, 245 struct cmdq_pkt *cmdq_pkt) 246 { 247 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 248 unsigned int reg; 249 unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; 250 251 if (!ovl->data->supports_clrfmt_ext) 252 return; 253 254 reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); 255 reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); 256 257 if (format == DRM_FORMAT_RGBA1010102 || 258 format == DRM_FORMAT_BGRA1010102 || 259 format == DRM_FORMAT_ARGB2101010) 260 bit_depth = OVL_CON_CLRFMT_10_BIT; 261 262 reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); 263 264 mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, 265 ovl->regs, DISP_REG_OVL_CLRFMT_EXT); 266 } 267 268 void mtk_ovl_config(struct device *dev, unsigned int w, 269 unsigned int h, unsigned int vrefresh, 270 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) 271 { 272 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 273 274 if (w != 0 && h != 0) 275 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, 276 DISP_REG_OVL_ROI_SIZE); 277 mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR); 278 279 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); 280 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); 281 } 282 283 unsigned int mtk_ovl_layer_nr(struct device *dev) 284 { 285 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 286 287 return ovl->data->layer_nr; 288 } 289 290 unsigned int mtk_ovl_supported_rotations(struct device *dev) 291 { 292 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 293 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 294 } 295 296 int mtk_ovl_layer_check(struct device *dev, unsigned int idx, 297 struct mtk_plane_state *mtk_state) 298 { 299 struct drm_plane_state *state = &mtk_state->base; 300 unsigned int rotation = 0; 301 302 rotation = drm_rotation_simplify(state->rotation, 303 DRM_MODE_ROTATE_0 | 304 DRM_MODE_REFLECT_X | 305 DRM_MODE_REFLECT_Y); 306 rotation &= ~DRM_MODE_ROTATE_0; 307 308 /* We can only do reflection, not rotation */ 309 if ((rotation & DRM_MODE_ROTATE_MASK) != 0) 310 return -EINVAL; 311 312 /* 313 * TODO: Rotating/reflecting YUV buffers is not supported at this time. 314 * Only RGB[AX] variants are supported. 315 */ 316 if (state->fb->format->is_yuv && rotation != 0) 317 return -EINVAL; 318 319 state->rotation = rotation; 320 321 return 0; 322 } 323 324 void mtk_ovl_layer_on(struct device *dev, unsigned int idx, 325 struct cmdq_pkt *cmdq_pkt) 326 { 327 unsigned int gmc_thrshd_l; 328 unsigned int gmc_thrshd_h; 329 unsigned int gmc_value; 330 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 331 332 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, 333 DISP_REG_OVL_RDMA_CTRL(idx)); 334 gmc_thrshd_l = GMC_THRESHOLD_LOW >> 335 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 336 gmc_thrshd_h = GMC_THRESHOLD_HIGH >> 337 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); 338 if (ovl->data->gmc_bits == 10) 339 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16; 340 else 341 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | 342 gmc_thrshd_h << 16 | gmc_thrshd_h << 24; 343 mtk_ddp_write(cmdq_pkt, gmc_value, 344 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); 345 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, 346 DISP_REG_OVL_SRC_CON, BIT(idx)); 347 } 348 349 void mtk_ovl_layer_off(struct device *dev, unsigned int idx, 350 struct cmdq_pkt *cmdq_pkt) 351 { 352 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 353 354 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, 355 DISP_REG_OVL_SRC_CON, BIT(idx)); 356 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, 357 DISP_REG_OVL_RDMA_CTRL(idx)); 358 } 359 360 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) 361 { 362 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 363 * is defined in mediatek HW data sheet. 364 * The alphabet order in XXX is no relation to data 365 * arrangement in memory. 366 */ 367 switch (fmt) { 368 default: 369 case DRM_FORMAT_RGB565: 370 return OVL_CON_CLRFMT_RGB565(ovl); 371 case DRM_FORMAT_BGR565: 372 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; 373 case DRM_FORMAT_RGB888: 374 return OVL_CON_CLRFMT_RGB888(ovl); 375 case DRM_FORMAT_BGR888: 376 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; 377 case DRM_FORMAT_RGBX8888: 378 case DRM_FORMAT_RGBA8888: 379 return OVL_CON_CLRFMT_ARGB8888; 380 case DRM_FORMAT_BGRX8888: 381 case DRM_FORMAT_BGRA8888: 382 case DRM_FORMAT_BGRA1010102: 383 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; 384 case DRM_FORMAT_XRGB8888: 385 case DRM_FORMAT_ARGB8888: 386 case DRM_FORMAT_ARGB2101010: 387 return OVL_CON_CLRFMT_RGBA8888; 388 case DRM_FORMAT_XBGR8888: 389 case DRM_FORMAT_ABGR8888: 390 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; 391 case DRM_FORMAT_UYVY: 392 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; 393 case DRM_FORMAT_YUYV: 394 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; 395 } 396 } 397 398 void mtk_ovl_layer_config(struct device *dev, unsigned int idx, 399 struct mtk_plane_state *state, 400 struct cmdq_pkt *cmdq_pkt) 401 { 402 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 403 struct mtk_plane_pending_state *pending = &state->pending; 404 unsigned int addr = pending->addr; 405 unsigned int hdr_addr = pending->hdr_addr; 406 unsigned int pitch = pending->pitch; 407 unsigned int hdr_pitch = pending->hdr_pitch; 408 unsigned int fmt = pending->format; 409 unsigned int offset = (pending->y << 16) | pending->x; 410 unsigned int src_size = (pending->height << 16) | pending->width; 411 unsigned int con; 412 bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR; 413 union overlay_pitch { 414 struct split_pitch { 415 u16 lsb; 416 u16 msb; 417 } split_pitch; 418 u32 pitch; 419 } overlay_pitch; 420 421 overlay_pitch.pitch = pitch; 422 423 if (!pending->enable) { 424 mtk_ovl_layer_off(dev, idx, cmdq_pkt); 425 return; 426 } 427 428 con = ovl_fmt_convert(ovl, fmt); 429 if (state->base.fb && state->base.fb->format->has_alpha) 430 con |= OVL_CON_AEN | OVL_CON_ALPHA; 431 432 if (pending->rotation & DRM_MODE_REFLECT_Y) { 433 con |= OVL_CON_VIRT_FLIP; 434 addr += (pending->height - 1) * pending->pitch; 435 } 436 437 if (pending->rotation & DRM_MODE_REFLECT_X) { 438 con |= OVL_CON_HORZ_FLIP; 439 addr += pending->pitch - 1; 440 } 441 442 if (ovl->data->supports_afbc) 443 mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc); 444 445 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, 446 DISP_REG_OVL_CON(idx)); 447 mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs, 448 DISP_REG_OVL_PITCH(idx)); 449 mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, 450 DISP_REG_OVL_SRC_SIZE(idx)); 451 mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, 452 DISP_REG_OVL_OFFSET(idx)); 453 mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, 454 DISP_REG_OVL_ADDR(ovl, idx)); 455 456 if (is_afbc) { 457 mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs, 458 DISP_REG_OVL_HDR_ADDR(ovl, idx)); 459 mtk_ddp_write_relaxed(cmdq_pkt, 460 OVL_PITCH_MSB_2ND_SUBBUF | overlay_pitch.split_pitch.msb, 461 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); 462 mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs, 463 DISP_REG_OVL_HDR_PITCH(ovl, idx)); 464 } else { 465 mtk_ddp_write_relaxed(cmdq_pkt, 466 overlay_pitch.split_pitch.msb, 467 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); 468 } 469 470 mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); 471 mtk_ovl_layer_on(dev, idx, cmdq_pkt); 472 } 473 474 void mtk_ovl_bgclr_in_on(struct device *dev) 475 { 476 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 477 unsigned int reg; 478 479 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 480 reg = reg | OVL_BGCLR_SEL_IN; 481 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 482 } 483 484 void mtk_ovl_bgclr_in_off(struct device *dev) 485 { 486 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 487 unsigned int reg; 488 489 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); 490 reg = reg & ~OVL_BGCLR_SEL_IN; 491 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); 492 } 493 494 static int mtk_disp_ovl_bind(struct device *dev, struct device *master, 495 void *data) 496 { 497 return 0; 498 } 499 500 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, 501 void *data) 502 { 503 } 504 505 static const struct component_ops mtk_disp_ovl_component_ops = { 506 .bind = mtk_disp_ovl_bind, 507 .unbind = mtk_disp_ovl_unbind, 508 }; 509 510 static int mtk_disp_ovl_probe(struct platform_device *pdev) 511 { 512 struct device *dev = &pdev->dev; 513 struct mtk_disp_ovl *priv; 514 struct resource *res; 515 int irq; 516 int ret; 517 518 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 519 if (!priv) 520 return -ENOMEM; 521 522 irq = platform_get_irq(pdev, 0); 523 if (irq < 0) 524 return irq; 525 526 priv->clk = devm_clk_get(dev, NULL); 527 if (IS_ERR(priv->clk)) { 528 dev_err(dev, "failed to get ovl clk\n"); 529 return PTR_ERR(priv->clk); 530 } 531 532 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 533 priv->regs = devm_ioremap_resource(dev, res); 534 if (IS_ERR(priv->regs)) { 535 dev_err(dev, "failed to ioremap ovl\n"); 536 return PTR_ERR(priv->regs); 537 } 538 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 539 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); 540 if (ret) 541 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); 542 #endif 543 544 priv->data = of_device_get_match_data(dev); 545 platform_set_drvdata(pdev, priv); 546 547 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, 548 IRQF_TRIGGER_NONE, dev_name(dev), priv); 549 if (ret < 0) { 550 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 551 return ret; 552 } 553 554 pm_runtime_enable(dev); 555 556 ret = component_add(dev, &mtk_disp_ovl_component_ops); 557 if (ret) { 558 pm_runtime_disable(dev); 559 dev_err(dev, "Failed to add component: %d\n", ret); 560 } 561 562 return ret; 563 } 564 565 static int mtk_disp_ovl_remove(struct platform_device *pdev) 566 { 567 component_del(&pdev->dev, &mtk_disp_ovl_component_ops); 568 pm_runtime_disable(&pdev->dev); 569 570 return 0; 571 } 572 573 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { 574 .addr = DISP_REG_OVL_ADDR_MT2701, 575 .gmc_bits = 8, 576 .layer_nr = 4, 577 .fmt_rgb565_is_0 = false, 578 .formats = mt8173_formats, 579 .num_formats = ARRAY_SIZE(mt8173_formats), 580 }; 581 582 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { 583 .addr = DISP_REG_OVL_ADDR_MT8173, 584 .gmc_bits = 8, 585 .layer_nr = 4, 586 .fmt_rgb565_is_0 = true, 587 .formats = mt8173_formats, 588 .num_formats = ARRAY_SIZE(mt8173_formats), 589 }; 590 591 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { 592 .addr = DISP_REG_OVL_ADDR_MT8173, 593 .gmc_bits = 10, 594 .layer_nr = 4, 595 .fmt_rgb565_is_0 = true, 596 .formats = mt8173_formats, 597 .num_formats = ARRAY_SIZE(mt8173_formats), 598 }; 599 600 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { 601 .addr = DISP_REG_OVL_ADDR_MT8173, 602 .gmc_bits = 10, 603 .layer_nr = 2, 604 .fmt_rgb565_is_0 = true, 605 .formats = mt8173_formats, 606 .num_formats = ARRAY_SIZE(mt8173_formats), 607 }; 608 609 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { 610 .addr = DISP_REG_OVL_ADDR_MT8173, 611 .gmc_bits = 10, 612 .layer_nr = 4, 613 .fmt_rgb565_is_0 = true, 614 .smi_id_en = true, 615 .formats = mt8173_formats, 616 .num_formats = ARRAY_SIZE(mt8173_formats), 617 }; 618 619 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { 620 .addr = DISP_REG_OVL_ADDR_MT8173, 621 .gmc_bits = 10, 622 .layer_nr = 2, 623 .fmt_rgb565_is_0 = true, 624 .smi_id_en = true, 625 .formats = mt8173_formats, 626 .num_formats = ARRAY_SIZE(mt8173_formats), 627 }; 628 629 static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { 630 .addr = DISP_REG_OVL_ADDR_MT8173, 631 .gmc_bits = 10, 632 .layer_nr = 4, 633 .fmt_rgb565_is_0 = true, 634 .smi_id_en = true, 635 .supports_afbc = true, 636 .formats = mt8195_formats, 637 .num_formats = ARRAY_SIZE(mt8195_formats), 638 .supports_clrfmt_ext = true, 639 }; 640 641 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 642 { .compatible = "mediatek,mt2701-disp-ovl", 643 .data = &mt2701_ovl_driver_data}, 644 { .compatible = "mediatek,mt8173-disp-ovl", 645 .data = &mt8173_ovl_driver_data}, 646 { .compatible = "mediatek,mt8183-disp-ovl", 647 .data = &mt8183_ovl_driver_data}, 648 { .compatible = "mediatek,mt8183-disp-ovl-2l", 649 .data = &mt8183_ovl_2l_driver_data}, 650 { .compatible = "mediatek,mt8192-disp-ovl", 651 .data = &mt8192_ovl_driver_data}, 652 { .compatible = "mediatek,mt8192-disp-ovl-2l", 653 .data = &mt8192_ovl_2l_driver_data}, 654 { .compatible = "mediatek,mt8195-disp-ovl", 655 .data = &mt8195_ovl_driver_data}, 656 {}, 657 }; 658 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); 659 660 struct platform_driver mtk_disp_ovl_driver = { 661 .probe = mtk_disp_ovl_probe, 662 .remove = mtk_disp_ovl_remove, 663 .driver = { 664 .name = "mediatek-disp-ovl", 665 .owner = THIS_MODULE, 666 .of_match_table = mtk_disp_ovl_driver_dt_match, 667 }, 668 }; 669