1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/clk.h> 3 #include <linux/component.h> 4 #include <linux/delay.h> 5 #include <linux/io.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/module.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <linux/regulator/consumer.h> 12 #include <video/mipi_display.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_bridge.h> 16 #include <drm/drm_device.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_encoder.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_modeset_helper_vtables.h> 21 #include <drm/drm_of.h> 22 #include <drm/drm_panel.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 26 #include "mcde_drm.h" 27 #include "mcde_dsi_regs.h" 28 29 #define DSI_DEFAULT_LP_FREQ_HZ 19200000 30 #define DSI_DEFAULT_HS_FREQ_HZ 420160000 31 32 /* PRCMU DSI reset registers */ 33 #define PRCM_DSI_SW_RESET 0x324 34 #define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) 35 #define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) 36 #define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) 37 38 struct mcde_dsi { 39 struct device *dev; 40 struct mcde *mcde; 41 struct drm_bridge bridge; 42 struct drm_panel *panel; 43 struct drm_bridge *bridge_out; 44 struct mipi_dsi_host dsi_host; 45 struct mipi_dsi_device *mdsi; 46 struct clk *hs_clk; 47 struct clk *lp_clk; 48 unsigned long hs_freq; 49 unsigned long lp_freq; 50 bool unused; 51 52 void __iomem *regs; 53 struct regmap *prcmu; 54 }; 55 56 static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge) 57 { 58 return container_of(bridge, struct mcde_dsi, bridge); 59 } 60 61 static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h) 62 { 63 return container_of(h, struct mcde_dsi, dsi_host); 64 } 65 66 bool mcde_dsi_irq(struct mipi_dsi_device *mdsi) 67 { 68 struct mcde_dsi *d; 69 u32 val; 70 bool te_received = false; 71 72 d = host_to_mcde_dsi(mdsi->host); 73 74 dev_dbg(d->dev, "%s called\n", __func__); 75 76 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); 77 if (val) 78 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); 79 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 80 dev_dbg(d->dev, "direct command write completed\n"); 81 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) { 82 te_received = true; 83 dev_dbg(d->dev, "direct command TE received\n"); 84 } 85 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) 86 dev_err(d->dev, "direct command ACK ERR received\n"); 87 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) 88 dev_err(d->dev, "direct command read ERR received\n"); 89 /* Mask off the ACK value and clear status */ 90 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR); 91 92 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG); 93 if (val) 94 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val); 95 if (val & DSI_CMD_MODE_STS_ERR_NO_TE) 96 /* This happens all the time (safe to ignore) */ 97 dev_dbg(d->dev, "CMD mode no TE\n"); 98 if (val & DSI_CMD_MODE_STS_ERR_TE_MISS) 99 /* This happens all the time (safe to ignore) */ 100 dev_dbg(d->dev, "CMD mode TE miss\n"); 101 if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN) 102 dev_err(d->dev, "CMD mode SD1 underrun\n"); 103 if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN) 104 dev_err(d->dev, "CMD mode SD2 underrun\n"); 105 if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD) 106 dev_err(d->dev, "CMD mode unwanted RD\n"); 107 writel(val, d->regs + DSI_CMD_MODE_STS_CLR); 108 109 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG); 110 if (val) 111 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val); 112 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR); 113 114 val = readl(d->regs + DSI_TG_STS_FLAG); 115 if (val) 116 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val); 117 writel(val, d->regs + DSI_TG_STS_CLR); 118 119 val = readl(d->regs + DSI_VID_MODE_STS_FLAG); 120 if (val) 121 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val); 122 if (val & DSI_VID_MODE_STS_VSG_RUNNING) 123 dev_dbg(d->dev, "VID mode VSG running\n"); 124 if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA) 125 dev_err(d->dev, "VID mode missing data\n"); 126 if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC) 127 dev_err(d->dev, "VID mode missing HSYNC\n"); 128 if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC) 129 dev_err(d->dev, "VID mode missing VSYNC\n"); 130 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH) 131 dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n"); 132 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT) 133 dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n"); 134 if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE | 135 DSI_VID_MODE_STS_ERR_LINEWRITE | 136 DSI_VID_MODE_STS_ERR_LONGREAD)) 137 dev_err(d->dev, "VID mode read/write error\n"); 138 if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH) 139 dev_err(d->dev, "VID mode received packets differ from expected size\n"); 140 if (val & DSI_VID_MODE_STS_VSG_RECOVERY) 141 dev_err(d->dev, "VID mode VSG in recovery mode\n"); 142 writel(val, d->regs + DSI_VID_MODE_STS_CLR); 143 144 return te_received; 145 } 146 147 static void mcde_dsi_attach_to_mcde(struct mcde_dsi *d) 148 { 149 d->mcde->mdsi = d->mdsi; 150 151 d->mcde->video_mode = !!(d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO); 152 /* Enable use of the TE signal for all command mode panels */ 153 d->mcde->te_sync = !d->mcde->video_mode; 154 } 155 156 static int mcde_dsi_host_attach(struct mipi_dsi_host *host, 157 struct mipi_dsi_device *mdsi) 158 { 159 struct mcde_dsi *d = host_to_mcde_dsi(host); 160 161 if (mdsi->lanes < 1 || mdsi->lanes > 2) { 162 DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n"); 163 return -EINVAL; 164 } 165 166 dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes); 167 /* MIPI_DSI_FMT_RGB88 etc */ 168 dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format, 169 mipi_dsi_pixel_format_to_bpp(mdsi->format)); 170 dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags); 171 172 d->mdsi = mdsi; 173 if (d->mcde) 174 mcde_dsi_attach_to_mcde(d); 175 176 return 0; 177 } 178 179 static int mcde_dsi_host_detach(struct mipi_dsi_host *host, 180 struct mipi_dsi_device *mdsi) 181 { 182 struct mcde_dsi *d = host_to_mcde_dsi(host); 183 184 d->mdsi = NULL; 185 if (d->mcde) 186 d->mcde->mdsi = NULL; 187 188 return 0; 189 } 190 191 #define MCDE_DSI_HOST_IS_READ(type) \ 192 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 193 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 194 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 195 (type == MIPI_DSI_DCS_READ)) 196 197 static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, 198 const struct mipi_dsi_msg *msg) 199 { 200 struct mcde_dsi *d = host_to_mcde_dsi(host); 201 const u32 loop_delay_us = 10; /* us */ 202 const u8 *tx = msg->tx_buf; 203 u32 loop_counter; 204 size_t txlen = msg->tx_len; 205 size_t rxlen = msg->rx_len; 206 u32 val; 207 int ret; 208 int i; 209 210 if (txlen > 16) { 211 dev_err(d->dev, 212 "dunno how to write more than 16 bytes yet\n"); 213 return -EIO; 214 } 215 if (rxlen > 4) { 216 dev_err(d->dev, 217 "dunno how to read more than 4 bytes yet\n"); 218 return -EIO; 219 } 220 221 dev_dbg(d->dev, 222 "message to channel %d, write %zd bytes read %zd bytes\n", 223 msg->channel, txlen, rxlen); 224 225 /* Command "nature" */ 226 if (MCDE_DSI_HOST_IS_READ(msg->type)) 227 /* MCTL_MAIN_DATA_CTL already set up */ 228 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ; 229 else 230 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE; 231 /* 232 * More than 2 bytes will not fit in a single packet, so it's 233 * time to set the "long not short" bit. One byte is used by 234 * the MIPI DCS command leaving just one byte for the payload 235 * in a short package. 236 */ 237 if (mipi_dsi_packet_format_is_long(msg->type)) 238 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT; 239 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 240 val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 241 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 242 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 243 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 244 245 /* MIPI DCS command is part of the data */ 246 if (txlen > 0) { 247 val = 0; 248 for (i = 0; i < 4 && i < txlen; i++) 249 val |= tx[i] << (i * 8); 250 } 251 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0); 252 if (txlen > 4) { 253 val = 0; 254 for (i = 0; i < 4 && (i + 4) < txlen; i++) 255 val |= tx[i + 4] << (i * 8); 256 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1); 257 } 258 if (txlen > 8) { 259 val = 0; 260 for (i = 0; i < 4 && (i + 8) < txlen; i++) 261 val |= tx[i + 8] << (i * 8); 262 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2); 263 } 264 if (txlen > 12) { 265 val = 0; 266 for (i = 0; i < 4 && (i + 12) < txlen; i++) 267 val |= tx[i + 12] << (i * 8); 268 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3); 269 } 270 271 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 272 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 273 /* Send command */ 274 writel(1, d->regs + DSI_DIRECT_CMD_SEND); 275 276 loop_counter = 1000 * 1000 / loop_delay_us; 277 if (MCDE_DSI_HOST_IS_READ(msg->type)) { 278 /* Read command */ 279 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 280 (DSI_DIRECT_CMD_STS_READ_COMPLETED | 281 DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)) 282 && --loop_counter) 283 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 284 if (!loop_counter) { 285 dev_err(d->dev, "DSI read timeout!\n"); 286 return -ETIME; 287 } 288 } else { 289 /* Writing only */ 290 while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 291 DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 292 && --loop_counter) 293 usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 294 295 if (!loop_counter) { 296 dev_err(d->dev, "DSI write timeout!\n"); 297 return -ETIME; 298 } 299 } 300 301 val = readl(d->regs + DSI_DIRECT_CMD_STS); 302 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) { 303 dev_err(d->dev, "read completed with error\n"); 304 writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT); 305 return -EIO; 306 } 307 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) { 308 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT; 309 dev_err(d->dev, "error during transmission: %04x\n", 310 val); 311 return -EIO; 312 } 313 314 if (!MCDE_DSI_HOST_IS_READ(msg->type)) { 315 /* Return number of bytes written */ 316 ret = txlen; 317 } else { 318 /* OK this is a read command, get the response */ 319 u32 rdsz; 320 u32 rddat; 321 u8 *rx = msg->rx_buf; 322 323 rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY); 324 rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK; 325 rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT); 326 if (rdsz < rxlen) { 327 dev_err(d->dev, "read error, requested %zd got %d\n", 328 rxlen, rdsz); 329 return -EIO; 330 } 331 /* FIXME: read more than 4 bytes */ 332 for (i = 0; i < 4 && i < rxlen; i++) 333 rx[i] = (rddat >> (i * 8)) & 0xff; 334 ret = rdsz; 335 } 336 337 writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 338 writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 339 340 return ret; 341 } 342 343 static const struct mipi_dsi_host_ops mcde_dsi_host_ops = { 344 .attach = mcde_dsi_host_attach, 345 .detach = mcde_dsi_host_detach, 346 .transfer = mcde_dsi_host_transfer, 347 }; 348 349 /* This sends a direct (short) command to request TE */ 350 void mcde_dsi_te_request(struct mipi_dsi_device *mdsi) 351 { 352 struct mcde_dsi *d; 353 u32 val; 354 355 d = host_to_mcde_dsi(mdsi->host); 356 357 /* Command "nature" TE request */ 358 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ; 359 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 360 val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 361 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 362 val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM << 363 DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 364 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 365 366 /* Clear TE reveived and error status bits and enables them */ 367 writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR | 368 DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR, 369 d->regs + DSI_DIRECT_CMD_STS_CLR); 370 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL); 371 val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN; 372 val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN; 373 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL); 374 375 /* Clear and enable no TE or TE missing status */ 376 writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR | 377 DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR, 378 d->regs + DSI_CMD_MODE_STS_CLR); 379 val = readl(d->regs + DSI_CMD_MODE_STS_CTL); 380 val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN; 381 val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN; 382 writel(val, d->regs + DSI_CMD_MODE_STS_CTL); 383 384 /* Send this TE request command */ 385 writel(1, d->regs + DSI_DIRECT_CMD_SEND); 386 } 387 388 static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, 389 const struct drm_display_mode *mode) 390 { 391 /* cpp, characters per pixel, number of bytes per pixel */ 392 u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8; 393 u64 pclk; 394 u64 bpl; 395 int hfp; 396 int hbp; 397 int hsa; 398 u32 blkline_pck, line_duration; 399 u32 val; 400 401 val = 0; 402 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 403 val |= DSI_VID_MAIN_CTL_BURST_MODE; 404 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 405 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE; 406 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL; 407 } 408 /* RGB header and pixel mode */ 409 switch (d->mdsi->format) { 410 case MIPI_DSI_FMT_RGB565: 411 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 << 412 DSI_VID_MAIN_CTL_HEADER_SHIFT; 413 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS; 414 break; 415 case MIPI_DSI_FMT_RGB666_PACKED: 416 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 << 417 DSI_VID_MAIN_CTL_HEADER_SHIFT; 418 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS; 419 break; 420 case MIPI_DSI_FMT_RGB666: 421 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18 422 << DSI_VID_MAIN_CTL_HEADER_SHIFT; 423 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE; 424 break; 425 case MIPI_DSI_FMT_RGB888: 426 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 << 427 DSI_VID_MAIN_CTL_HEADER_SHIFT; 428 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS; 429 break; 430 default: 431 dev_err(d->dev, "unknown pixel mode\n"); 432 return; 433 } 434 435 /* TODO: TVG (test video generator) could be enabled here */ 436 437 /* 438 * During vertical blanking: go to LP mode 439 * Like with the EOL setting, if this is not set, the EOL area will be 440 * filled with NULL or blanking packets in the vblank area. 441 * FIXME: some Samsung phones and display panels such as s6e63m0 use 442 * DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING here instead, 443 * figure out how to properly configure that from the panel. 444 */ 445 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0; 446 /* 447 * During EOL: go to LP mode. If this is not set, the EOL area will be 448 * filled with NULL or blanking packets. 449 */ 450 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0; 451 /* Recovery mode 1 */ 452 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT; 453 /* All other fields zero */ 454 writel(val, d->regs + DSI_VID_MAIN_CTL); 455 456 /* Vertical frame parameters are pretty straight-forward */ 457 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT; 458 /* vertical front porch */ 459 val |= (mode->vsync_start - mode->vdisplay) 460 << DSI_VID_VSIZE_VFP_LENGTH_SHIFT; 461 /* vertical sync active */ 462 val |= (mode->vsync_end - mode->vsync_start) 463 << DSI_VID_VSIZE_VSA_LENGTH_SHIFT; 464 /* vertical back porch */ 465 val |= (mode->vtotal - mode->vsync_end) 466 << DSI_VID_VSIZE_VBP_LENGTH_SHIFT; 467 writel(val, d->regs + DSI_VID_VSIZE); 468 469 /* 470 * Horizontal frame parameters: 471 * horizontal resolution is given in pixels but must be re-calculated 472 * into bytes since this is what the hardware expects, these registers 473 * define the payload size of the packet. 474 * 475 * hfp = horizontal front porch in bytes 476 * hbp = horizontal back porch in bytes 477 * hsa = horizontal sync active in bytes 478 * 479 * 6 + 2 is HFP header + checksum 480 */ 481 hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2; 482 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 483 /* 484 * Use sync pulse for sync: explicit HSA time 485 * 6 is HBP header + checksum 486 * 4 is RGB header + checksum 487 */ 488 hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6; 489 /* 490 * 6 is HBP header + checksum 491 * 4 is HSW packet bytes 492 * 4 is RGB header + checksum 493 */ 494 hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6; 495 } else { 496 /* 497 * Use event for sync: HBP includes both back porch and sync 498 * 6 is HBP header + checksum 499 * 4 is HSW packet bytes 500 * 4 is RGB header + checksum 501 */ 502 hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6; 503 /* HSA is not present in this mode and set to 0 */ 504 hsa = 0; 505 } 506 if (hfp < 0) { 507 dev_info(d->dev, "hfp negative, set to 0\n"); 508 hfp = 0; 509 } 510 if (hbp < 0) { 511 dev_info(d->dev, "hbp negative, set to 0\n"); 512 hbp = 0; 513 } 514 if (hsa < 0) { 515 dev_info(d->dev, "hsa negative, set to 0\n"); 516 hsa = 0; 517 } 518 dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n", 519 hfp, hbp, hsa); 520 521 /* Frame parameters: horizontal sync active */ 522 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT; 523 /* horizontal back porch */ 524 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT; 525 /* horizontal front porch */ 526 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT; 527 writel(val, d->regs + DSI_VID_HSIZE1); 528 529 /* RGB data length (visible bytes on one scanline) */ 530 val = mode->hdisplay * cpp; 531 writel(val, d->regs + DSI_VID_HSIZE2); 532 dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val); 533 534 /* 535 * Calculate the time between two pixels in picoseconds using 536 * the supplied refresh rate and total resolution including 537 * porches and sync. 538 */ 539 /* (ps/s) / (pixels/s) = ps/pixels */ 540 pclk = DIV_ROUND_UP_ULL(1000000000000, 541 (mode->vrefresh * mode->htotal * mode->vtotal)); 542 dev_dbg(d->dev, "picoseconds between two pixels: %llu\n", 543 pclk); 544 545 /* 546 * How many bytes per line will this update frequency yield? 547 * 548 * Calculate the number of picoseconds for one scanline (1), then 549 * divide by 1000000000000 (2) to get in pixels per second we 550 * want to output. 551 * 552 * Multiply with number of bytes per second at this video display 553 * frequency (3) to get number of bytes transferred during this 554 * time. Notice that we use the frequency the display wants, 555 * not what we actually get from the DSI PLL, which is hs_freq. 556 * 557 * These arithmetics are done in a different order to avoid 558 * overflow. 559 */ 560 bpl = pclk * mode->htotal; /* (1) picoseconds per line */ 561 dev_dbg(d->dev, "picoseconds per line: %llu\n", bpl); 562 /* Multiply with bytes per second (3) */ 563 bpl *= (d->mdsi->hs_rate / 8); 564 /* Pixels per second (2) */ 565 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* microseconds */ 566 bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* seconds */ 567 /* parallel transactions in all lanes */ 568 bpl *= d->mdsi->lanes; 569 dev_dbg(d->dev, 570 "calculated bytes per line: %llu @ %d Hz with HS %lu Hz\n", 571 bpl, mode->vrefresh, d->mdsi->hs_rate); 572 573 /* 574 * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes 575 * 4 is short packet for vsync/hsync 576 */ 577 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 578 /* Set the event packet size to 0 (not used) */ 579 writel(0, d->regs + DSI_VID_BLKSIZE1); 580 /* 581 * FIXME: isn't the hsync width in pixels? The porch and 582 * sync area size is in pixels here, but this -6 583 * seems to be for bytes. It looks like this in the vendor 584 * code though. Is it completely untested? 585 */ 586 blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6; 587 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT; 588 writel(val, d->regs + DSI_VID_BLKSIZE2); 589 } else { 590 /* Set the sync pulse packet size to 0 (not used) */ 591 writel(0, d->regs + DSI_VID_BLKSIZE2); 592 /* Specifying payload size in bytes (-4-6 from manual) */ 593 blkline_pck = bpl - 4 - 6; 594 if (blkline_pck > 0x1FFF) 595 dev_err(d->dev, "blkline_pck too big %d bytes\n", 596 blkline_pck); 597 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT; 598 val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK; 599 writel(val, d->regs + DSI_VID_BLKSIZE1); 600 } 601 602 /* 603 * The line duration is used to scale back the frequency from 604 * the max frequency supported by the HS clock to the desired 605 * update frequency in vrefresh. 606 */ 607 line_duration = blkline_pck + 6; 608 /* 609 * The datasheet contains this complex condition to decreasing 610 * the line duration by 1 under very specific circumstances. 611 * Here we also imply that LP is used during burst EOL. 612 */ 613 if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01) 614 && (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) 615 line_duration--; 616 line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes); 617 dev_dbg(d->dev, "line duration %u bytes\n", line_duration); 618 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT; 619 /* 620 * This is the time to perform LP->HS on D-PHY 621 * FIXME: nowhere to get this from: DT property on the DSI? 622 * The manual says this is "system dependent". 623 * values like 48 and 72 seen in the vendor code. 624 */ 625 val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT; 626 writel(val, d->regs + DSI_VID_DPHY_TIME); 627 628 /* 629 * See the manual figure 657 page 2203 for understanding the impact 630 * of the different burst mode settings. 631 */ 632 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 633 int blkeol_pck, blkeol_duration; 634 /* 635 * Packet size at EOL for burst mode, this is only used 636 * if DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is NOT set, 637 * but we instead send NULL or blanking packets at EOL. 638 * This is given in number of bytes. 639 * 640 * See the manual page 2198 for the 13 reg_blkeol_pck bits. 641 */ 642 blkeol_pck = bpl - (mode->htotal * cpp) - 6; 643 if (blkeol_pck < 0) { 644 dev_err(d->dev, "video block does not fit on line!\n"); 645 dev_err(d->dev, 646 "calculated bytes per line: %llu @ %d Hz\n", 647 bpl, mode->vrefresh); 648 dev_err(d->dev, 649 "bytes per line (blkline_pck) %u bytes\n", 650 blkline_pck); 651 dev_err(d->dev, 652 "blkeol_pck becomes %d bytes\n", blkeol_pck); 653 return; 654 } 655 dev_dbg(d->dev, "BLKEOL packet: %d bytes\n", blkeol_pck); 656 657 val = readl(d->regs + DSI_VID_BLKSIZE1); 658 val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK; 659 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT; 660 writel(val, d->regs + DSI_VID_BLKSIZE1); 661 /* Use the same value for exact burst limit */ 662 val = blkeol_pck << 663 DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT; 664 val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK; 665 writel(val, d->regs + DSI_VID_VCA_SETTING2); 666 /* 667 * This BLKEOL duration is claimed to be the duration in clock 668 * cycles of the BLLP end-of-line (EOL) period for each line if 669 * DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is set. 670 * 671 * It is hard to trust the manuals' claim that this is in clock 672 * cycles as we mimic the behaviour of the vendor code, which 673 * appears to write a number of bytes that would have been 674 * transferred on a single lane. 675 * 676 * See the manual figure 657 page 2203 and page 2198 for the 13 677 * reg_blkeol_duration bits. 678 * 679 * FIXME: should this also be set up also for non-burst mode 680 * according to figure 565 page 2202? 681 */ 682 blkeol_duration = DIV_ROUND_CLOSEST(blkeol_pck + 6, 683 d->mdsi->lanes); 684 dev_dbg(d->dev, "BLKEOL duration: %d clock cycles\n", 685 blkeol_duration); 686 687 val = readl(d->regs + DSI_VID_PCK_TIME); 688 val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK; 689 val |= blkeol_duration << 690 DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT; 691 writel(val, d->regs + DSI_VID_PCK_TIME); 692 693 /* Max burst limit, this is given in bytes */ 694 val = readl(d->regs + DSI_VID_VCA_SETTING1); 695 val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK; 696 val |= (blkeol_pck - 6) << 697 DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT; 698 writel(val, d->regs + DSI_VID_VCA_SETTING1); 699 } 700 701 /* Maximum line limit */ 702 val = readl(d->regs + DSI_VID_VCA_SETTING2); 703 val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK; 704 val |= (blkline_pck - 6) << 705 DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT; 706 writel(val, d->regs + DSI_VID_VCA_SETTING2); 707 dev_dbg(d->dev, "blkline pck: %d bytes\n", blkline_pck - 6); 708 } 709 710 static void mcde_dsi_start(struct mcde_dsi *d) 711 { 712 unsigned long hs_freq; 713 u32 val; 714 int i; 715 716 /* No integration mode */ 717 writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE); 718 719 /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */ 720 val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN | 721 DSI_MCTL_MAIN_DATA_CTL_BTA_EN | 722 DSI_MCTL_MAIN_DATA_CTL_READ_EN | 723 DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN; 724 if (d->mdsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 725 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN; 726 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 727 728 /* Set a high command timeout, clear other fields */ 729 val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT; 730 writel(val, d->regs + DSI_CMD_MODE_CTL); 731 732 /* 733 * UI_X4 is described as "unit interval times four" 734 * I guess since DSI packets are 4 bytes wide, one unit 735 * is one byte. 736 */ 737 hs_freq = clk_get_rate(d->hs_clk); 738 hs_freq /= 1000000; /* MHz */ 739 val = 4000 / hs_freq; 740 dev_dbg(d->dev, "UI value: %d\n", val); 741 val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT; 742 val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK; 743 writel(val, d->regs + DSI_MCTL_DPHY_STATIC); 744 745 /* 746 * Enable clocking: 0x0f (something?) between each burst, 747 * enable the second lane if needed, enable continuous clock if 748 * needed, enable switch into ULPM (ultra-low power mode) on 749 * all the lines. 750 */ 751 val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT; 752 if (d->mdsi->lanes == 2) 753 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN; 754 if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 755 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS; 756 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN | 757 DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN | 758 DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN; 759 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL); 760 761 val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) | 762 (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT); 763 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME); 764 765 writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90, 766 d->regs + DSI_DPHY_LANES_TRIM); 767 768 /* High PHY timeout */ 769 val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) | 770 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) | 771 (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT); 772 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT); 773 774 val = DSI_MCTL_MAIN_EN_PLL_START | 775 DSI_MCTL_MAIN_EN_CKLANE_EN | 776 DSI_MCTL_MAIN_EN_DAT1_EN | 777 DSI_MCTL_MAIN_EN_IF1_EN; 778 if (d->mdsi->lanes == 2) 779 val |= DSI_MCTL_MAIN_EN_DAT2_EN; 780 writel(val, d->regs + DSI_MCTL_MAIN_EN); 781 782 /* Wait for the PLL to lock and the clock and data lines to come up */ 783 i = 0; 784 val = DSI_MCTL_MAIN_STS_PLL_LOCK | 785 DSI_MCTL_MAIN_STS_CLKLANE_READY | 786 DSI_MCTL_MAIN_STS_DAT1_READY; 787 if (d->mdsi->lanes == 2) 788 val |= DSI_MCTL_MAIN_STS_DAT2_READY; 789 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) { 790 /* Sleep for a millisecond */ 791 usleep_range(1000, 1500); 792 if (i++ == 100) { 793 dev_warn(d->dev, "DSI lanes did not start up\n"); 794 return; 795 } 796 } 797 798 /* TODO needed? */ 799 800 /* Command mode, clear IF1 ID */ 801 val = readl(d->regs + DSI_CMD_MODE_CTL); 802 /* 803 * If we enable low-power mode here, with 804 * val |= DSI_CMD_MODE_CTL_IF1_LP_EN 805 * then display updates become really slow. 806 */ 807 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 808 writel(val, d->regs + DSI_CMD_MODE_CTL); 809 810 /* Wait for DSI PHY to initialize */ 811 usleep_range(100, 200); 812 dev_info(d->dev, "DSI link enabled\n"); 813 } 814 815 816 static void mcde_dsi_bridge_enable(struct drm_bridge *bridge) 817 { 818 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 819 u32 val; 820 821 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 822 /* Enable video mode */ 823 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 824 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; 825 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 826 } 827 828 dev_info(d->dev, "enable DSI master\n"); 829 }; 830 831 static void mcde_dsi_bridge_pre_enable(struct drm_bridge *bridge) 832 { 833 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 834 unsigned long hs_freq, lp_freq; 835 u32 val; 836 int ret; 837 838 /* Copy maximum clock frequencies */ 839 if (d->mdsi->lp_rate) 840 lp_freq = d->mdsi->lp_rate; 841 else 842 lp_freq = DSI_DEFAULT_LP_FREQ_HZ; 843 if (d->mdsi->hs_rate) 844 hs_freq = d->mdsi->hs_rate; 845 else 846 hs_freq = DSI_DEFAULT_HS_FREQ_HZ; 847 848 /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */ 849 d->lp_freq = clk_round_rate(d->lp_clk, lp_freq); 850 ret = clk_set_rate(d->lp_clk, d->lp_freq); 851 if (ret) 852 dev_err(d->dev, "failed to set LP clock rate %lu Hz\n", 853 d->lp_freq); 854 855 d->hs_freq = clk_round_rate(d->hs_clk, hs_freq); 856 ret = clk_set_rate(d->hs_clk, d->hs_freq); 857 if (ret) 858 dev_err(d->dev, "failed to set HS clock rate %lu Hz\n", 859 d->hs_freq); 860 861 /* Start clocks */ 862 ret = clk_prepare_enable(d->lp_clk); 863 if (ret) 864 dev_err(d->dev, "failed to enable LP clock\n"); 865 else 866 dev_info(d->dev, "DSI LP clock rate %lu Hz\n", 867 d->lp_freq); 868 ret = clk_prepare_enable(d->hs_clk); 869 if (ret) 870 dev_err(d->dev, "failed to enable HS clock\n"); 871 else 872 dev_info(d->dev, "DSI HS clock rate %lu Hz\n", 873 d->hs_freq); 874 875 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 876 /* Put IF1 into video mode */ 877 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 878 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE; 879 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 880 881 /* Disable command mode on IF1 */ 882 val = readl(d->regs + DSI_CMD_MODE_CTL); 883 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN; 884 writel(val, d->regs + DSI_CMD_MODE_CTL); 885 886 /* Enable some error interrupts */ 887 val = readl(d->regs + DSI_VID_MODE_STS_CTL); 888 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; 889 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; 890 writel(val, d->regs + DSI_VID_MODE_STS_CTL); 891 } else { 892 /* Command mode, clear IF1 ID */ 893 val = readl(d->regs + DSI_CMD_MODE_CTL); 894 /* 895 * If we enable low-power mode here with 896 * val |= DSI_CMD_MODE_CTL_IF1_LP_EN 897 * the display updates become really slow. 898 */ 899 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 900 writel(val, d->regs + DSI_CMD_MODE_CTL); 901 } 902 } 903 904 static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge, 905 const struct drm_display_mode *mode, 906 const struct drm_display_mode *adj) 907 { 908 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 909 910 if (!d->mdsi) { 911 dev_err(d->dev, "no DSI device attached to encoder!\n"); 912 return; 913 } 914 915 dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n", 916 mode->hdisplay, mode->vdisplay, mode->clock * 1000, 917 (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD" 918 ); 919 920 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) 921 mcde_dsi_setup_video_mode(d, mode); 922 } 923 924 static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d) 925 { 926 u32 val; 927 int i; 928 929 /* 930 * Wait until we get out of command mode 931 * CSM = Command State Machine 932 */ 933 i = 0; 934 val = DSI_CMD_MODE_STS_CSM_RUNNING; 935 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) { 936 /* Sleep for a millisecond */ 937 usleep_range(1000, 2000); 938 if (i++ == 100) { 939 dev_warn(d->dev, 940 "could not get out of command mode\n"); 941 return; 942 } 943 } 944 } 945 946 static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d) 947 { 948 u32 val; 949 int i; 950 951 /* Wait until we get out og video mode */ 952 i = 0; 953 val = DSI_VID_MODE_STS_VSG_RUNNING; 954 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) { 955 /* Sleep for a millisecond */ 956 usleep_range(1000, 2000); 957 if (i++ == 100) { 958 dev_warn(d->dev, 959 "could not get out of video mode\n"); 960 return; 961 } 962 } 963 } 964 965 static void mcde_dsi_bridge_disable(struct drm_bridge *bridge) 966 { 967 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 968 u32 val; 969 970 /* Disable all error interrupts */ 971 writel(0, d->regs + DSI_VID_MODE_STS_CTL); 972 973 if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 974 /* Stop video mode */ 975 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 976 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN; 977 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 978 mcde_dsi_wait_for_video_mode_stop(d); 979 } else { 980 /* Stop command mode */ 981 mcde_dsi_wait_for_command_mode_stop(d); 982 } 983 984 /* Stop clocks */ 985 clk_disable_unprepare(d->hs_clk); 986 clk_disable_unprepare(d->lp_clk); 987 } 988 989 static int mcde_dsi_bridge_attach(struct drm_bridge *bridge, 990 enum drm_bridge_attach_flags flags) 991 { 992 struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 993 struct drm_device *drm = bridge->dev; 994 int ret; 995 996 if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { 997 dev_err(d->dev, "we need atomic updates\n"); 998 return -ENOTSUPP; 999 } 1000 1001 /* Attach the DSI bridge to the output (panel etc) bridge */ 1002 ret = drm_bridge_attach(bridge->encoder, d->bridge_out, bridge, flags); 1003 if (ret) { 1004 dev_err(d->dev, "failed to attach the DSI bridge\n"); 1005 return ret; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = { 1012 .attach = mcde_dsi_bridge_attach, 1013 .mode_set = mcde_dsi_bridge_mode_set, 1014 .disable = mcde_dsi_bridge_disable, 1015 .enable = mcde_dsi_bridge_enable, 1016 .pre_enable = mcde_dsi_bridge_pre_enable, 1017 }; 1018 1019 static int mcde_dsi_bind(struct device *dev, struct device *master, 1020 void *data) 1021 { 1022 struct drm_device *drm = data; 1023 struct mcde *mcde = to_mcde(drm); 1024 struct mcde_dsi *d = dev_get_drvdata(dev); 1025 struct device_node *child; 1026 struct drm_panel *panel = NULL; 1027 struct drm_bridge *bridge = NULL; 1028 1029 if (!of_get_available_child_count(dev->of_node)) { 1030 dev_info(dev, "unused DSI interface\n"); 1031 d->unused = true; 1032 return 0; 1033 } 1034 d->mcde = mcde; 1035 /* If the display attached before binding, set this up */ 1036 if (d->mdsi) 1037 mcde_dsi_attach_to_mcde(d); 1038 1039 /* Obtain the clocks */ 1040 d->hs_clk = devm_clk_get(dev, "hs"); 1041 if (IS_ERR(d->hs_clk)) { 1042 dev_err(dev, "unable to get HS clock\n"); 1043 return PTR_ERR(d->hs_clk); 1044 } 1045 1046 d->lp_clk = devm_clk_get(dev, "lp"); 1047 if (IS_ERR(d->lp_clk)) { 1048 dev_err(dev, "unable to get LP clock\n"); 1049 return PTR_ERR(d->lp_clk); 1050 } 1051 1052 /* Assert RESET through the PRCMU, active low */ 1053 /* FIXME: which DSI block? */ 1054 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 1055 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 1056 1057 usleep_range(100, 200); 1058 1059 /* De-assert RESET again */ 1060 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 1061 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 1062 PRCM_DSI_SW_RESET_DSI0_SW_RESETN); 1063 1064 /* Start up the hardware */ 1065 mcde_dsi_start(d); 1066 1067 /* Look for a panel as a child to this node */ 1068 for_each_available_child_of_node(dev->of_node, child) { 1069 panel = of_drm_find_panel(child); 1070 if (IS_ERR(panel)) { 1071 dev_err(dev, "failed to find panel try bridge (%ld)\n", 1072 PTR_ERR(panel)); 1073 panel = NULL; 1074 1075 bridge = of_drm_find_bridge(child); 1076 if (!bridge) { 1077 dev_err(dev, "failed to find bridge\n"); 1078 return -EINVAL; 1079 } 1080 } 1081 } 1082 if (panel) { 1083 bridge = drm_panel_bridge_add_typed(panel, 1084 DRM_MODE_CONNECTOR_DSI); 1085 if (IS_ERR(bridge)) { 1086 dev_err(dev, "error adding panel bridge\n"); 1087 return PTR_ERR(bridge); 1088 } 1089 dev_info(dev, "connected to panel\n"); 1090 d->panel = panel; 1091 } else if (bridge) { 1092 /* TODO: AV8100 HDMI encoder goes here for example */ 1093 dev_info(dev, "connected to non-panel bridge (unsupported)\n"); 1094 return -ENODEV; 1095 } else { 1096 dev_err(dev, "no panel or bridge\n"); 1097 return -ENODEV; 1098 } 1099 1100 d->bridge_out = bridge; 1101 1102 /* Create a bridge for this DSI channel */ 1103 d->bridge.funcs = &mcde_dsi_bridge_funcs; 1104 d->bridge.of_node = dev->of_node; 1105 drm_bridge_add(&d->bridge); 1106 1107 /* TODO: first come first serve, use a list */ 1108 mcde->bridge = &d->bridge; 1109 1110 dev_info(dev, "initialized MCDE DSI bridge\n"); 1111 1112 return 0; 1113 } 1114 1115 static void mcde_dsi_unbind(struct device *dev, struct device *master, 1116 void *data) 1117 { 1118 struct mcde_dsi *d = dev_get_drvdata(dev); 1119 1120 if (d->panel) 1121 drm_panel_bridge_remove(d->bridge_out); 1122 regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 1123 PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 1124 } 1125 1126 static const struct component_ops mcde_dsi_component_ops = { 1127 .bind = mcde_dsi_bind, 1128 .unbind = mcde_dsi_unbind, 1129 }; 1130 1131 static int mcde_dsi_probe(struct platform_device *pdev) 1132 { 1133 struct device *dev = &pdev->dev; 1134 struct mcde_dsi *d; 1135 struct mipi_dsi_host *host; 1136 struct resource *res; 1137 u32 dsi_id; 1138 int ret; 1139 1140 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 1141 if (!d) 1142 return -ENOMEM; 1143 d->dev = dev; 1144 platform_set_drvdata(pdev, d); 1145 1146 /* Get a handle on the PRCMU so we can do reset */ 1147 d->prcmu = 1148 syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu"); 1149 if (IS_ERR(d->prcmu)) { 1150 dev_err(dev, "no PRCMU regmap\n"); 1151 return PTR_ERR(d->prcmu); 1152 } 1153 1154 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1155 d->regs = devm_ioremap_resource(dev, res); 1156 if (IS_ERR(d->regs)) { 1157 dev_err(dev, "no DSI regs\n"); 1158 return PTR_ERR(d->regs); 1159 } 1160 1161 dsi_id = readl(d->regs + DSI_ID_REG); 1162 dev_info(dev, "HW revision 0x%08x\n", dsi_id); 1163 1164 host = &d->dsi_host; 1165 host->dev = dev; 1166 host->ops = &mcde_dsi_host_ops; 1167 ret = mipi_dsi_host_register(host); 1168 if (ret < 0) { 1169 dev_err(dev, "failed to register DSI host: %d\n", ret); 1170 return ret; 1171 } 1172 dev_info(dev, "registered DSI host\n"); 1173 1174 platform_set_drvdata(pdev, d); 1175 return component_add(dev, &mcde_dsi_component_ops); 1176 } 1177 1178 static int mcde_dsi_remove(struct platform_device *pdev) 1179 { 1180 struct mcde_dsi *d = platform_get_drvdata(pdev); 1181 1182 component_del(&pdev->dev, &mcde_dsi_component_ops); 1183 mipi_dsi_host_unregister(&d->dsi_host); 1184 1185 return 0; 1186 } 1187 1188 static const struct of_device_id mcde_dsi_of_match[] = { 1189 { 1190 .compatible = "ste,mcde-dsi", 1191 }, 1192 {}, 1193 }; 1194 1195 struct platform_driver mcde_dsi_driver = { 1196 .driver = { 1197 .name = "mcde-dsi", 1198 .of_match_table = of_match_ptr(mcde_dsi_of_match), 1199 }, 1200 .probe = mcde_dsi_probe, 1201 .remove = mcde_dsi_remove, 1202 }; 1203