15fc537bfSLinus Walleij // SPDX-License-Identifier: GPL-2.0+ 25fc537bfSLinus Walleij #include <linux/clk.h> 35fc537bfSLinus Walleij #include <linux/component.h> 45fc537bfSLinus Walleij #include <linux/delay.h> 55fc537bfSLinus Walleij #include <linux/io.h> 65fc537bfSLinus Walleij #include <linux/mfd/syscon.h> 75fc537bfSLinus Walleij #include <linux/module.h> 85fc537bfSLinus Walleij #include <linux/of.h> 95fc537bfSLinus Walleij #include <linux/platform_device.h> 105fc537bfSLinus Walleij #include <linux/regmap.h> 115fc537bfSLinus Walleij #include <linux/regulator/consumer.h> 125fc537bfSLinus Walleij #include <video/mipi_display.h> 135fc537bfSLinus Walleij 145fc537bfSLinus Walleij #include <drm/drm_atomic_helper.h> 155fc537bfSLinus Walleij #include <drm/drm_bridge.h> 165fc537bfSLinus Walleij #include <drm/drm_device.h> 175fc537bfSLinus Walleij #include <drm/drm_drv.h> 185fc537bfSLinus Walleij #include <drm/drm_encoder.h> 195fc537bfSLinus Walleij #include <drm/drm_mipi_dsi.h> 205fc537bfSLinus Walleij #include <drm/drm_modeset_helper_vtables.h> 215fc537bfSLinus Walleij #include <drm/drm_of.h> 225fc537bfSLinus Walleij #include <drm/drm_panel.h> 235fc537bfSLinus Walleij #include <drm/drm_print.h> 245fc537bfSLinus Walleij #include <drm/drm_probe_helper.h> 255fc537bfSLinus Walleij 265fc537bfSLinus Walleij #include "mcde_drm.h" 275fc537bfSLinus Walleij #include "mcde_dsi_regs.h" 285fc537bfSLinus Walleij 295fc537bfSLinus Walleij #define DSI_DEFAULT_LP_FREQ_HZ 19200000 305fc537bfSLinus Walleij #define DSI_DEFAULT_HS_FREQ_HZ 420160000 315fc537bfSLinus Walleij 325fc537bfSLinus Walleij /* PRCMU DSI reset registers */ 335fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET 0x324 345fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) 355fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) 365fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) 375fc537bfSLinus Walleij 385fc537bfSLinus Walleij struct mcde_dsi { 395fc537bfSLinus Walleij struct device *dev; 405fc537bfSLinus Walleij struct mcde *mcde; 415fc537bfSLinus Walleij struct drm_bridge bridge; 425fc537bfSLinus Walleij struct drm_panel *panel; 435fc537bfSLinus Walleij struct drm_bridge *bridge_out; 445fc537bfSLinus Walleij struct mipi_dsi_host dsi_host; 455fc537bfSLinus Walleij struct mipi_dsi_device *mdsi; 46c4842d4dSLinus Walleij const struct drm_display_mode *mode; 475fc537bfSLinus Walleij struct clk *hs_clk; 485fc537bfSLinus Walleij struct clk *lp_clk; 495fc537bfSLinus Walleij unsigned long hs_freq; 505fc537bfSLinus Walleij unsigned long lp_freq; 515fc537bfSLinus Walleij bool unused; 525fc537bfSLinus Walleij 535fc537bfSLinus Walleij void __iomem *regs; 545fc537bfSLinus Walleij struct regmap *prcmu; 555fc537bfSLinus Walleij }; 565fc537bfSLinus Walleij 575fc537bfSLinus Walleij static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge) 585fc537bfSLinus Walleij { 595fc537bfSLinus Walleij return container_of(bridge, struct mcde_dsi, bridge); 605fc537bfSLinus Walleij } 615fc537bfSLinus Walleij 625fc537bfSLinus Walleij static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h) 635fc537bfSLinus Walleij { 645fc537bfSLinus Walleij return container_of(h, struct mcde_dsi, dsi_host); 655fc537bfSLinus Walleij } 665fc537bfSLinus Walleij 675fc537bfSLinus Walleij bool mcde_dsi_irq(struct mipi_dsi_device *mdsi) 685fc537bfSLinus Walleij { 695fc537bfSLinus Walleij struct mcde_dsi *d; 705fc537bfSLinus Walleij u32 val; 715fc537bfSLinus Walleij bool te_received = false; 725fc537bfSLinus Walleij 735fc537bfSLinus Walleij d = host_to_mcde_dsi(mdsi->host); 745fc537bfSLinus Walleij 755fc537bfSLinus Walleij dev_dbg(d->dev, "%s called\n", __func__); 765fc537bfSLinus Walleij 775fc537bfSLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); 785fc537bfSLinus Walleij if (val) 795fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); 805fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 815fc537bfSLinus Walleij dev_dbg(d->dev, "direct command write completed\n"); 825fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) { 835fc537bfSLinus Walleij te_received = true; 845fc537bfSLinus Walleij dev_dbg(d->dev, "direct command TE received\n"); 855fc537bfSLinus Walleij } 865fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) 875fc537bfSLinus Walleij dev_err(d->dev, "direct command ACK ERR received\n"); 885fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) 895fc537bfSLinus Walleij dev_err(d->dev, "direct command read ERR received\n"); 905fc537bfSLinus Walleij /* Mask off the ACK value and clear status */ 915fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR); 925fc537bfSLinus Walleij 935fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_STS_FLAG); 945fc537bfSLinus Walleij if (val) 955fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val); 965fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_NO_TE) 975fc537bfSLinus Walleij /* This happens all the time (safe to ignore) */ 985fc537bfSLinus Walleij dev_dbg(d->dev, "CMD mode no TE\n"); 995fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_TE_MISS) 1005fc537bfSLinus Walleij /* This happens all the time (safe to ignore) */ 1015fc537bfSLinus Walleij dev_dbg(d->dev, "CMD mode TE miss\n"); 1025fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN) 1035fc537bfSLinus Walleij dev_err(d->dev, "CMD mode SD1 underrun\n"); 1045fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN) 1055fc537bfSLinus Walleij dev_err(d->dev, "CMD mode SD2 underrun\n"); 1065fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD) 1075fc537bfSLinus Walleij dev_err(d->dev, "CMD mode unwanted RD\n"); 1085fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_STS_CLR); 1095fc537bfSLinus Walleij 1105fc537bfSLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG); 1115fc537bfSLinus Walleij if (val) 1125fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val); 1135fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR); 1145fc537bfSLinus Walleij 1155fc537bfSLinus Walleij val = readl(d->regs + DSI_TG_STS_FLAG); 1165fc537bfSLinus Walleij if (val) 1175fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val); 1185fc537bfSLinus Walleij writel(val, d->regs + DSI_TG_STS_CLR); 1195fc537bfSLinus Walleij 1205fc537bfSLinus Walleij val = readl(d->regs + DSI_VID_MODE_STS_FLAG); 1215fc537bfSLinus Walleij if (val) 12257efea87SStephan Gerhold dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val); 12357efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_VSG_RUNNING) 12457efea87SStephan Gerhold dev_dbg(d->dev, "VID mode VSG running\n"); 12557efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA) 12657efea87SStephan Gerhold dev_err(d->dev, "VID mode missing data\n"); 12757efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC) 12857efea87SStephan Gerhold dev_err(d->dev, "VID mode missing HSYNC\n"); 12957efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC) 13057efea87SStephan Gerhold dev_err(d->dev, "VID mode missing VSYNC\n"); 13157efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH) 13257efea87SStephan Gerhold dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n"); 13357efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT) 13457efea87SStephan Gerhold dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n"); 13557efea87SStephan Gerhold if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE | 13657efea87SStephan Gerhold DSI_VID_MODE_STS_ERR_LINEWRITE | 13757efea87SStephan Gerhold DSI_VID_MODE_STS_ERR_LONGREAD)) 13857efea87SStephan Gerhold dev_err(d->dev, "VID mode read/write error\n"); 13957efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH) 14057efea87SStephan Gerhold dev_err(d->dev, "VID mode received packets differ from expected size\n"); 14157efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_VSG_RECOVERY) 14257efea87SStephan Gerhold dev_err(d->dev, "VID mode VSG in recovery mode\n"); 1435fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_MODE_STS_CLR); 1445fc537bfSLinus Walleij 1455fc537bfSLinus Walleij return te_received; 1465fc537bfSLinus Walleij } 1475fc537bfSLinus Walleij 148d920e8daSStephan Gerhold static void mcde_dsi_attach_to_mcde(struct mcde_dsi *d) 149d920e8daSStephan Gerhold { 150d920e8daSStephan Gerhold d->mcde->mdsi = d->mdsi; 151d920e8daSStephan Gerhold 152709c2773SLinus Walleij /* 153709c2773SLinus Walleij * Select the way the DSI data flow is pushing to the display: 154709c2773SLinus Walleij * currently we just support video or command mode depending 155709c2773SLinus Walleij * on the type of display. Video mode defaults to using the 156709c2773SLinus Walleij * formatter itself for synchronization (stateless video panel). 157709c2773SLinus Walleij * 158709c2773SLinus Walleij * FIXME: add flags to struct mipi_dsi_device .flags to indicate 159709c2773SLinus Walleij * displays that require BTA (bus turn around) so we can handle 160709c2773SLinus Walleij * such displays as well. Figure out how to properly handle 161709c2773SLinus Walleij * single frame on-demand updates with DRM for command mode 162709c2773SLinus Walleij * displays (MCDE_COMMAND_ONESHOT_FLOW). 163709c2773SLinus Walleij */ 164709c2773SLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) 165709c2773SLinus Walleij d->mcde->flow_mode = MCDE_VIDEO_FORMATTER_FLOW; 166709c2773SLinus Walleij else 167709c2773SLinus Walleij d->mcde->flow_mode = MCDE_COMMAND_TE_FLOW; 168d920e8daSStephan Gerhold } 169d920e8daSStephan Gerhold 1705fc537bfSLinus Walleij static int mcde_dsi_host_attach(struct mipi_dsi_host *host, 1715fc537bfSLinus Walleij struct mipi_dsi_device *mdsi) 1725fc537bfSLinus Walleij { 1735fc537bfSLinus Walleij struct mcde_dsi *d = host_to_mcde_dsi(host); 1745fc537bfSLinus Walleij 1755fc537bfSLinus Walleij if (mdsi->lanes < 1 || mdsi->lanes > 2) { 1765fc537bfSLinus Walleij DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n"); 1775fc537bfSLinus Walleij return -EINVAL; 1785fc537bfSLinus Walleij } 1795fc537bfSLinus Walleij 1805fc537bfSLinus Walleij dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes); 1815fc537bfSLinus Walleij /* MIPI_DSI_FMT_RGB88 etc */ 1825fc537bfSLinus Walleij dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format, 1835fc537bfSLinus Walleij mipi_dsi_pixel_format_to_bpp(mdsi->format)); 1845fc537bfSLinus Walleij dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags); 1855fc537bfSLinus Walleij 1865fc537bfSLinus Walleij d->mdsi = mdsi; 1875fc537bfSLinus Walleij if (d->mcde) 188d920e8daSStephan Gerhold mcde_dsi_attach_to_mcde(d); 1895fc537bfSLinus Walleij 1905fc537bfSLinus Walleij return 0; 1915fc537bfSLinus Walleij } 1925fc537bfSLinus Walleij 1935fc537bfSLinus Walleij static int mcde_dsi_host_detach(struct mipi_dsi_host *host, 1945fc537bfSLinus Walleij struct mipi_dsi_device *mdsi) 1955fc537bfSLinus Walleij { 1965fc537bfSLinus Walleij struct mcde_dsi *d = host_to_mcde_dsi(host); 1975fc537bfSLinus Walleij 1985fc537bfSLinus Walleij d->mdsi = NULL; 1995fc537bfSLinus Walleij if (d->mcde) 2005fc537bfSLinus Walleij d->mcde->mdsi = NULL; 2015fc537bfSLinus Walleij 2025fc537bfSLinus Walleij return 0; 2035fc537bfSLinus Walleij } 2045fc537bfSLinus Walleij 2055fc537bfSLinus Walleij #define MCDE_DSI_HOST_IS_READ(type) \ 2065fc537bfSLinus Walleij ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 2075fc537bfSLinus Walleij (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 2085fc537bfSLinus Walleij (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 2095fc537bfSLinus Walleij (type == MIPI_DSI_DCS_READ)) 2105fc537bfSLinus Walleij 21172957f48SLinus Walleij static int mcde_dsi_execute_transfer(struct mcde_dsi *d, 21272957f48SLinus Walleij const struct mipi_dsi_msg *msg) 21372957f48SLinus Walleij { 21472957f48SLinus Walleij const u32 loop_delay_us = 10; /* us */ 21572957f48SLinus Walleij u32 loop_counter; 21672957f48SLinus Walleij size_t txlen = msg->tx_len; 21772957f48SLinus Walleij size_t rxlen = msg->rx_len; 21872957f48SLinus Walleij int i; 21972957f48SLinus Walleij u32 val; 22072957f48SLinus Walleij int ret; 22172957f48SLinus Walleij 22272957f48SLinus Walleij writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 22372957f48SLinus Walleij writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 22472957f48SLinus Walleij /* Send command */ 22572957f48SLinus Walleij writel(1, d->regs + DSI_DIRECT_CMD_SEND); 22672957f48SLinus Walleij 22772957f48SLinus Walleij loop_counter = 1000 * 1000 / loop_delay_us; 22872957f48SLinus Walleij if (MCDE_DSI_HOST_IS_READ(msg->type)) { 22972957f48SLinus Walleij /* Read command */ 23072957f48SLinus Walleij while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 23172957f48SLinus Walleij (DSI_DIRECT_CMD_STS_READ_COMPLETED | 23272957f48SLinus Walleij DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)) 23372957f48SLinus Walleij && --loop_counter) 23472957f48SLinus Walleij usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 23572957f48SLinus Walleij if (!loop_counter) { 23672957f48SLinus Walleij dev_err(d->dev, "DSI read timeout!\n"); 23772957f48SLinus Walleij /* Set exit code and retry */ 23872957f48SLinus Walleij return -ETIME; 23972957f48SLinus Walleij } 24072957f48SLinus Walleij } else { 24172957f48SLinus Walleij /* Writing only */ 24272957f48SLinus Walleij while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 24372957f48SLinus Walleij DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 24472957f48SLinus Walleij && --loop_counter) 24572957f48SLinus Walleij usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 24672957f48SLinus Walleij 24772957f48SLinus Walleij if (!loop_counter) { 24872957f48SLinus Walleij /* Set exit code and retry */ 24972957f48SLinus Walleij dev_err(d->dev, "DSI write timeout!\n"); 25072957f48SLinus Walleij return -ETIME; 25172957f48SLinus Walleij } 25272957f48SLinus Walleij } 25372957f48SLinus Walleij 25472957f48SLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_STS); 25572957f48SLinus Walleij if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) { 25672957f48SLinus Walleij dev_err(d->dev, "read completed with error\n"); 25772957f48SLinus Walleij writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT); 25872957f48SLinus Walleij return -EIO; 25972957f48SLinus Walleij } 26072957f48SLinus Walleij if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) { 26172957f48SLinus Walleij val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT; 26272957f48SLinus Walleij dev_err(d->dev, "error during transmission: %04x\n", 26372957f48SLinus Walleij val); 26472957f48SLinus Walleij return -EIO; 26572957f48SLinus Walleij } 26672957f48SLinus Walleij 26772957f48SLinus Walleij if (!MCDE_DSI_HOST_IS_READ(msg->type)) { 26872957f48SLinus Walleij /* Return number of bytes written */ 26972957f48SLinus Walleij ret = txlen; 27072957f48SLinus Walleij } else { 27172957f48SLinus Walleij /* OK this is a read command, get the response */ 27272957f48SLinus Walleij u32 rdsz; 27372957f48SLinus Walleij u32 rddat; 27472957f48SLinus Walleij u8 *rx = msg->rx_buf; 27572957f48SLinus Walleij 27672957f48SLinus Walleij rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY); 27772957f48SLinus Walleij rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK; 27872957f48SLinus Walleij rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT); 27972957f48SLinus Walleij if (rdsz < rxlen) { 28072957f48SLinus Walleij dev_err(d->dev, "read error, requested %zd got %d\n", 28172957f48SLinus Walleij rxlen, rdsz); 28272957f48SLinus Walleij return -EIO; 28372957f48SLinus Walleij } 28472957f48SLinus Walleij /* FIXME: read more than 4 bytes */ 28572957f48SLinus Walleij for (i = 0; i < 4 && i < rxlen; i++) 28672957f48SLinus Walleij rx[i] = (rddat >> (i * 8)) & 0xff; 28772957f48SLinus Walleij ret = rdsz; 28872957f48SLinus Walleij } 28972957f48SLinus Walleij 29072957f48SLinus Walleij /* Successful transmission */ 29172957f48SLinus Walleij return ret; 29272957f48SLinus Walleij } 29372957f48SLinus Walleij 2945fc537bfSLinus Walleij static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, 2955fc537bfSLinus Walleij const struct mipi_dsi_msg *msg) 2965fc537bfSLinus Walleij { 2975fc537bfSLinus Walleij struct mcde_dsi *d = host_to_mcde_dsi(host); 2985fc537bfSLinus Walleij const u8 *tx = msg->tx_buf; 29988537ddbSLinus Walleij size_t txlen = msg->tx_len; 30088537ddbSLinus Walleij size_t rxlen = msg->rx_len; 30172957f48SLinus Walleij unsigned int retries = 0; 3025fc537bfSLinus Walleij u32 val; 3035fc537bfSLinus Walleij int ret; 3045fc537bfSLinus Walleij int i; 3055fc537bfSLinus Walleij 30688537ddbSLinus Walleij if (txlen > 16) { 3075fc537bfSLinus Walleij dev_err(d->dev, 30888537ddbSLinus Walleij "dunno how to write more than 16 bytes yet\n"); 30988537ddbSLinus Walleij return -EIO; 31088537ddbSLinus Walleij } 31188537ddbSLinus Walleij if (rxlen > 4) { 31288537ddbSLinus Walleij dev_err(d->dev, 31388537ddbSLinus Walleij "dunno how to read more than 4 bytes yet\n"); 3145fc537bfSLinus Walleij return -EIO; 3155fc537bfSLinus Walleij } 3165fc537bfSLinus Walleij 3175fc537bfSLinus Walleij dev_dbg(d->dev, 31888537ddbSLinus Walleij "message to channel %d, write %zd bytes read %zd bytes\n", 31988537ddbSLinus Walleij msg->channel, txlen, rxlen); 3205fc537bfSLinus Walleij 3215fc537bfSLinus Walleij /* Command "nature" */ 3225fc537bfSLinus Walleij if (MCDE_DSI_HOST_IS_READ(msg->type)) 3235fc537bfSLinus Walleij /* MCTL_MAIN_DATA_CTL already set up */ 3245fc537bfSLinus Walleij val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ; 3255fc537bfSLinus Walleij else 3265fc537bfSLinus Walleij val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE; 3275fc537bfSLinus Walleij /* 3285fc537bfSLinus Walleij * More than 2 bytes will not fit in a single packet, so it's 3295fc537bfSLinus Walleij * time to set the "long not short" bit. One byte is used by 3305fc537bfSLinus Walleij * the MIPI DCS command leaving just one byte for the payload 3315fc537bfSLinus Walleij * in a short package. 3325fc537bfSLinus Walleij */ 3335fc537bfSLinus Walleij if (mipi_dsi_packet_format_is_long(msg->type)) 3345fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT; 3355fc537bfSLinus Walleij val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 33688537ddbSLinus Walleij val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 3375fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 3385fc537bfSLinus Walleij val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 3395fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 3405fc537bfSLinus Walleij 3415fc537bfSLinus Walleij /* MIPI DCS command is part of the data */ 3425fc537bfSLinus Walleij if (txlen > 0) { 3435fc537bfSLinus Walleij val = 0; 3445fc537bfSLinus Walleij for (i = 0; i < 4 && i < txlen; i++) 345b23490cbSLinus Walleij val |= tx[i] << (i * 8); 3465fc537bfSLinus Walleij } 3475fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0); 3485fc537bfSLinus Walleij if (txlen > 4) { 3495fc537bfSLinus Walleij val = 0; 3505fc537bfSLinus Walleij for (i = 0; i < 4 && (i + 4) < txlen; i++) 351b23490cbSLinus Walleij val |= tx[i + 4] << (i * 8); 3525fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1); 3535fc537bfSLinus Walleij } 3545fc537bfSLinus Walleij if (txlen > 8) { 3555fc537bfSLinus Walleij val = 0; 3565fc537bfSLinus Walleij for (i = 0; i < 4 && (i + 8) < txlen; i++) 357b23490cbSLinus Walleij val |= tx[i + 8] << (i * 8); 3585fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2); 3595fc537bfSLinus Walleij } 3605fc537bfSLinus Walleij if (txlen > 12) { 3615fc537bfSLinus Walleij val = 0; 3625fc537bfSLinus Walleij for (i = 0; i < 4 && (i + 12) < txlen; i++) 363b23490cbSLinus Walleij val |= tx[i + 12] << (i * 8); 3645fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3); 3655fc537bfSLinus Walleij } 3665fc537bfSLinus Walleij 36772957f48SLinus Walleij while (retries < 3) { 36872957f48SLinus Walleij ret = mcde_dsi_execute_transfer(d, msg); 36972957f48SLinus Walleij if (ret >= 0) 37072957f48SLinus Walleij break; 37172957f48SLinus Walleij retries++; 37272957f48SLinus Walleij } 37372957f48SLinus Walleij if (ret < 0 && retries) 37472957f48SLinus Walleij dev_err(d->dev, "gave up after %d retries\n", retries); 3755fc537bfSLinus Walleij 37672957f48SLinus Walleij /* Clear any errors */ 3775fc537bfSLinus Walleij writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 3785fc537bfSLinus Walleij writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 3795fc537bfSLinus Walleij 3805fc537bfSLinus Walleij return ret; 3815fc537bfSLinus Walleij } 3825fc537bfSLinus Walleij 3835fc537bfSLinus Walleij static const struct mipi_dsi_host_ops mcde_dsi_host_ops = { 3845fc537bfSLinus Walleij .attach = mcde_dsi_host_attach, 3855fc537bfSLinus Walleij .detach = mcde_dsi_host_detach, 3865fc537bfSLinus Walleij .transfer = mcde_dsi_host_transfer, 3875fc537bfSLinus Walleij }; 3885fc537bfSLinus Walleij 3895fc537bfSLinus Walleij /* This sends a direct (short) command to request TE */ 3905fc537bfSLinus Walleij void mcde_dsi_te_request(struct mipi_dsi_device *mdsi) 3915fc537bfSLinus Walleij { 3925fc537bfSLinus Walleij struct mcde_dsi *d; 3935fc537bfSLinus Walleij u32 val; 3945fc537bfSLinus Walleij 3955fc537bfSLinus Walleij d = host_to_mcde_dsi(mdsi->host); 3965fc537bfSLinus Walleij 3975fc537bfSLinus Walleij /* Command "nature" TE request */ 3985fc537bfSLinus Walleij val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ; 3995fc537bfSLinus Walleij val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 4005fc537bfSLinus Walleij val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 4015fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 402ce9cde04SLinus Walleij val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM << 4035fc537bfSLinus Walleij DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 4045fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 4055fc537bfSLinus Walleij 4065fc537bfSLinus Walleij /* Clear TE reveived and error status bits and enables them */ 4075fc537bfSLinus Walleij writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR | 4085fc537bfSLinus Walleij DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR, 4095fc537bfSLinus Walleij d->regs + DSI_DIRECT_CMD_STS_CLR); 4105fc537bfSLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL); 4115fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN; 4125fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN; 4135fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL); 4145fc537bfSLinus Walleij 4155fc537bfSLinus Walleij /* Clear and enable no TE or TE missing status */ 4165fc537bfSLinus Walleij writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR | 4175fc537bfSLinus Walleij DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR, 4185fc537bfSLinus Walleij d->regs + DSI_CMD_MODE_STS_CLR); 4195fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_STS_CTL); 4205fc537bfSLinus Walleij val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN; 4215fc537bfSLinus Walleij val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN; 4225fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_STS_CTL); 4235fc537bfSLinus Walleij 4245fc537bfSLinus Walleij /* Send this TE request command */ 4255fc537bfSLinus Walleij writel(1, d->regs + DSI_DIRECT_CMD_SEND); 4265fc537bfSLinus Walleij } 4275fc537bfSLinus Walleij 4285fc537bfSLinus Walleij static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, 4295fc537bfSLinus Walleij const struct drm_display_mode *mode) 4305fc537bfSLinus Walleij { 431c8d4a560SLinus Walleij /* cpp, characters per pixel, number of bytes per pixel */ 432c8d4a560SLinus Walleij u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8; 433c8d4a560SLinus Walleij u64 pclk; 4345fc537bfSLinus Walleij u64 bpl; 435c8d4a560SLinus Walleij int hfp; 436c8d4a560SLinus Walleij int hbp; 437c8d4a560SLinus Walleij int hsa; 4385fc537bfSLinus Walleij u32 blkline_pck, line_duration; 4395fc537bfSLinus Walleij u32 val; 4405fc537bfSLinus Walleij 4415fc537bfSLinus Walleij val = 0; 4425fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 4435fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_BURST_MODE; 4445fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 4455fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE; 4465fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL; 4475fc537bfSLinus Walleij } 4485fc537bfSLinus Walleij /* RGB header and pixel mode */ 4495fc537bfSLinus Walleij switch (d->mdsi->format) { 4505fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB565: 4515fc537bfSLinus Walleij val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 << 4525fc537bfSLinus Walleij DSI_VID_MAIN_CTL_HEADER_SHIFT; 4535fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS; 4545fc537bfSLinus Walleij break; 4555fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB666_PACKED: 4565fc537bfSLinus Walleij val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 << 4575fc537bfSLinus Walleij DSI_VID_MAIN_CTL_HEADER_SHIFT; 4585fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS; 4595fc537bfSLinus Walleij break; 4605fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB666: 4615fc537bfSLinus Walleij val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18 4625fc537bfSLinus Walleij << DSI_VID_MAIN_CTL_HEADER_SHIFT; 4635fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE; 4645fc537bfSLinus Walleij break; 4655fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB888: 4665fc537bfSLinus Walleij val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 << 4675fc537bfSLinus Walleij DSI_VID_MAIN_CTL_HEADER_SHIFT; 4685fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS; 4695fc537bfSLinus Walleij break; 4705fc537bfSLinus Walleij default: 4715fc537bfSLinus Walleij dev_err(d->dev, "unknown pixel mode\n"); 4725fc537bfSLinus Walleij return; 4735fc537bfSLinus Walleij } 4745fc537bfSLinus Walleij 475c8d4a560SLinus Walleij /* TODO: TVG (test video generator) could be enabled here */ 4765fc537bfSLinus Walleij 477c8d4a560SLinus Walleij /* 478c8d4a560SLinus Walleij * During vertical blanking: go to LP mode 479c8d4a560SLinus Walleij * Like with the EOL setting, if this is not set, the EOL area will be 480c8d4a560SLinus Walleij * filled with NULL or blanking packets in the vblank area. 481c8d4a560SLinus Walleij * FIXME: some Samsung phones and display panels such as s6e63m0 use 482c8d4a560SLinus Walleij * DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING here instead, 483c8d4a560SLinus Walleij * figure out how to properly configure that from the panel. 484c8d4a560SLinus Walleij */ 4855fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0; 486c8d4a560SLinus Walleij /* 487c8d4a560SLinus Walleij * During EOL: go to LP mode. If this is not set, the EOL area will be 488c8d4a560SLinus Walleij * filled with NULL or blanking packets. 489c8d4a560SLinus Walleij */ 4905fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0; 4915fc537bfSLinus Walleij /* Recovery mode 1 */ 4925fc537bfSLinus Walleij val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT; 4935fc537bfSLinus Walleij /* All other fields zero */ 4945fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_MAIN_CTL); 4955fc537bfSLinus Walleij 4965fc537bfSLinus Walleij /* Vertical frame parameters are pretty straight-forward */ 497c8d4a560SLinus Walleij val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT; 4985fc537bfSLinus Walleij /* vertical front porch */ 4995fc537bfSLinus Walleij val |= (mode->vsync_start - mode->vdisplay) 5005fc537bfSLinus Walleij << DSI_VID_VSIZE_VFP_LENGTH_SHIFT; 5015fc537bfSLinus Walleij /* vertical sync active */ 5025fc537bfSLinus Walleij val |= (mode->vsync_end - mode->vsync_start) 503c8d4a560SLinus Walleij << DSI_VID_VSIZE_VSA_LENGTH_SHIFT; 5045fc537bfSLinus Walleij /* vertical back porch */ 5055fc537bfSLinus Walleij val |= (mode->vtotal - mode->vsync_end) 5065fc537bfSLinus Walleij << DSI_VID_VSIZE_VBP_LENGTH_SHIFT; 5075fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_VSIZE); 5085fc537bfSLinus Walleij 5095fc537bfSLinus Walleij /* 5105fc537bfSLinus Walleij * Horizontal frame parameters: 511c8d4a560SLinus Walleij * horizontal resolution is given in pixels but must be re-calculated 512c8d4a560SLinus Walleij * into bytes since this is what the hardware expects, these registers 513c8d4a560SLinus Walleij * define the payload size of the packet. 514c8d4a560SLinus Walleij * 515c8d4a560SLinus Walleij * hfp = horizontal front porch in bytes 516c8d4a560SLinus Walleij * hbp = horizontal back porch in bytes 517c8d4a560SLinus Walleij * hsa = horizontal sync active in bytes 5185fc537bfSLinus Walleij * 5195fc537bfSLinus Walleij * 6 + 2 is HFP header + checksum 5205fc537bfSLinus Walleij */ 521c8d4a560SLinus Walleij hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2; 5225fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 5235fc537bfSLinus Walleij /* 524c8d4a560SLinus Walleij * Use sync pulse for sync: explicit HSA time 5255fc537bfSLinus Walleij * 6 is HBP header + checksum 5265fc537bfSLinus Walleij * 4 is RGB header + checksum 5275fc537bfSLinus Walleij */ 528c8d4a560SLinus Walleij hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6; 5295fc537bfSLinus Walleij /* 5305fc537bfSLinus Walleij * 6 is HBP header + checksum 5315fc537bfSLinus Walleij * 4 is HSW packet bytes 5325fc537bfSLinus Walleij * 4 is RGB header + checksum 5335fc537bfSLinus Walleij */ 534c8d4a560SLinus Walleij hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6; 5355fc537bfSLinus Walleij } else { 5365fc537bfSLinus Walleij /* 537c8d4a560SLinus Walleij * Use event for sync: HBP includes both back porch and sync 5385fc537bfSLinus Walleij * 6 is HBP header + checksum 5395fc537bfSLinus Walleij * 4 is HSW packet bytes 5405fc537bfSLinus Walleij * 4 is RGB header + checksum 5415fc537bfSLinus Walleij */ 542c8d4a560SLinus Walleij hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6; 543c8d4a560SLinus Walleij /* HSA is not present in this mode and set to 0 */ 5445fc537bfSLinus Walleij hsa = 0; 5455fc537bfSLinus Walleij } 546c8d4a560SLinus Walleij if (hfp < 0) { 547c8d4a560SLinus Walleij dev_info(d->dev, "hfp negative, set to 0\n"); 548c8d4a560SLinus Walleij hfp = 0; 549c8d4a560SLinus Walleij } 550c8d4a560SLinus Walleij if (hbp < 0) { 551c8d4a560SLinus Walleij dev_info(d->dev, "hbp negative, set to 0\n"); 552c8d4a560SLinus Walleij hbp = 0; 553c8d4a560SLinus Walleij } 554c8d4a560SLinus Walleij if (hsa < 0) { 555c8d4a560SLinus Walleij dev_info(d->dev, "hsa negative, set to 0\n"); 556c8d4a560SLinus Walleij hsa = 0; 557c8d4a560SLinus Walleij } 558c8d4a560SLinus Walleij dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n", 5595fc537bfSLinus Walleij hfp, hbp, hsa); 5605fc537bfSLinus Walleij 5615fc537bfSLinus Walleij /* Frame parameters: horizontal sync active */ 5625fc537bfSLinus Walleij val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT; 5635fc537bfSLinus Walleij /* horizontal back porch */ 5645fc537bfSLinus Walleij val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT; 5655fc537bfSLinus Walleij /* horizontal front porch */ 5665fc537bfSLinus Walleij val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT; 5675fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_HSIZE1); 5685fc537bfSLinus Walleij 569c8d4a560SLinus Walleij /* RGB data length (visible bytes on one scanline) */ 570c8d4a560SLinus Walleij val = mode->hdisplay * cpp; 5715fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_HSIZE2); 572c8d4a560SLinus Walleij dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val); 5735fc537bfSLinus Walleij 5745fc537bfSLinus Walleij /* 575c8d4a560SLinus Walleij * Calculate the time between two pixels in picoseconds using 576c8d4a560SLinus Walleij * the supplied refresh rate and total resolution including 577c8d4a560SLinus Walleij * porches and sync. 5785fc537bfSLinus Walleij */ 579c8d4a560SLinus Walleij /* (ps/s) / (pixels/s) = ps/pixels */ 580c8a57044SLinus Walleij pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000)); 581c8d4a560SLinus Walleij dev_dbg(d->dev, "picoseconds between two pixels: %llu\n", 582c8d4a560SLinus Walleij pclk); 583c8d4a560SLinus Walleij 584c8d4a560SLinus Walleij /* 585c8d4a560SLinus Walleij * How many bytes per line will this update frequency yield? 586c8d4a560SLinus Walleij * 587c8d4a560SLinus Walleij * Calculate the number of picoseconds for one scanline (1), then 588c8d4a560SLinus Walleij * divide by 1000000000000 (2) to get in pixels per second we 589c8d4a560SLinus Walleij * want to output. 590c8d4a560SLinus Walleij * 591c8d4a560SLinus Walleij * Multiply with number of bytes per second at this video display 592c8d4a560SLinus Walleij * frequency (3) to get number of bytes transferred during this 593c8d4a560SLinus Walleij * time. Notice that we use the frequency the display wants, 594c8d4a560SLinus Walleij * not what we actually get from the DSI PLL, which is hs_freq. 595c8d4a560SLinus Walleij * 596c8d4a560SLinus Walleij * These arithmetics are done in a different order to avoid 597c8d4a560SLinus Walleij * overflow. 598c8d4a560SLinus Walleij */ 599c8d4a560SLinus Walleij bpl = pclk * mode->htotal; /* (1) picoseconds per line */ 600c8d4a560SLinus Walleij dev_dbg(d->dev, "picoseconds per line: %llu\n", bpl); 601c8d4a560SLinus Walleij /* Multiply with bytes per second (3) */ 602c8d4a560SLinus Walleij bpl *= (d->mdsi->hs_rate / 8); 603c8d4a560SLinus Walleij /* Pixels per second (2) */ 604c8d4a560SLinus Walleij bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* microseconds */ 605c8d4a560SLinus Walleij bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* seconds */ 606c8d4a560SLinus Walleij /* parallel transactions in all lanes */ 6075fc537bfSLinus Walleij bpl *= d->mdsi->lanes; 608c8d4a560SLinus Walleij dev_dbg(d->dev, 609c8d4a560SLinus Walleij "calculated bytes per line: %llu @ %d Hz with HS %lu Hz\n", 6100425662fSVille Syrjälä bpl, drm_mode_vrefresh(mode), d->mdsi->hs_rate); 611c8d4a560SLinus Walleij 6125fc537bfSLinus Walleij /* 6135fc537bfSLinus Walleij * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes 6145fc537bfSLinus Walleij * 4 is short packet for vsync/hsync 6155fc537bfSLinus Walleij */ 6165fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 617c8d4a560SLinus Walleij /* Set the event packet size to 0 (not used) */ 618c8d4a560SLinus Walleij writel(0, d->regs + DSI_VID_BLKSIZE1); 619c8d4a560SLinus Walleij /* 620c8d4a560SLinus Walleij * FIXME: isn't the hsync width in pixels? The porch and 621c8d4a560SLinus Walleij * sync area size is in pixels here, but this -6 622c8d4a560SLinus Walleij * seems to be for bytes. It looks like this in the vendor 623c8d4a560SLinus Walleij * code though. Is it completely untested? 624c8d4a560SLinus Walleij */ 6255fc537bfSLinus Walleij blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6; 6265fc537bfSLinus Walleij val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT; 6275fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_BLKSIZE2); 6285fc537bfSLinus Walleij } else { 629c8d4a560SLinus Walleij /* Set the sync pulse packet size to 0 (not used) */ 630c8d4a560SLinus Walleij writel(0, d->regs + DSI_VID_BLKSIZE2); 631c8d4a560SLinus Walleij /* Specifying payload size in bytes (-4-6 from manual) */ 6325fc537bfSLinus Walleij blkline_pck = bpl - 4 - 6; 633c8d4a560SLinus Walleij if (blkline_pck > 0x1FFF) 634c8d4a560SLinus Walleij dev_err(d->dev, "blkline_pck too big %d bytes\n", 635c8d4a560SLinus Walleij blkline_pck); 6365fc537bfSLinus Walleij val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT; 637c8d4a560SLinus Walleij val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK; 6385fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_BLKSIZE1); 6395fc537bfSLinus Walleij } 6405fc537bfSLinus Walleij 641c8d4a560SLinus Walleij /* 642c8d4a560SLinus Walleij * The line duration is used to scale back the frequency from 643c8d4a560SLinus Walleij * the max frequency supported by the HS clock to the desired 644c8d4a560SLinus Walleij * update frequency in vrefresh. 645c8d4a560SLinus Walleij */ 646c8d4a560SLinus Walleij line_duration = blkline_pck + 6; 647c8d4a560SLinus Walleij /* 648c8d4a560SLinus Walleij * The datasheet contains this complex condition to decreasing 649c8d4a560SLinus Walleij * the line duration by 1 under very specific circumstances. 650c8d4a560SLinus Walleij * Here we also imply that LP is used during burst EOL. 651c8d4a560SLinus Walleij */ 652c8d4a560SLinus Walleij if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01) 653c8d4a560SLinus Walleij && (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) 654c8d4a560SLinus Walleij line_duration--; 655c8d4a560SLinus Walleij line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes); 656c8d4a560SLinus Walleij dev_dbg(d->dev, "line duration %u bytes\n", line_duration); 6575fc537bfSLinus Walleij val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT; 6585fc537bfSLinus Walleij /* 6595fc537bfSLinus Walleij * This is the time to perform LP->HS on D-PHY 6605fc537bfSLinus Walleij * FIXME: nowhere to get this from: DT property on the DSI? 661c8d4a560SLinus Walleij * The manual says this is "system dependent". 662c8d4a560SLinus Walleij * values like 48 and 72 seen in the vendor code. 6635fc537bfSLinus Walleij */ 664c8d4a560SLinus Walleij val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT; 6655fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_DPHY_TIME); 6665fc537bfSLinus Walleij 667c8d4a560SLinus Walleij /* 668c8d4a560SLinus Walleij * See the manual figure 657 page 2203 for understanding the impact 669c8d4a560SLinus Walleij * of the different burst mode settings. 670c8d4a560SLinus Walleij */ 6715fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 672c8d4a560SLinus Walleij int blkeol_pck, blkeol_duration; 673c8d4a560SLinus Walleij /* 674c8d4a560SLinus Walleij * Packet size at EOL for burst mode, this is only used 675c8d4a560SLinus Walleij * if DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is NOT set, 676c8d4a560SLinus Walleij * but we instead send NULL or blanking packets at EOL. 677c8d4a560SLinus Walleij * This is given in number of bytes. 678c8d4a560SLinus Walleij * 679c8d4a560SLinus Walleij * See the manual page 2198 for the 13 reg_blkeol_pck bits. 680c8d4a560SLinus Walleij */ 681c8d4a560SLinus Walleij blkeol_pck = bpl - (mode->htotal * cpp) - 6; 682c8d4a560SLinus Walleij if (blkeol_pck < 0) { 683c8d4a560SLinus Walleij dev_err(d->dev, "video block does not fit on line!\n"); 684c8d4a560SLinus Walleij dev_err(d->dev, 685c8d4a560SLinus Walleij "calculated bytes per line: %llu @ %d Hz\n", 6860425662fSVille Syrjälä bpl, drm_mode_vrefresh(mode)); 687c8d4a560SLinus Walleij dev_err(d->dev, 688c8d4a560SLinus Walleij "bytes per line (blkline_pck) %u bytes\n", 689c8d4a560SLinus Walleij blkline_pck); 690c8d4a560SLinus Walleij dev_err(d->dev, 691c8d4a560SLinus Walleij "blkeol_pck becomes %d bytes\n", blkeol_pck); 692c8d4a560SLinus Walleij return; 693c8d4a560SLinus Walleij } 694c8d4a560SLinus Walleij dev_dbg(d->dev, "BLKEOL packet: %d bytes\n", blkeol_pck); 695c8d4a560SLinus Walleij 6965fc537bfSLinus Walleij val = readl(d->regs + DSI_VID_BLKSIZE1); 697c8d4a560SLinus Walleij val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK; 6985fc537bfSLinus Walleij val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT; 6995fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_BLKSIZE1); 700c8d4a560SLinus Walleij /* Use the same value for exact burst limit */ 701c8d4a560SLinus Walleij val = blkeol_pck << 702c8d4a560SLinus Walleij DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT; 703c8d4a560SLinus Walleij val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK; 704c8d4a560SLinus Walleij writel(val, d->regs + DSI_VID_VCA_SETTING2); 705c8d4a560SLinus Walleij /* 706c8d4a560SLinus Walleij * This BLKEOL duration is claimed to be the duration in clock 707c8d4a560SLinus Walleij * cycles of the BLLP end-of-line (EOL) period for each line if 708c8d4a560SLinus Walleij * DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is set. 709c8d4a560SLinus Walleij * 710c8d4a560SLinus Walleij * It is hard to trust the manuals' claim that this is in clock 711c8d4a560SLinus Walleij * cycles as we mimic the behaviour of the vendor code, which 712c8d4a560SLinus Walleij * appears to write a number of bytes that would have been 713c8d4a560SLinus Walleij * transferred on a single lane. 714c8d4a560SLinus Walleij * 715c8d4a560SLinus Walleij * See the manual figure 657 page 2203 and page 2198 for the 13 716c8d4a560SLinus Walleij * reg_blkeol_duration bits. 717c8d4a560SLinus Walleij * 718c8d4a560SLinus Walleij * FIXME: should this also be set up also for non-burst mode 719c8d4a560SLinus Walleij * according to figure 565 page 2202? 720c8d4a560SLinus Walleij */ 721c8d4a560SLinus Walleij blkeol_duration = DIV_ROUND_CLOSEST(blkeol_pck + 6, 722c8d4a560SLinus Walleij d->mdsi->lanes); 723c8d4a560SLinus Walleij dev_dbg(d->dev, "BLKEOL duration: %d clock cycles\n", 724c8d4a560SLinus Walleij blkeol_duration); 7255fc537bfSLinus Walleij 726c8d4a560SLinus Walleij val = readl(d->regs + DSI_VID_PCK_TIME); 727c8d4a560SLinus Walleij val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK; 728c8d4a560SLinus Walleij val |= blkeol_duration << 729c8d4a560SLinus Walleij DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT; 730c8d4a560SLinus Walleij writel(val, d->regs + DSI_VID_PCK_TIME); 731c8d4a560SLinus Walleij 732c8d4a560SLinus Walleij /* Max burst limit, this is given in bytes */ 733c8d4a560SLinus Walleij val = readl(d->regs + DSI_VID_VCA_SETTING1); 734c8d4a560SLinus Walleij val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK; 735c8d4a560SLinus Walleij val |= (blkeol_pck - 6) << 736c8d4a560SLinus Walleij DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT; 737c8d4a560SLinus Walleij writel(val, d->regs + DSI_VID_VCA_SETTING1); 7385fc537bfSLinus Walleij } 7395fc537bfSLinus Walleij 7405fc537bfSLinus Walleij /* Maximum line limit */ 7415fc537bfSLinus Walleij val = readl(d->regs + DSI_VID_VCA_SETTING2); 742c8d4a560SLinus Walleij val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK; 743c8d4a560SLinus Walleij val |= (blkline_pck - 6) << 744c8d4a560SLinus Walleij DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT; 7455fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_VCA_SETTING2); 746c8d4a560SLinus Walleij dev_dbg(d->dev, "blkline pck: %d bytes\n", blkline_pck - 6); 7475fc537bfSLinus Walleij } 7485fc537bfSLinus Walleij 7495fc537bfSLinus Walleij static void mcde_dsi_start(struct mcde_dsi *d) 7505fc537bfSLinus Walleij { 7515fc537bfSLinus Walleij unsigned long hs_freq; 7525fc537bfSLinus Walleij u32 val; 7535fc537bfSLinus Walleij int i; 7545fc537bfSLinus Walleij 7555fc537bfSLinus Walleij /* No integration mode */ 7565fc537bfSLinus Walleij writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE); 7575fc537bfSLinus Walleij 7585fc537bfSLinus Walleij /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */ 7595fc537bfSLinus Walleij val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN | 7605fc537bfSLinus Walleij DSI_MCTL_MAIN_DATA_CTL_BTA_EN | 7615fc537bfSLinus Walleij DSI_MCTL_MAIN_DATA_CTL_READ_EN | 7625fc537bfSLinus Walleij DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN; 763d0c5ac04SLinus Walleij if (!(d->mdsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 7645fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN; 7655fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 7665fc537bfSLinus Walleij 7675fc537bfSLinus Walleij /* Set a high command timeout, clear other fields */ 7685fc537bfSLinus Walleij val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT; 7695fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_CTL); 7705fc537bfSLinus Walleij 7715fc537bfSLinus Walleij /* 7725fc537bfSLinus Walleij * UI_X4 is described as "unit interval times four" 7735fc537bfSLinus Walleij * I guess since DSI packets are 4 bytes wide, one unit 7745fc537bfSLinus Walleij * is one byte. 7755fc537bfSLinus Walleij */ 7765fc537bfSLinus Walleij hs_freq = clk_get_rate(d->hs_clk); 7775fc537bfSLinus Walleij hs_freq /= 1000000; /* MHz */ 7785fc537bfSLinus Walleij val = 4000 / hs_freq; 7795fc537bfSLinus Walleij dev_dbg(d->dev, "UI value: %d\n", val); 7805fc537bfSLinus Walleij val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT; 7815fc537bfSLinus Walleij val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK; 7825fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_DPHY_STATIC); 7835fc537bfSLinus Walleij 7845fc537bfSLinus Walleij /* 7855fc537bfSLinus Walleij * Enable clocking: 0x0f (something?) between each burst, 7865fc537bfSLinus Walleij * enable the second lane if needed, enable continuous clock if 7875fc537bfSLinus Walleij * needed, enable switch into ULPM (ultra-low power mode) on 7885fc537bfSLinus Walleij * all the lines. 7895fc537bfSLinus Walleij */ 7905fc537bfSLinus Walleij val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT; 7915fc537bfSLinus Walleij if (d->mdsi->lanes == 2) 7925fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN; 7935fc537bfSLinus Walleij if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 7945fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS; 7955fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN | 7965fc537bfSLinus Walleij DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN | 7975fc537bfSLinus Walleij DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN; 7985fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL); 7995fc537bfSLinus Walleij 8005fc537bfSLinus Walleij val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) | 8015fc537bfSLinus Walleij (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT); 8025fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_ULPOUT_TIME); 8035fc537bfSLinus Walleij 8045fc537bfSLinus Walleij writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90, 8055fc537bfSLinus Walleij d->regs + DSI_DPHY_LANES_TRIM); 8065fc537bfSLinus Walleij 8075fc537bfSLinus Walleij /* High PHY timeout */ 8085fc537bfSLinus Walleij val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) | 8095fc537bfSLinus Walleij (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) | 8105fc537bfSLinus Walleij (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT); 8115fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT); 8125fc537bfSLinus Walleij 8135fc537bfSLinus Walleij val = DSI_MCTL_MAIN_EN_PLL_START | 8145fc537bfSLinus Walleij DSI_MCTL_MAIN_EN_CKLANE_EN | 8155fc537bfSLinus Walleij DSI_MCTL_MAIN_EN_DAT1_EN | 8165fc537bfSLinus Walleij DSI_MCTL_MAIN_EN_IF1_EN; 8175fc537bfSLinus Walleij if (d->mdsi->lanes == 2) 8185fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_EN_DAT2_EN; 8195fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_EN); 8205fc537bfSLinus Walleij 8215fc537bfSLinus Walleij /* Wait for the PLL to lock and the clock and data lines to come up */ 8225fc537bfSLinus Walleij i = 0; 8235fc537bfSLinus Walleij val = DSI_MCTL_MAIN_STS_PLL_LOCK | 8245fc537bfSLinus Walleij DSI_MCTL_MAIN_STS_CLKLANE_READY | 8255fc537bfSLinus Walleij DSI_MCTL_MAIN_STS_DAT1_READY; 8265fc537bfSLinus Walleij if (d->mdsi->lanes == 2) 8275fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_STS_DAT2_READY; 8285fc537bfSLinus Walleij while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) { 8295fc537bfSLinus Walleij /* Sleep for a millisecond */ 8305fc537bfSLinus Walleij usleep_range(1000, 1500); 8315fc537bfSLinus Walleij if (i++ == 100) { 8325fc537bfSLinus Walleij dev_warn(d->dev, "DSI lanes did not start up\n"); 8335fc537bfSLinus Walleij return; 8345fc537bfSLinus Walleij } 8355fc537bfSLinus Walleij } 8365fc537bfSLinus Walleij 8375fc537bfSLinus Walleij /* TODO needed? */ 8385fc537bfSLinus Walleij 8395fc537bfSLinus Walleij /* Command mode, clear IF1 ID */ 8405fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_CTL); 8415fc537bfSLinus Walleij /* 842f6fd1d70SLinus Walleij * If we enable low-power mode here, 8435fc537bfSLinus Walleij * then display updates become really slow. 8445fc537bfSLinus Walleij */ 845f6fd1d70SLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM) 846f6fd1d70SLinus Walleij val |= DSI_CMD_MODE_CTL_IF1_LP_EN; 8475fc537bfSLinus Walleij val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 8485fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_CTL); 8495fc537bfSLinus Walleij 8505fc537bfSLinus Walleij /* Wait for DSI PHY to initialize */ 8515fc537bfSLinus Walleij usleep_range(100, 200); 8525fc537bfSLinus Walleij dev_info(d->dev, "DSI link enabled\n"); 8535fc537bfSLinus Walleij } 8545fc537bfSLinus Walleij 85542bac89aSLinus Walleij /* 85642bac89aSLinus Walleij * Notice that this is called from inside the display controller 85742bac89aSLinus Walleij * and not from the bridge callbacks. 85842bac89aSLinus Walleij */ 85942bac89aSLinus Walleij void mcde_dsi_enable(struct drm_bridge *bridge) 8605fc537bfSLinus Walleij { 8615fc537bfSLinus Walleij struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 8625fc537bfSLinus Walleij unsigned long hs_freq, lp_freq; 8635fc537bfSLinus Walleij u32 val; 8645fc537bfSLinus Walleij int ret; 8655fc537bfSLinus Walleij 8665fc537bfSLinus Walleij /* Copy maximum clock frequencies */ 8675fc537bfSLinus Walleij if (d->mdsi->lp_rate) 8685fc537bfSLinus Walleij lp_freq = d->mdsi->lp_rate; 8695fc537bfSLinus Walleij else 8705fc537bfSLinus Walleij lp_freq = DSI_DEFAULT_LP_FREQ_HZ; 8715fc537bfSLinus Walleij if (d->mdsi->hs_rate) 8725fc537bfSLinus Walleij hs_freq = d->mdsi->hs_rate; 8735fc537bfSLinus Walleij else 8745fc537bfSLinus Walleij hs_freq = DSI_DEFAULT_HS_FREQ_HZ; 8755fc537bfSLinus Walleij 8765fc537bfSLinus Walleij /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */ 8775fc537bfSLinus Walleij d->lp_freq = clk_round_rate(d->lp_clk, lp_freq); 8785fc537bfSLinus Walleij ret = clk_set_rate(d->lp_clk, d->lp_freq); 8795fc537bfSLinus Walleij if (ret) 8805fc537bfSLinus Walleij dev_err(d->dev, "failed to set LP clock rate %lu Hz\n", 8815fc537bfSLinus Walleij d->lp_freq); 8825fc537bfSLinus Walleij 8835fc537bfSLinus Walleij d->hs_freq = clk_round_rate(d->hs_clk, hs_freq); 8845fc537bfSLinus Walleij ret = clk_set_rate(d->hs_clk, d->hs_freq); 8855fc537bfSLinus Walleij if (ret) 8865fc537bfSLinus Walleij dev_err(d->dev, "failed to set HS clock rate %lu Hz\n", 8875fc537bfSLinus Walleij d->hs_freq); 8885fc537bfSLinus Walleij 8895fc537bfSLinus Walleij /* Start clocks */ 8905fc537bfSLinus Walleij ret = clk_prepare_enable(d->lp_clk); 8915fc537bfSLinus Walleij if (ret) 8925fc537bfSLinus Walleij dev_err(d->dev, "failed to enable LP clock\n"); 8935fc537bfSLinus Walleij else 8945fc537bfSLinus Walleij dev_info(d->dev, "DSI LP clock rate %lu Hz\n", 8955fc537bfSLinus Walleij d->lp_freq); 8965fc537bfSLinus Walleij ret = clk_prepare_enable(d->hs_clk); 8975fc537bfSLinus Walleij if (ret) 8985fc537bfSLinus Walleij dev_err(d->dev, "failed to enable HS clock\n"); 8995fc537bfSLinus Walleij else 9005fc537bfSLinus Walleij dev_info(d->dev, "DSI HS clock rate %lu Hz\n", 9015fc537bfSLinus Walleij d->hs_freq); 9025fc537bfSLinus Walleij 903c4842d4dSLinus Walleij /* Assert RESET through the PRCMU, active low */ 904c4842d4dSLinus Walleij /* FIXME: which DSI block? */ 905c4842d4dSLinus Walleij regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 906c4842d4dSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 907c4842d4dSLinus Walleij 908c4842d4dSLinus Walleij usleep_range(100, 200); 909c4842d4dSLinus Walleij 910c4842d4dSLinus Walleij /* De-assert RESET again */ 911c4842d4dSLinus Walleij regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 912c4842d4dSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 913c4842d4dSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN); 914c4842d4dSLinus Walleij 915c4842d4dSLinus Walleij /* Start up the hardware */ 916c4842d4dSLinus Walleij mcde_dsi_start(d); 917c4842d4dSLinus Walleij 9185fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 919c4842d4dSLinus Walleij /* Set up the video mode from the DRM mode */ 920c4842d4dSLinus Walleij mcde_dsi_setup_video_mode(d, d->mode); 921c4842d4dSLinus Walleij 9223c5824bdSStephan Gerhold /* Put IF1 into video mode */ 9233c5824bdSStephan Gerhold val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 9243c5824bdSStephan Gerhold val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE; 9253c5824bdSStephan Gerhold writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 9263c5824bdSStephan Gerhold 9273c5824bdSStephan Gerhold /* Disable command mode on IF1 */ 9283c5824bdSStephan Gerhold val = readl(d->regs + DSI_CMD_MODE_CTL); 9293c5824bdSStephan Gerhold val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN; 9303c5824bdSStephan Gerhold writel(val, d->regs + DSI_CMD_MODE_CTL); 9313c5824bdSStephan Gerhold 9323c5824bdSStephan Gerhold /* Enable some error interrupts */ 9333c5824bdSStephan Gerhold val = readl(d->regs + DSI_VID_MODE_STS_CTL); 9343c5824bdSStephan Gerhold val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; 9353c5824bdSStephan Gerhold val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; 9363c5824bdSStephan Gerhold writel(val, d->regs + DSI_VID_MODE_STS_CTL); 93742bac89aSLinus Walleij 93842bac89aSLinus Walleij /* Enable video mode */ 93942bac89aSLinus Walleij val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 94042bac89aSLinus Walleij val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; 94142bac89aSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 9425fc537bfSLinus Walleij } else { 9435fc537bfSLinus Walleij /* Command mode, clear IF1 ID */ 9445fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_CTL); 9455fc537bfSLinus Walleij /* 946f6fd1d70SLinus Walleij * If we enable low-power mode here 9475fc537bfSLinus Walleij * the display updates become really slow. 9485fc537bfSLinus Walleij */ 949f6fd1d70SLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_LPM) 950f6fd1d70SLinus Walleij val |= DSI_CMD_MODE_CTL_IF1_LP_EN; 9515fc537bfSLinus Walleij val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 9525fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_CTL); 9535fc537bfSLinus Walleij } 95442bac89aSLinus Walleij 95542bac89aSLinus Walleij dev_info(d->dev, "enabled MCDE DSI master\n"); 9565fc537bfSLinus Walleij } 9575fc537bfSLinus Walleij 9583c5824bdSStephan Gerhold static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge, 9593c5824bdSStephan Gerhold const struct drm_display_mode *mode, 9603c5824bdSStephan Gerhold const struct drm_display_mode *adj) 9613c5824bdSStephan Gerhold { 9623c5824bdSStephan Gerhold struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 9633c5824bdSStephan Gerhold 9643c5824bdSStephan Gerhold if (!d->mdsi) { 9653c5824bdSStephan Gerhold dev_err(d->dev, "no DSI device attached to encoder!\n"); 9663c5824bdSStephan Gerhold return; 9673c5824bdSStephan Gerhold } 9683c5824bdSStephan Gerhold 969c4842d4dSLinus Walleij d->mode = mode; 970c4842d4dSLinus Walleij 9713c5824bdSStephan Gerhold dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n", 9723c5824bdSStephan Gerhold mode->hdisplay, mode->vdisplay, mode->clock * 1000, 9733c5824bdSStephan Gerhold (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD" 9743c5824bdSStephan Gerhold ); 9753c5824bdSStephan Gerhold } 9763c5824bdSStephan Gerhold 9775fc537bfSLinus Walleij static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d) 9785fc537bfSLinus Walleij { 9795fc537bfSLinus Walleij u32 val; 9805fc537bfSLinus Walleij int i; 9815fc537bfSLinus Walleij 9825fc537bfSLinus Walleij /* 9835fc537bfSLinus Walleij * Wait until we get out of command mode 9845fc537bfSLinus Walleij * CSM = Command State Machine 9855fc537bfSLinus Walleij */ 9865fc537bfSLinus Walleij i = 0; 9875fc537bfSLinus Walleij val = DSI_CMD_MODE_STS_CSM_RUNNING; 9885fc537bfSLinus Walleij while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) { 9895fc537bfSLinus Walleij /* Sleep for a millisecond */ 9905fc537bfSLinus Walleij usleep_range(1000, 2000); 9915fc537bfSLinus Walleij if (i++ == 100) { 9925fc537bfSLinus Walleij dev_warn(d->dev, 9935fc537bfSLinus Walleij "could not get out of command mode\n"); 9945fc537bfSLinus Walleij return; 9955fc537bfSLinus Walleij } 9965fc537bfSLinus Walleij } 9975fc537bfSLinus Walleij } 9985fc537bfSLinus Walleij 9995fc537bfSLinus Walleij static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d) 10005fc537bfSLinus Walleij { 10015fc537bfSLinus Walleij u32 val; 10025fc537bfSLinus Walleij int i; 10035fc537bfSLinus Walleij 10045fc537bfSLinus Walleij /* Wait until we get out og video mode */ 10055fc537bfSLinus Walleij i = 0; 10065fc537bfSLinus Walleij val = DSI_VID_MODE_STS_VSG_RUNNING; 10075fc537bfSLinus Walleij while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) { 10085fc537bfSLinus Walleij /* Sleep for a millisecond */ 10095fc537bfSLinus Walleij usleep_range(1000, 2000); 10105fc537bfSLinus Walleij if (i++ == 100) { 10115fc537bfSLinus Walleij dev_warn(d->dev, 10125fc537bfSLinus Walleij "could not get out of video mode\n"); 10135fc537bfSLinus Walleij return; 10145fc537bfSLinus Walleij } 10155fc537bfSLinus Walleij } 10165fc537bfSLinus Walleij } 10175fc537bfSLinus Walleij 101842bac89aSLinus Walleij /* 101942bac89aSLinus Walleij * Notice that this is called from inside the display controller 102042bac89aSLinus Walleij * and not from the bridge callbacks. 102142bac89aSLinus Walleij */ 102242bac89aSLinus Walleij void mcde_dsi_disable(struct drm_bridge *bridge) 10235fc537bfSLinus Walleij { 10245fc537bfSLinus Walleij struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 10255fc537bfSLinus Walleij u32 val; 10265fc537bfSLinus Walleij 10275fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 10285fc537bfSLinus Walleij /* Stop video mode */ 10295fc537bfSLinus Walleij val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 10305fc537bfSLinus Walleij val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN; 10315fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 10325fc537bfSLinus Walleij mcde_dsi_wait_for_video_mode_stop(d); 10335fc537bfSLinus Walleij } else { 10345fc537bfSLinus Walleij /* Stop command mode */ 10355fc537bfSLinus Walleij mcde_dsi_wait_for_command_mode_stop(d); 10365fc537bfSLinus Walleij } 1037c4842d4dSLinus Walleij 1038c4842d4dSLinus Walleij /* 1039c4842d4dSLinus Walleij * Stop clocks and terminate any DSI traffic here so the panel can 1040c4842d4dSLinus Walleij * send commands to shut down the display using DSI direct write until 1041c4842d4dSLinus Walleij * this point. 1042c4842d4dSLinus Walleij */ 1043c4842d4dSLinus Walleij 1044c4842d4dSLinus Walleij /* Disable all error interrupts */ 1045c4842d4dSLinus Walleij writel(0, d->regs + DSI_VID_MODE_STS_CTL); 10465fc537bfSLinus Walleij clk_disable_unprepare(d->hs_clk); 10475fc537bfSLinus Walleij clk_disable_unprepare(d->lp_clk); 10485fc537bfSLinus Walleij } 10495fc537bfSLinus Walleij 1050a25b988fSLaurent Pinchart static int mcde_dsi_bridge_attach(struct drm_bridge *bridge, 1051a25b988fSLaurent Pinchart enum drm_bridge_attach_flags flags) 10525fc537bfSLinus Walleij { 10535fc537bfSLinus Walleij struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 10545fc537bfSLinus Walleij struct drm_device *drm = bridge->dev; 10555fc537bfSLinus Walleij 10565fc537bfSLinus Walleij if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { 10575fc537bfSLinus Walleij dev_err(d->dev, "we need atomic updates\n"); 10585fc537bfSLinus Walleij return -ENOTSUPP; 10595fc537bfSLinus Walleij } 10605fc537bfSLinus Walleij 10611f79c60eSStephan Gerhold /* Attach the DSI bridge to the output (panel etc) bridge */ 1062*fb8d617fSLaurent Pinchart return drm_bridge_attach(bridge->encoder, d->bridge_out, bridge, flags); 10635fc537bfSLinus Walleij } 10645fc537bfSLinus Walleij 10655fc537bfSLinus Walleij static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = { 10665fc537bfSLinus Walleij .attach = mcde_dsi_bridge_attach, 10675fc537bfSLinus Walleij .mode_set = mcde_dsi_bridge_mode_set, 10685fc537bfSLinus Walleij }; 10695fc537bfSLinus Walleij 10705fc537bfSLinus Walleij static int mcde_dsi_bind(struct device *dev, struct device *master, 10715fc537bfSLinus Walleij void *data) 10725fc537bfSLinus Walleij { 10735fc537bfSLinus Walleij struct drm_device *drm = data; 1074fd7ee85cSDaniel Vetter struct mcde *mcde = to_mcde(drm); 10755fc537bfSLinus Walleij struct mcde_dsi *d = dev_get_drvdata(dev); 10765fc537bfSLinus Walleij struct device_node *child; 10775fc537bfSLinus Walleij struct drm_panel *panel = NULL; 10785fc537bfSLinus Walleij struct drm_bridge *bridge = NULL; 10795fc537bfSLinus Walleij 10805fc537bfSLinus Walleij if (!of_get_available_child_count(dev->of_node)) { 10815fc537bfSLinus Walleij dev_info(dev, "unused DSI interface\n"); 10825fc537bfSLinus Walleij d->unused = true; 10835fc537bfSLinus Walleij return 0; 10845fc537bfSLinus Walleij } 10855fc537bfSLinus Walleij d->mcde = mcde; 10865fc537bfSLinus Walleij /* If the display attached before binding, set this up */ 10875fc537bfSLinus Walleij if (d->mdsi) 1088d920e8daSStephan Gerhold mcde_dsi_attach_to_mcde(d); 10895fc537bfSLinus Walleij 10905fc537bfSLinus Walleij /* Obtain the clocks */ 10915fc537bfSLinus Walleij d->hs_clk = devm_clk_get(dev, "hs"); 10925fc537bfSLinus Walleij if (IS_ERR(d->hs_clk)) { 10935fc537bfSLinus Walleij dev_err(dev, "unable to get HS clock\n"); 10945fc537bfSLinus Walleij return PTR_ERR(d->hs_clk); 10955fc537bfSLinus Walleij } 10965fc537bfSLinus Walleij 10975fc537bfSLinus Walleij d->lp_clk = devm_clk_get(dev, "lp"); 10985fc537bfSLinus Walleij if (IS_ERR(d->lp_clk)) { 10995fc537bfSLinus Walleij dev_err(dev, "unable to get LP clock\n"); 11005fc537bfSLinus Walleij return PTR_ERR(d->lp_clk); 11015fc537bfSLinus Walleij } 11025fc537bfSLinus Walleij 11035fc537bfSLinus Walleij /* Look for a panel as a child to this node */ 11045fc537bfSLinus Walleij for_each_available_child_of_node(dev->of_node, child) { 11055fc537bfSLinus Walleij panel = of_drm_find_panel(child); 11065fc537bfSLinus Walleij if (IS_ERR(panel)) { 1107c131280cSStephan Gerhold dev_err(dev, "failed to find panel try bridge (%ld)\n", 11085fc537bfSLinus Walleij PTR_ERR(panel)); 1109c131280cSStephan Gerhold panel = NULL; 1110c131280cSStephan Gerhold 11115fc537bfSLinus Walleij bridge = of_drm_find_bridge(child); 1112761e9f4fSWei Yongjun if (!bridge) { 1113761e9f4fSWei Yongjun dev_err(dev, "failed to find bridge\n"); 1114761e9f4fSWei Yongjun return -EINVAL; 11155fc537bfSLinus Walleij } 11165fc537bfSLinus Walleij } 11175fc537bfSLinus Walleij } 11185fc537bfSLinus Walleij if (panel) { 111989958b7cSLaurent Pinchart bridge = drm_panel_bridge_add_typed(panel, 11205fc537bfSLinus Walleij DRM_MODE_CONNECTOR_DSI); 11215fc537bfSLinus Walleij if (IS_ERR(bridge)) { 11225fc537bfSLinus Walleij dev_err(dev, "error adding panel bridge\n"); 11235fc537bfSLinus Walleij return PTR_ERR(bridge); 11245fc537bfSLinus Walleij } 11255fc537bfSLinus Walleij dev_info(dev, "connected to panel\n"); 11265fc537bfSLinus Walleij d->panel = panel; 11275fc537bfSLinus Walleij } else if (bridge) { 11285fc537bfSLinus Walleij /* TODO: AV8100 HDMI encoder goes here for example */ 11295fc537bfSLinus Walleij dev_info(dev, "connected to non-panel bridge (unsupported)\n"); 11305fc537bfSLinus Walleij return -ENODEV; 11315fc537bfSLinus Walleij } else { 11325fc537bfSLinus Walleij dev_err(dev, "no panel or bridge\n"); 11335fc537bfSLinus Walleij return -ENODEV; 11345fc537bfSLinus Walleij } 11355fc537bfSLinus Walleij 11365fc537bfSLinus Walleij d->bridge_out = bridge; 11375fc537bfSLinus Walleij 11385fc537bfSLinus Walleij /* Create a bridge for this DSI channel */ 11395fc537bfSLinus Walleij d->bridge.funcs = &mcde_dsi_bridge_funcs; 11405fc537bfSLinus Walleij d->bridge.of_node = dev->of_node; 11415fc537bfSLinus Walleij drm_bridge_add(&d->bridge); 11425fc537bfSLinus Walleij 11435fc537bfSLinus Walleij /* TODO: first come first serve, use a list */ 11445fc537bfSLinus Walleij mcde->bridge = &d->bridge; 11455fc537bfSLinus Walleij 11465fc537bfSLinus Walleij dev_info(dev, "initialized MCDE DSI bridge\n"); 11475fc537bfSLinus Walleij 11485fc537bfSLinus Walleij return 0; 11495fc537bfSLinus Walleij } 11505fc537bfSLinus Walleij 11515fc537bfSLinus Walleij static void mcde_dsi_unbind(struct device *dev, struct device *master, 11525fc537bfSLinus Walleij void *data) 11535fc537bfSLinus Walleij { 11545fc537bfSLinus Walleij struct mcde_dsi *d = dev_get_drvdata(dev); 11555fc537bfSLinus Walleij 11565fc537bfSLinus Walleij if (d->panel) 11575fc537bfSLinus Walleij drm_panel_bridge_remove(d->bridge_out); 11585fc537bfSLinus Walleij regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 11595fc537bfSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 11605fc537bfSLinus Walleij } 11615fc537bfSLinus Walleij 11625fc537bfSLinus Walleij static const struct component_ops mcde_dsi_component_ops = { 11635fc537bfSLinus Walleij .bind = mcde_dsi_bind, 11645fc537bfSLinus Walleij .unbind = mcde_dsi_unbind, 11655fc537bfSLinus Walleij }; 11665fc537bfSLinus Walleij 11675fc537bfSLinus Walleij static int mcde_dsi_probe(struct platform_device *pdev) 11685fc537bfSLinus Walleij { 11695fc537bfSLinus Walleij struct device *dev = &pdev->dev; 11705fc537bfSLinus Walleij struct mcde_dsi *d; 11715fc537bfSLinus Walleij struct mipi_dsi_host *host; 11725fc537bfSLinus Walleij struct resource *res; 11735fc537bfSLinus Walleij u32 dsi_id; 11745fc537bfSLinus Walleij int ret; 11755fc537bfSLinus Walleij 11765fc537bfSLinus Walleij d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 11775fc537bfSLinus Walleij if (!d) 11785fc537bfSLinus Walleij return -ENOMEM; 11795fc537bfSLinus Walleij d->dev = dev; 11805fc537bfSLinus Walleij platform_set_drvdata(pdev, d); 11815fc537bfSLinus Walleij 11825fc537bfSLinus Walleij /* Get a handle on the PRCMU so we can do reset */ 11835fc537bfSLinus Walleij d->prcmu = 11845fc537bfSLinus Walleij syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu"); 11855fc537bfSLinus Walleij if (IS_ERR(d->prcmu)) { 11865fc537bfSLinus Walleij dev_err(dev, "no PRCMU regmap\n"); 11875fc537bfSLinus Walleij return PTR_ERR(d->prcmu); 11885fc537bfSLinus Walleij } 11895fc537bfSLinus Walleij 11905fc537bfSLinus Walleij res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 11915fc537bfSLinus Walleij d->regs = devm_ioremap_resource(dev, res); 11929146bc27SZhen Lei if (IS_ERR(d->regs)) 11935fc537bfSLinus Walleij return PTR_ERR(d->regs); 11945fc537bfSLinus Walleij 11955fc537bfSLinus Walleij dsi_id = readl(d->regs + DSI_ID_REG); 11965fc537bfSLinus Walleij dev_info(dev, "HW revision 0x%08x\n", dsi_id); 11975fc537bfSLinus Walleij 11985fc537bfSLinus Walleij host = &d->dsi_host; 11995fc537bfSLinus Walleij host->dev = dev; 12005fc537bfSLinus Walleij host->ops = &mcde_dsi_host_ops; 12015fc537bfSLinus Walleij ret = mipi_dsi_host_register(host); 12025fc537bfSLinus Walleij if (ret < 0) { 12035fc537bfSLinus Walleij dev_err(dev, "failed to register DSI host: %d\n", ret); 12045fc537bfSLinus Walleij return ret; 12055fc537bfSLinus Walleij } 12065fc537bfSLinus Walleij dev_info(dev, "registered DSI host\n"); 12075fc537bfSLinus Walleij 12085fc537bfSLinus Walleij platform_set_drvdata(pdev, d); 12095fc537bfSLinus Walleij return component_add(dev, &mcde_dsi_component_ops); 12105fc537bfSLinus Walleij } 12115fc537bfSLinus Walleij 12125fc537bfSLinus Walleij static int mcde_dsi_remove(struct platform_device *pdev) 12135fc537bfSLinus Walleij { 12145fc537bfSLinus Walleij struct mcde_dsi *d = platform_get_drvdata(pdev); 12155fc537bfSLinus Walleij 12165fc537bfSLinus Walleij component_del(&pdev->dev, &mcde_dsi_component_ops); 12175fc537bfSLinus Walleij mipi_dsi_host_unregister(&d->dsi_host); 12185fc537bfSLinus Walleij 12195fc537bfSLinus Walleij return 0; 12205fc537bfSLinus Walleij } 12215fc537bfSLinus Walleij 12225fc537bfSLinus Walleij static const struct of_device_id mcde_dsi_of_match[] = { 12235fc537bfSLinus Walleij { 12245fc537bfSLinus Walleij .compatible = "ste,mcde-dsi", 12255fc537bfSLinus Walleij }, 12265fc537bfSLinus Walleij {}, 12275fc537bfSLinus Walleij }; 12285fc537bfSLinus Walleij 12295fc537bfSLinus Walleij struct platform_driver mcde_dsi_driver = { 12305fc537bfSLinus Walleij .driver = { 12315fc537bfSLinus Walleij .name = "mcde-dsi", 12325fc537bfSLinus Walleij .of_match_table = of_match_ptr(mcde_dsi_of_match), 12335fc537bfSLinus Walleij }, 12345fc537bfSLinus Walleij .probe = mcde_dsi_probe, 12355fc537bfSLinus Walleij .remove = mcde_dsi_remove, 12365fc537bfSLinus Walleij }; 1237