15fc537bfSLinus Walleij // SPDX-License-Identifier: GPL-2.0+ 25fc537bfSLinus Walleij #include <linux/clk.h> 35fc537bfSLinus Walleij #include <linux/component.h> 45fc537bfSLinus Walleij #include <linux/delay.h> 55fc537bfSLinus Walleij #include <linux/io.h> 65fc537bfSLinus Walleij #include <linux/mfd/syscon.h> 75fc537bfSLinus Walleij #include <linux/module.h> 85fc537bfSLinus Walleij #include <linux/of.h> 95fc537bfSLinus Walleij #include <linux/platform_device.h> 105fc537bfSLinus Walleij #include <linux/regmap.h> 115fc537bfSLinus Walleij #include <linux/regulator/consumer.h> 125fc537bfSLinus Walleij #include <video/mipi_display.h> 135fc537bfSLinus Walleij 145fc537bfSLinus Walleij #include <drm/drm_atomic_helper.h> 155fc537bfSLinus Walleij #include <drm/drm_bridge.h> 165fc537bfSLinus Walleij #include <drm/drm_device.h> 175fc537bfSLinus Walleij #include <drm/drm_drv.h> 185fc537bfSLinus Walleij #include <drm/drm_encoder.h> 195fc537bfSLinus Walleij #include <drm/drm_mipi_dsi.h> 205fc537bfSLinus Walleij #include <drm/drm_modeset_helper_vtables.h> 215fc537bfSLinus Walleij #include <drm/drm_of.h> 225fc537bfSLinus Walleij #include <drm/drm_panel.h> 235fc537bfSLinus Walleij #include <drm/drm_print.h> 245fc537bfSLinus Walleij #include <drm/drm_probe_helper.h> 255fc537bfSLinus Walleij 265fc537bfSLinus Walleij #include "mcde_drm.h" 275fc537bfSLinus Walleij #include "mcde_dsi_regs.h" 285fc537bfSLinus Walleij 295fc537bfSLinus Walleij #define DSI_DEFAULT_LP_FREQ_HZ 19200000 305fc537bfSLinus Walleij #define DSI_DEFAULT_HS_FREQ_HZ 420160000 315fc537bfSLinus Walleij 325fc537bfSLinus Walleij /* PRCMU DSI reset registers */ 335fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET 0x324 345fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) 355fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) 365fc537bfSLinus Walleij #define PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) 375fc537bfSLinus Walleij 385fc537bfSLinus Walleij struct mcde_dsi { 395fc537bfSLinus Walleij struct device *dev; 405fc537bfSLinus Walleij struct mcde *mcde; 415fc537bfSLinus Walleij struct drm_bridge bridge; 425fc537bfSLinus Walleij struct drm_panel *panel; 435fc537bfSLinus Walleij struct drm_bridge *bridge_out; 445fc537bfSLinus Walleij struct mipi_dsi_host dsi_host; 455fc537bfSLinus Walleij struct mipi_dsi_device *mdsi; 465fc537bfSLinus Walleij struct clk *hs_clk; 475fc537bfSLinus Walleij struct clk *lp_clk; 485fc537bfSLinus Walleij unsigned long hs_freq; 495fc537bfSLinus Walleij unsigned long lp_freq; 505fc537bfSLinus Walleij bool unused; 515fc537bfSLinus Walleij 525fc537bfSLinus Walleij void __iomem *regs; 535fc537bfSLinus Walleij struct regmap *prcmu; 545fc537bfSLinus Walleij }; 555fc537bfSLinus Walleij 565fc537bfSLinus Walleij static inline struct mcde_dsi *bridge_to_mcde_dsi(struct drm_bridge *bridge) 575fc537bfSLinus Walleij { 585fc537bfSLinus Walleij return container_of(bridge, struct mcde_dsi, bridge); 595fc537bfSLinus Walleij } 605fc537bfSLinus Walleij 615fc537bfSLinus Walleij static inline struct mcde_dsi *host_to_mcde_dsi(struct mipi_dsi_host *h) 625fc537bfSLinus Walleij { 635fc537bfSLinus Walleij return container_of(h, struct mcde_dsi, dsi_host); 645fc537bfSLinus Walleij } 655fc537bfSLinus Walleij 665fc537bfSLinus Walleij bool mcde_dsi_irq(struct mipi_dsi_device *mdsi) 675fc537bfSLinus Walleij { 685fc537bfSLinus Walleij struct mcde_dsi *d; 695fc537bfSLinus Walleij u32 val; 705fc537bfSLinus Walleij bool te_received = false; 715fc537bfSLinus Walleij 725fc537bfSLinus Walleij d = host_to_mcde_dsi(mdsi->host); 735fc537bfSLinus Walleij 745fc537bfSLinus Walleij dev_dbg(d->dev, "%s called\n", __func__); 755fc537bfSLinus Walleij 765fc537bfSLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); 775fc537bfSLinus Walleij if (val) 785fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); 795fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 805fc537bfSLinus Walleij dev_dbg(d->dev, "direct command write completed\n"); 815fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) { 825fc537bfSLinus Walleij te_received = true; 835fc537bfSLinus Walleij dev_dbg(d->dev, "direct command TE received\n"); 845fc537bfSLinus Walleij } 855fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) 865fc537bfSLinus Walleij dev_err(d->dev, "direct command ACK ERR received\n"); 875fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) 885fc537bfSLinus Walleij dev_err(d->dev, "direct command read ERR received\n"); 895fc537bfSLinus Walleij /* Mask off the ACK value and clear status */ 905fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR); 915fc537bfSLinus Walleij 925fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_STS_FLAG); 935fc537bfSLinus Walleij if (val) 945fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val); 955fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_NO_TE) 965fc537bfSLinus Walleij /* This happens all the time (safe to ignore) */ 975fc537bfSLinus Walleij dev_dbg(d->dev, "CMD mode no TE\n"); 985fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_TE_MISS) 995fc537bfSLinus Walleij /* This happens all the time (safe to ignore) */ 1005fc537bfSLinus Walleij dev_dbg(d->dev, "CMD mode TE miss\n"); 1015fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN) 1025fc537bfSLinus Walleij dev_err(d->dev, "CMD mode SD1 underrun\n"); 1035fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN) 1045fc537bfSLinus Walleij dev_err(d->dev, "CMD mode SD2 underrun\n"); 1055fc537bfSLinus Walleij if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD) 1065fc537bfSLinus Walleij dev_err(d->dev, "CMD mode unwanted RD\n"); 1075fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_STS_CLR); 1085fc537bfSLinus Walleij 1095fc537bfSLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG); 1105fc537bfSLinus Walleij if (val) 1115fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val); 1125fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR); 1135fc537bfSLinus Walleij 1145fc537bfSLinus Walleij val = readl(d->regs + DSI_TG_STS_FLAG); 1155fc537bfSLinus Walleij if (val) 1165fc537bfSLinus Walleij dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val); 1175fc537bfSLinus Walleij writel(val, d->regs + DSI_TG_STS_CLR); 1185fc537bfSLinus Walleij 1195fc537bfSLinus Walleij val = readl(d->regs + DSI_VID_MODE_STS_FLAG); 1205fc537bfSLinus Walleij if (val) 12157efea87SStephan Gerhold dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val); 12257efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_VSG_RUNNING) 12357efea87SStephan Gerhold dev_dbg(d->dev, "VID mode VSG running\n"); 12457efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA) 12557efea87SStephan Gerhold dev_err(d->dev, "VID mode missing data\n"); 12657efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC) 12757efea87SStephan Gerhold dev_err(d->dev, "VID mode missing HSYNC\n"); 12857efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC) 12957efea87SStephan Gerhold dev_err(d->dev, "VID mode missing VSYNC\n"); 13057efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH) 13157efea87SStephan Gerhold dev_err(d->dev, "VID mode less bytes than expected between two HSYNC\n"); 13257efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT) 13357efea87SStephan Gerhold dev_err(d->dev, "VID mode less lines than expected between two VSYNC\n"); 13457efea87SStephan Gerhold if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE | 13557efea87SStephan Gerhold DSI_VID_MODE_STS_ERR_LINEWRITE | 13657efea87SStephan Gerhold DSI_VID_MODE_STS_ERR_LONGREAD)) 13757efea87SStephan Gerhold dev_err(d->dev, "VID mode read/write error\n"); 13857efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH) 13957efea87SStephan Gerhold dev_err(d->dev, "VID mode received packets differ from expected size\n"); 14057efea87SStephan Gerhold if (val & DSI_VID_MODE_STS_VSG_RECOVERY) 14157efea87SStephan Gerhold dev_err(d->dev, "VID mode VSG in recovery mode\n"); 1425fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_MODE_STS_CLR); 1435fc537bfSLinus Walleij 1445fc537bfSLinus Walleij return te_received; 1455fc537bfSLinus Walleij } 1465fc537bfSLinus Walleij 147d920e8daSStephan Gerhold static void mcde_dsi_attach_to_mcde(struct mcde_dsi *d) 148d920e8daSStephan Gerhold { 149d920e8daSStephan Gerhold d->mcde->mdsi = d->mdsi; 150d920e8daSStephan Gerhold 151709c2773SLinus Walleij /* 152709c2773SLinus Walleij * Select the way the DSI data flow is pushing to the display: 153709c2773SLinus Walleij * currently we just support video or command mode depending 154709c2773SLinus Walleij * on the type of display. Video mode defaults to using the 155709c2773SLinus Walleij * formatter itself for synchronization (stateless video panel). 156709c2773SLinus Walleij * 157709c2773SLinus Walleij * FIXME: add flags to struct mipi_dsi_device .flags to indicate 158709c2773SLinus Walleij * displays that require BTA (bus turn around) so we can handle 159709c2773SLinus Walleij * such displays as well. Figure out how to properly handle 160709c2773SLinus Walleij * single frame on-demand updates with DRM for command mode 161709c2773SLinus Walleij * displays (MCDE_COMMAND_ONESHOT_FLOW). 162709c2773SLinus Walleij */ 163709c2773SLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) 164709c2773SLinus Walleij d->mcde->flow_mode = MCDE_VIDEO_FORMATTER_FLOW; 165709c2773SLinus Walleij else 166709c2773SLinus Walleij d->mcde->flow_mode = MCDE_COMMAND_TE_FLOW; 167d920e8daSStephan Gerhold } 168d920e8daSStephan Gerhold 1695fc537bfSLinus Walleij static int mcde_dsi_host_attach(struct mipi_dsi_host *host, 1705fc537bfSLinus Walleij struct mipi_dsi_device *mdsi) 1715fc537bfSLinus Walleij { 1725fc537bfSLinus Walleij struct mcde_dsi *d = host_to_mcde_dsi(host); 1735fc537bfSLinus Walleij 1745fc537bfSLinus Walleij if (mdsi->lanes < 1 || mdsi->lanes > 2) { 1755fc537bfSLinus Walleij DRM_ERROR("dsi device params invalid, 1 or 2 lanes supported\n"); 1765fc537bfSLinus Walleij return -EINVAL; 1775fc537bfSLinus Walleij } 1785fc537bfSLinus Walleij 1795fc537bfSLinus Walleij dev_info(d->dev, "attached DSI device with %d lanes\n", mdsi->lanes); 1805fc537bfSLinus Walleij /* MIPI_DSI_FMT_RGB88 etc */ 1815fc537bfSLinus Walleij dev_info(d->dev, "format %08x, %dbpp\n", mdsi->format, 1825fc537bfSLinus Walleij mipi_dsi_pixel_format_to_bpp(mdsi->format)); 1835fc537bfSLinus Walleij dev_info(d->dev, "mode flags: %08lx\n", mdsi->mode_flags); 1845fc537bfSLinus Walleij 1855fc537bfSLinus Walleij d->mdsi = mdsi; 1865fc537bfSLinus Walleij if (d->mcde) 187d920e8daSStephan Gerhold mcde_dsi_attach_to_mcde(d); 1885fc537bfSLinus Walleij 1895fc537bfSLinus Walleij return 0; 1905fc537bfSLinus Walleij } 1915fc537bfSLinus Walleij 1925fc537bfSLinus Walleij static int mcde_dsi_host_detach(struct mipi_dsi_host *host, 1935fc537bfSLinus Walleij struct mipi_dsi_device *mdsi) 1945fc537bfSLinus Walleij { 1955fc537bfSLinus Walleij struct mcde_dsi *d = host_to_mcde_dsi(host); 1965fc537bfSLinus Walleij 1975fc537bfSLinus Walleij d->mdsi = NULL; 1985fc537bfSLinus Walleij if (d->mcde) 1995fc537bfSLinus Walleij d->mcde->mdsi = NULL; 2005fc537bfSLinus Walleij 2015fc537bfSLinus Walleij return 0; 2025fc537bfSLinus Walleij } 2035fc537bfSLinus Walleij 2045fc537bfSLinus Walleij #define MCDE_DSI_HOST_IS_READ(type) \ 2055fc537bfSLinus Walleij ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \ 2065fc537bfSLinus Walleij (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \ 2075fc537bfSLinus Walleij (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \ 2085fc537bfSLinus Walleij (type == MIPI_DSI_DCS_READ)) 2095fc537bfSLinus Walleij 2105fc537bfSLinus Walleij static ssize_t mcde_dsi_host_transfer(struct mipi_dsi_host *host, 2115fc537bfSLinus Walleij const struct mipi_dsi_msg *msg) 2125fc537bfSLinus Walleij { 2135fc537bfSLinus Walleij struct mcde_dsi *d = host_to_mcde_dsi(host); 2145fc537bfSLinus Walleij const u32 loop_delay_us = 10; /* us */ 2155fc537bfSLinus Walleij const u8 *tx = msg->tx_buf; 2165fc537bfSLinus Walleij u32 loop_counter; 21788537ddbSLinus Walleij size_t txlen = msg->tx_len; 21888537ddbSLinus Walleij size_t rxlen = msg->rx_len; 2195fc537bfSLinus Walleij u32 val; 2205fc537bfSLinus Walleij int ret; 2215fc537bfSLinus Walleij int i; 2225fc537bfSLinus Walleij 22388537ddbSLinus Walleij if (txlen > 16) { 2245fc537bfSLinus Walleij dev_err(d->dev, 22588537ddbSLinus Walleij "dunno how to write more than 16 bytes yet\n"); 22688537ddbSLinus Walleij return -EIO; 22788537ddbSLinus Walleij } 22888537ddbSLinus Walleij if (rxlen > 4) { 22988537ddbSLinus Walleij dev_err(d->dev, 23088537ddbSLinus Walleij "dunno how to read more than 4 bytes yet\n"); 2315fc537bfSLinus Walleij return -EIO; 2325fc537bfSLinus Walleij } 2335fc537bfSLinus Walleij 2345fc537bfSLinus Walleij dev_dbg(d->dev, 23588537ddbSLinus Walleij "message to channel %d, write %zd bytes read %zd bytes\n", 23688537ddbSLinus Walleij msg->channel, txlen, rxlen); 2375fc537bfSLinus Walleij 2385fc537bfSLinus Walleij /* Command "nature" */ 2395fc537bfSLinus Walleij if (MCDE_DSI_HOST_IS_READ(msg->type)) 2405fc537bfSLinus Walleij /* MCTL_MAIN_DATA_CTL already set up */ 2415fc537bfSLinus Walleij val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ; 2425fc537bfSLinus Walleij else 2435fc537bfSLinus Walleij val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE; 2445fc537bfSLinus Walleij /* 2455fc537bfSLinus Walleij * More than 2 bytes will not fit in a single packet, so it's 2465fc537bfSLinus Walleij * time to set the "long not short" bit. One byte is used by 2475fc537bfSLinus Walleij * the MIPI DCS command leaving just one byte for the payload 2485fc537bfSLinus Walleij * in a short package. 2495fc537bfSLinus Walleij */ 2505fc537bfSLinus Walleij if (mipi_dsi_packet_format_is_long(msg->type)) 2515fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT; 2525fc537bfSLinus Walleij val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 25388537ddbSLinus Walleij val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 2545fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 2555fc537bfSLinus Walleij val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 2565fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 2575fc537bfSLinus Walleij 2585fc537bfSLinus Walleij /* MIPI DCS command is part of the data */ 2595fc537bfSLinus Walleij if (txlen > 0) { 2605fc537bfSLinus Walleij val = 0; 2615fc537bfSLinus Walleij for (i = 0; i < 4 && i < txlen; i++) 262b23490cbSLinus Walleij val |= tx[i] << (i * 8); 2635fc537bfSLinus Walleij } 2645fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0); 2655fc537bfSLinus Walleij if (txlen > 4) { 2665fc537bfSLinus Walleij val = 0; 2675fc537bfSLinus Walleij for (i = 0; i < 4 && (i + 4) < txlen; i++) 268b23490cbSLinus Walleij val |= tx[i + 4] << (i * 8); 2695fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1); 2705fc537bfSLinus Walleij } 2715fc537bfSLinus Walleij if (txlen > 8) { 2725fc537bfSLinus Walleij val = 0; 2735fc537bfSLinus Walleij for (i = 0; i < 4 && (i + 8) < txlen; i++) 274b23490cbSLinus Walleij val |= tx[i + 8] << (i * 8); 2755fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2); 2765fc537bfSLinus Walleij } 2775fc537bfSLinus Walleij if (txlen > 12) { 2785fc537bfSLinus Walleij val = 0; 2795fc537bfSLinus Walleij for (i = 0; i < 4 && (i + 12) < txlen; i++) 280b23490cbSLinus Walleij val |= tx[i + 12] << (i * 8); 2815fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3); 2825fc537bfSLinus Walleij } 2835fc537bfSLinus Walleij 2845fc537bfSLinus Walleij writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 2855fc537bfSLinus Walleij writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 2865fc537bfSLinus Walleij /* Send command */ 2875fc537bfSLinus Walleij writel(1, d->regs + DSI_DIRECT_CMD_SEND); 2885fc537bfSLinus Walleij 2895fc537bfSLinus Walleij loop_counter = 1000 * 1000 / loop_delay_us; 29088537ddbSLinus Walleij if (MCDE_DSI_HOST_IS_READ(msg->type)) { 29188537ddbSLinus Walleij /* Read command */ 29288537ddbSLinus Walleij while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 29388537ddbSLinus Walleij (DSI_DIRECT_CMD_STS_READ_COMPLETED | 29488537ddbSLinus Walleij DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)) 29588537ddbSLinus Walleij && --loop_counter) 29688537ddbSLinus Walleij usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 29788537ddbSLinus Walleij if (!loop_counter) { 29888537ddbSLinus Walleij dev_err(d->dev, "DSI read timeout!\n"); 29988537ddbSLinus Walleij return -ETIME; 30088537ddbSLinus Walleij } 30188537ddbSLinus Walleij } else { 30288537ddbSLinus Walleij /* Writing only */ 3035fc537bfSLinus Walleij while (!(readl(d->regs + DSI_DIRECT_CMD_STS) & 3045fc537bfSLinus Walleij DSI_DIRECT_CMD_STS_WRITE_COMPLETED) 3055fc537bfSLinus Walleij && --loop_counter) 3065fc537bfSLinus Walleij usleep_range(loop_delay_us, (loop_delay_us * 3) / 2); 3075fc537bfSLinus Walleij 3085fc537bfSLinus Walleij if (!loop_counter) { 3095fc537bfSLinus Walleij dev_err(d->dev, "DSI write timeout!\n"); 3105fc537bfSLinus Walleij return -ETIME; 3115fc537bfSLinus Walleij } 31288537ddbSLinus Walleij } 3135fc537bfSLinus Walleij 3145fc537bfSLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_STS); 31588537ddbSLinus Walleij if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) { 31688537ddbSLinus Walleij dev_err(d->dev, "read completed with error\n"); 31788537ddbSLinus Walleij writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT); 31888537ddbSLinus Walleij return -EIO; 31988537ddbSLinus Walleij } 3205fc537bfSLinus Walleij if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) { 3215fc537bfSLinus Walleij val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT; 3225fc537bfSLinus Walleij dev_err(d->dev, "error during transmission: %04x\n", 3235fc537bfSLinus Walleij val); 3245fc537bfSLinus Walleij return -EIO; 3255fc537bfSLinus Walleij } 3265fc537bfSLinus Walleij 3275fc537bfSLinus Walleij if (!MCDE_DSI_HOST_IS_READ(msg->type)) { 3285fc537bfSLinus Walleij /* Return number of bytes written */ 32988537ddbSLinus Walleij ret = txlen; 3305fc537bfSLinus Walleij } else { 3315fc537bfSLinus Walleij /* OK this is a read command, get the response */ 3325fc537bfSLinus Walleij u32 rdsz; 3335fc537bfSLinus Walleij u32 rddat; 3345fc537bfSLinus Walleij u8 *rx = msg->rx_buf; 3355fc537bfSLinus Walleij 3365fc537bfSLinus Walleij rdsz = readl(d->regs + DSI_DIRECT_CMD_RD_PROPERTY); 3375fc537bfSLinus Walleij rdsz &= DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK; 3385fc537bfSLinus Walleij rddat = readl(d->regs + DSI_DIRECT_CMD_RDDAT); 33988537ddbSLinus Walleij if (rdsz < rxlen) { 34088537ddbSLinus Walleij dev_err(d->dev, "read error, requested %zd got %d\n", 34188537ddbSLinus Walleij rxlen, rdsz); 34288537ddbSLinus Walleij return -EIO; 34388537ddbSLinus Walleij } 34488537ddbSLinus Walleij /* FIXME: read more than 4 bytes */ 34588537ddbSLinus Walleij for (i = 0; i < 4 && i < rxlen; i++) 3465fc537bfSLinus Walleij rx[i] = (rddat >> (i * 8)) & 0xff; 3475fc537bfSLinus Walleij ret = rdsz; 3485fc537bfSLinus Walleij } 3495fc537bfSLinus Walleij 3505fc537bfSLinus Walleij writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR); 3515fc537bfSLinus Walleij writel(~0, d->regs + DSI_CMD_MODE_STS_CLR); 3525fc537bfSLinus Walleij 3535fc537bfSLinus Walleij return ret; 3545fc537bfSLinus Walleij } 3555fc537bfSLinus Walleij 3565fc537bfSLinus Walleij static const struct mipi_dsi_host_ops mcde_dsi_host_ops = { 3575fc537bfSLinus Walleij .attach = mcde_dsi_host_attach, 3585fc537bfSLinus Walleij .detach = mcde_dsi_host_detach, 3595fc537bfSLinus Walleij .transfer = mcde_dsi_host_transfer, 3605fc537bfSLinus Walleij }; 3615fc537bfSLinus Walleij 3625fc537bfSLinus Walleij /* This sends a direct (short) command to request TE */ 3635fc537bfSLinus Walleij void mcde_dsi_te_request(struct mipi_dsi_device *mdsi) 3645fc537bfSLinus Walleij { 3655fc537bfSLinus Walleij struct mcde_dsi *d; 3665fc537bfSLinus Walleij u32 val; 3675fc537bfSLinus Walleij 3685fc537bfSLinus Walleij d = host_to_mcde_dsi(mdsi->host); 3695fc537bfSLinus Walleij 3705fc537bfSLinus Walleij /* Command "nature" TE request */ 3715fc537bfSLinus Walleij val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ; 3725fc537bfSLinus Walleij val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; 3735fc537bfSLinus Walleij val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; 3745fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; 375ce9cde04SLinus Walleij val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM << 3765fc537bfSLinus Walleij DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; 3775fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); 3785fc537bfSLinus Walleij 3795fc537bfSLinus Walleij /* Clear TE reveived and error status bits and enables them */ 3805fc537bfSLinus Walleij writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR | 3815fc537bfSLinus Walleij DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR, 3825fc537bfSLinus Walleij d->regs + DSI_DIRECT_CMD_STS_CLR); 3835fc537bfSLinus Walleij val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL); 3845fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN; 3855fc537bfSLinus Walleij val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN; 3865fc537bfSLinus Walleij writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL); 3875fc537bfSLinus Walleij 3885fc537bfSLinus Walleij /* Clear and enable no TE or TE missing status */ 3895fc537bfSLinus Walleij writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR | 3905fc537bfSLinus Walleij DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR, 3915fc537bfSLinus Walleij d->regs + DSI_CMD_MODE_STS_CLR); 3925fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_STS_CTL); 3935fc537bfSLinus Walleij val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN; 3945fc537bfSLinus Walleij val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN; 3955fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_STS_CTL); 3965fc537bfSLinus Walleij 3975fc537bfSLinus Walleij /* Send this TE request command */ 3985fc537bfSLinus Walleij writel(1, d->regs + DSI_DIRECT_CMD_SEND); 3995fc537bfSLinus Walleij } 4005fc537bfSLinus Walleij 4015fc537bfSLinus Walleij static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, 4025fc537bfSLinus Walleij const struct drm_display_mode *mode) 4035fc537bfSLinus Walleij { 404c8d4a560SLinus Walleij /* cpp, characters per pixel, number of bytes per pixel */ 405c8d4a560SLinus Walleij u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8; 406c8d4a560SLinus Walleij u64 pclk; 4075fc537bfSLinus Walleij u64 bpl; 408c8d4a560SLinus Walleij int hfp; 409c8d4a560SLinus Walleij int hbp; 410c8d4a560SLinus Walleij int hsa; 4115fc537bfSLinus Walleij u32 blkline_pck, line_duration; 4125fc537bfSLinus Walleij u32 val; 4135fc537bfSLinus Walleij 4145fc537bfSLinus Walleij val = 0; 4155fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 4165fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_BURST_MODE; 4175fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 4185fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE; 4195fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL; 4205fc537bfSLinus Walleij } 4215fc537bfSLinus Walleij /* RGB header and pixel mode */ 4225fc537bfSLinus Walleij switch (d->mdsi->format) { 4235fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB565: 4245fc537bfSLinus Walleij val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 << 4255fc537bfSLinus Walleij DSI_VID_MAIN_CTL_HEADER_SHIFT; 4265fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS; 4275fc537bfSLinus Walleij break; 4285fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB666_PACKED: 4295fc537bfSLinus Walleij val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 << 4305fc537bfSLinus Walleij DSI_VID_MAIN_CTL_HEADER_SHIFT; 4315fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS; 4325fc537bfSLinus Walleij break; 4335fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB666: 4345fc537bfSLinus Walleij val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18 4355fc537bfSLinus Walleij << DSI_VID_MAIN_CTL_HEADER_SHIFT; 4365fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE; 4375fc537bfSLinus Walleij break; 4385fc537bfSLinus Walleij case MIPI_DSI_FMT_RGB888: 4395fc537bfSLinus Walleij val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 << 4405fc537bfSLinus Walleij DSI_VID_MAIN_CTL_HEADER_SHIFT; 4415fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS; 4425fc537bfSLinus Walleij break; 4435fc537bfSLinus Walleij default: 4445fc537bfSLinus Walleij dev_err(d->dev, "unknown pixel mode\n"); 4455fc537bfSLinus Walleij return; 4465fc537bfSLinus Walleij } 4475fc537bfSLinus Walleij 448c8d4a560SLinus Walleij /* TODO: TVG (test video generator) could be enabled here */ 4495fc537bfSLinus Walleij 450c8d4a560SLinus Walleij /* 451c8d4a560SLinus Walleij * During vertical blanking: go to LP mode 452c8d4a560SLinus Walleij * Like with the EOL setting, if this is not set, the EOL area will be 453c8d4a560SLinus Walleij * filled with NULL or blanking packets in the vblank area. 454c8d4a560SLinus Walleij * FIXME: some Samsung phones and display panels such as s6e63m0 use 455c8d4a560SLinus Walleij * DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING here instead, 456c8d4a560SLinus Walleij * figure out how to properly configure that from the panel. 457c8d4a560SLinus Walleij */ 4585fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0; 459c8d4a560SLinus Walleij /* 460c8d4a560SLinus Walleij * During EOL: go to LP mode. If this is not set, the EOL area will be 461c8d4a560SLinus Walleij * filled with NULL or blanking packets. 462c8d4a560SLinus Walleij */ 4635fc537bfSLinus Walleij val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0; 4645fc537bfSLinus Walleij /* Recovery mode 1 */ 4655fc537bfSLinus Walleij val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT; 4665fc537bfSLinus Walleij /* All other fields zero */ 4675fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_MAIN_CTL); 4685fc537bfSLinus Walleij 4695fc537bfSLinus Walleij /* Vertical frame parameters are pretty straight-forward */ 470c8d4a560SLinus Walleij val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT; 4715fc537bfSLinus Walleij /* vertical front porch */ 4725fc537bfSLinus Walleij val |= (mode->vsync_start - mode->vdisplay) 4735fc537bfSLinus Walleij << DSI_VID_VSIZE_VFP_LENGTH_SHIFT; 4745fc537bfSLinus Walleij /* vertical sync active */ 4755fc537bfSLinus Walleij val |= (mode->vsync_end - mode->vsync_start) 476c8d4a560SLinus Walleij << DSI_VID_VSIZE_VSA_LENGTH_SHIFT; 4775fc537bfSLinus Walleij /* vertical back porch */ 4785fc537bfSLinus Walleij val |= (mode->vtotal - mode->vsync_end) 4795fc537bfSLinus Walleij << DSI_VID_VSIZE_VBP_LENGTH_SHIFT; 4805fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_VSIZE); 4815fc537bfSLinus Walleij 4825fc537bfSLinus Walleij /* 4835fc537bfSLinus Walleij * Horizontal frame parameters: 484c8d4a560SLinus Walleij * horizontal resolution is given in pixels but must be re-calculated 485c8d4a560SLinus Walleij * into bytes since this is what the hardware expects, these registers 486c8d4a560SLinus Walleij * define the payload size of the packet. 487c8d4a560SLinus Walleij * 488c8d4a560SLinus Walleij * hfp = horizontal front porch in bytes 489c8d4a560SLinus Walleij * hbp = horizontal back porch in bytes 490c8d4a560SLinus Walleij * hsa = horizontal sync active in bytes 4915fc537bfSLinus Walleij * 4925fc537bfSLinus Walleij * 6 + 2 is HFP header + checksum 4935fc537bfSLinus Walleij */ 494c8d4a560SLinus Walleij hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2; 4955fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 4965fc537bfSLinus Walleij /* 497c8d4a560SLinus Walleij * Use sync pulse for sync: explicit HSA time 4985fc537bfSLinus Walleij * 6 is HBP header + checksum 4995fc537bfSLinus Walleij * 4 is RGB header + checksum 5005fc537bfSLinus Walleij */ 501c8d4a560SLinus Walleij hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6; 5025fc537bfSLinus Walleij /* 5035fc537bfSLinus Walleij * 6 is HBP header + checksum 5045fc537bfSLinus Walleij * 4 is HSW packet bytes 5055fc537bfSLinus Walleij * 4 is RGB header + checksum 5065fc537bfSLinus Walleij */ 507c8d4a560SLinus Walleij hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6; 5085fc537bfSLinus Walleij } else { 5095fc537bfSLinus Walleij /* 510c8d4a560SLinus Walleij * Use event for sync: HBP includes both back porch and sync 5115fc537bfSLinus Walleij * 6 is HBP header + checksum 5125fc537bfSLinus Walleij * 4 is HSW packet bytes 5135fc537bfSLinus Walleij * 4 is RGB header + checksum 5145fc537bfSLinus Walleij */ 515c8d4a560SLinus Walleij hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6; 516c8d4a560SLinus Walleij /* HSA is not present in this mode and set to 0 */ 5175fc537bfSLinus Walleij hsa = 0; 5185fc537bfSLinus Walleij } 519c8d4a560SLinus Walleij if (hfp < 0) { 520c8d4a560SLinus Walleij dev_info(d->dev, "hfp negative, set to 0\n"); 521c8d4a560SLinus Walleij hfp = 0; 522c8d4a560SLinus Walleij } 523c8d4a560SLinus Walleij if (hbp < 0) { 524c8d4a560SLinus Walleij dev_info(d->dev, "hbp negative, set to 0\n"); 525c8d4a560SLinus Walleij hbp = 0; 526c8d4a560SLinus Walleij } 527c8d4a560SLinus Walleij if (hsa < 0) { 528c8d4a560SLinus Walleij dev_info(d->dev, "hsa negative, set to 0\n"); 529c8d4a560SLinus Walleij hsa = 0; 530c8d4a560SLinus Walleij } 531c8d4a560SLinus Walleij dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n", 5325fc537bfSLinus Walleij hfp, hbp, hsa); 5335fc537bfSLinus Walleij 5345fc537bfSLinus Walleij /* Frame parameters: horizontal sync active */ 5355fc537bfSLinus Walleij val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT; 5365fc537bfSLinus Walleij /* horizontal back porch */ 5375fc537bfSLinus Walleij val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT; 5385fc537bfSLinus Walleij /* horizontal front porch */ 5395fc537bfSLinus Walleij val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT; 5405fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_HSIZE1); 5415fc537bfSLinus Walleij 542c8d4a560SLinus Walleij /* RGB data length (visible bytes on one scanline) */ 543c8d4a560SLinus Walleij val = mode->hdisplay * cpp; 5445fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_HSIZE2); 545c8d4a560SLinus Walleij dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val); 5465fc537bfSLinus Walleij 5475fc537bfSLinus Walleij /* 548c8d4a560SLinus Walleij * Calculate the time between two pixels in picoseconds using 549c8d4a560SLinus Walleij * the supplied refresh rate and total resolution including 550c8d4a560SLinus Walleij * porches and sync. 5515fc537bfSLinus Walleij */ 552c8d4a560SLinus Walleij /* (ps/s) / (pixels/s) = ps/pixels */ 553920dd1b1SVille Syrjälä pclk = DIV_ROUND_UP_ULL(1000000000000, mode->clock); 554c8d4a560SLinus Walleij dev_dbg(d->dev, "picoseconds between two pixels: %llu\n", 555c8d4a560SLinus Walleij pclk); 556c8d4a560SLinus Walleij 557c8d4a560SLinus Walleij /* 558c8d4a560SLinus Walleij * How many bytes per line will this update frequency yield? 559c8d4a560SLinus Walleij * 560c8d4a560SLinus Walleij * Calculate the number of picoseconds for one scanline (1), then 561c8d4a560SLinus Walleij * divide by 1000000000000 (2) to get in pixels per second we 562c8d4a560SLinus Walleij * want to output. 563c8d4a560SLinus Walleij * 564c8d4a560SLinus Walleij * Multiply with number of bytes per second at this video display 565c8d4a560SLinus Walleij * frequency (3) to get number of bytes transferred during this 566c8d4a560SLinus Walleij * time. Notice that we use the frequency the display wants, 567c8d4a560SLinus Walleij * not what we actually get from the DSI PLL, which is hs_freq. 568c8d4a560SLinus Walleij * 569c8d4a560SLinus Walleij * These arithmetics are done in a different order to avoid 570c8d4a560SLinus Walleij * overflow. 571c8d4a560SLinus Walleij */ 572c8d4a560SLinus Walleij bpl = pclk * mode->htotal; /* (1) picoseconds per line */ 573c8d4a560SLinus Walleij dev_dbg(d->dev, "picoseconds per line: %llu\n", bpl); 574c8d4a560SLinus Walleij /* Multiply with bytes per second (3) */ 575c8d4a560SLinus Walleij bpl *= (d->mdsi->hs_rate / 8); 576c8d4a560SLinus Walleij /* Pixels per second (2) */ 577c8d4a560SLinus Walleij bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* microseconds */ 578c8d4a560SLinus Walleij bpl = DIV_ROUND_DOWN_ULL(bpl, 1000000); /* seconds */ 579c8d4a560SLinus Walleij /* parallel transactions in all lanes */ 5805fc537bfSLinus Walleij bpl *= d->mdsi->lanes; 581c8d4a560SLinus Walleij dev_dbg(d->dev, 582c8d4a560SLinus Walleij "calculated bytes per line: %llu @ %d Hz with HS %lu Hz\n", 5830425662fSVille Syrjälä bpl, drm_mode_vrefresh(mode), d->mdsi->hs_rate); 584c8d4a560SLinus Walleij 5855fc537bfSLinus Walleij /* 5865fc537bfSLinus Walleij * 6 is header + checksum, header = 4 bytes, checksum = 2 bytes 5875fc537bfSLinus Walleij * 4 is short packet for vsync/hsync 5885fc537bfSLinus Walleij */ 5895fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 590c8d4a560SLinus Walleij /* Set the event packet size to 0 (not used) */ 591c8d4a560SLinus Walleij writel(0, d->regs + DSI_VID_BLKSIZE1); 592c8d4a560SLinus Walleij /* 593c8d4a560SLinus Walleij * FIXME: isn't the hsync width in pixels? The porch and 594c8d4a560SLinus Walleij * sync area size is in pixels here, but this -6 595c8d4a560SLinus Walleij * seems to be for bytes. It looks like this in the vendor 596c8d4a560SLinus Walleij * code though. Is it completely untested? 597c8d4a560SLinus Walleij */ 5985fc537bfSLinus Walleij blkline_pck = bpl - (mode->hsync_end - mode->hsync_start) - 6; 5995fc537bfSLinus Walleij val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT; 6005fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_BLKSIZE2); 6015fc537bfSLinus Walleij } else { 602c8d4a560SLinus Walleij /* Set the sync pulse packet size to 0 (not used) */ 603c8d4a560SLinus Walleij writel(0, d->regs + DSI_VID_BLKSIZE2); 604c8d4a560SLinus Walleij /* Specifying payload size in bytes (-4-6 from manual) */ 6055fc537bfSLinus Walleij blkline_pck = bpl - 4 - 6; 606c8d4a560SLinus Walleij if (blkline_pck > 0x1FFF) 607c8d4a560SLinus Walleij dev_err(d->dev, "blkline_pck too big %d bytes\n", 608c8d4a560SLinus Walleij blkline_pck); 6095fc537bfSLinus Walleij val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT; 610c8d4a560SLinus Walleij val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK; 6115fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_BLKSIZE1); 6125fc537bfSLinus Walleij } 6135fc537bfSLinus Walleij 614c8d4a560SLinus Walleij /* 615c8d4a560SLinus Walleij * The line duration is used to scale back the frequency from 616c8d4a560SLinus Walleij * the max frequency supported by the HS clock to the desired 617c8d4a560SLinus Walleij * update frequency in vrefresh. 618c8d4a560SLinus Walleij */ 619c8d4a560SLinus Walleij line_duration = blkline_pck + 6; 620c8d4a560SLinus Walleij /* 621c8d4a560SLinus Walleij * The datasheet contains this complex condition to decreasing 622c8d4a560SLinus Walleij * the line duration by 1 under very specific circumstances. 623c8d4a560SLinus Walleij * Here we also imply that LP is used during burst EOL. 624c8d4a560SLinus Walleij */ 625c8d4a560SLinus Walleij if (d->mdsi->lanes == 2 && (hsa & 0x01) && (hfp & 0x01) 626c8d4a560SLinus Walleij && (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) 627c8d4a560SLinus Walleij line_duration--; 628c8d4a560SLinus Walleij line_duration = DIV_ROUND_CLOSEST(line_duration, d->mdsi->lanes); 629c8d4a560SLinus Walleij dev_dbg(d->dev, "line duration %u bytes\n", line_duration); 6305fc537bfSLinus Walleij val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT; 6315fc537bfSLinus Walleij /* 6325fc537bfSLinus Walleij * This is the time to perform LP->HS on D-PHY 6335fc537bfSLinus Walleij * FIXME: nowhere to get this from: DT property on the DSI? 634c8d4a560SLinus Walleij * The manual says this is "system dependent". 635c8d4a560SLinus Walleij * values like 48 and 72 seen in the vendor code. 6365fc537bfSLinus Walleij */ 637c8d4a560SLinus Walleij val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT; 6385fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_DPHY_TIME); 6395fc537bfSLinus Walleij 640c8d4a560SLinus Walleij /* 641c8d4a560SLinus Walleij * See the manual figure 657 page 2203 for understanding the impact 642c8d4a560SLinus Walleij * of the different burst mode settings. 643c8d4a560SLinus Walleij */ 6445fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 645c8d4a560SLinus Walleij int blkeol_pck, blkeol_duration; 646c8d4a560SLinus Walleij /* 647c8d4a560SLinus Walleij * Packet size at EOL for burst mode, this is only used 648c8d4a560SLinus Walleij * if DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is NOT set, 649c8d4a560SLinus Walleij * but we instead send NULL or blanking packets at EOL. 650c8d4a560SLinus Walleij * This is given in number of bytes. 651c8d4a560SLinus Walleij * 652c8d4a560SLinus Walleij * See the manual page 2198 for the 13 reg_blkeol_pck bits. 653c8d4a560SLinus Walleij */ 654c8d4a560SLinus Walleij blkeol_pck = bpl - (mode->htotal * cpp) - 6; 655c8d4a560SLinus Walleij if (blkeol_pck < 0) { 656c8d4a560SLinus Walleij dev_err(d->dev, "video block does not fit on line!\n"); 657c8d4a560SLinus Walleij dev_err(d->dev, 658c8d4a560SLinus Walleij "calculated bytes per line: %llu @ %d Hz\n", 6590425662fSVille Syrjälä bpl, drm_mode_vrefresh(mode)); 660c8d4a560SLinus Walleij dev_err(d->dev, 661c8d4a560SLinus Walleij "bytes per line (blkline_pck) %u bytes\n", 662c8d4a560SLinus Walleij blkline_pck); 663c8d4a560SLinus Walleij dev_err(d->dev, 664c8d4a560SLinus Walleij "blkeol_pck becomes %d bytes\n", blkeol_pck); 665c8d4a560SLinus Walleij return; 666c8d4a560SLinus Walleij } 667c8d4a560SLinus Walleij dev_dbg(d->dev, "BLKEOL packet: %d bytes\n", blkeol_pck); 668c8d4a560SLinus Walleij 6695fc537bfSLinus Walleij val = readl(d->regs + DSI_VID_BLKSIZE1); 670c8d4a560SLinus Walleij val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK; 6715fc537bfSLinus Walleij val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT; 6725fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_BLKSIZE1); 673c8d4a560SLinus Walleij /* Use the same value for exact burst limit */ 674c8d4a560SLinus Walleij val = blkeol_pck << 675c8d4a560SLinus Walleij DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT; 676c8d4a560SLinus Walleij val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK; 677c8d4a560SLinus Walleij writel(val, d->regs + DSI_VID_VCA_SETTING2); 678c8d4a560SLinus Walleij /* 679c8d4a560SLinus Walleij * This BLKEOL duration is claimed to be the duration in clock 680c8d4a560SLinus Walleij * cycles of the BLLP end-of-line (EOL) period for each line if 681c8d4a560SLinus Walleij * DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 is set. 682c8d4a560SLinus Walleij * 683c8d4a560SLinus Walleij * It is hard to trust the manuals' claim that this is in clock 684c8d4a560SLinus Walleij * cycles as we mimic the behaviour of the vendor code, which 685c8d4a560SLinus Walleij * appears to write a number of bytes that would have been 686c8d4a560SLinus Walleij * transferred on a single lane. 687c8d4a560SLinus Walleij * 688c8d4a560SLinus Walleij * See the manual figure 657 page 2203 and page 2198 for the 13 689c8d4a560SLinus Walleij * reg_blkeol_duration bits. 690c8d4a560SLinus Walleij * 691c8d4a560SLinus Walleij * FIXME: should this also be set up also for non-burst mode 692c8d4a560SLinus Walleij * according to figure 565 page 2202? 693c8d4a560SLinus Walleij */ 694c8d4a560SLinus Walleij blkeol_duration = DIV_ROUND_CLOSEST(blkeol_pck + 6, 695c8d4a560SLinus Walleij d->mdsi->lanes); 696c8d4a560SLinus Walleij dev_dbg(d->dev, "BLKEOL duration: %d clock cycles\n", 697c8d4a560SLinus Walleij blkeol_duration); 6985fc537bfSLinus Walleij 699c8d4a560SLinus Walleij val = readl(d->regs + DSI_VID_PCK_TIME); 700c8d4a560SLinus Walleij val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK; 701c8d4a560SLinus Walleij val |= blkeol_duration << 702c8d4a560SLinus Walleij DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT; 703c8d4a560SLinus Walleij writel(val, d->regs + DSI_VID_PCK_TIME); 704c8d4a560SLinus Walleij 705c8d4a560SLinus Walleij /* Max burst limit, this is given in bytes */ 706c8d4a560SLinus Walleij val = readl(d->regs + DSI_VID_VCA_SETTING1); 707c8d4a560SLinus Walleij val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK; 708c8d4a560SLinus Walleij val |= (blkeol_pck - 6) << 709c8d4a560SLinus Walleij DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT; 710c8d4a560SLinus Walleij writel(val, d->regs + DSI_VID_VCA_SETTING1); 7115fc537bfSLinus Walleij } 7125fc537bfSLinus Walleij 7135fc537bfSLinus Walleij /* Maximum line limit */ 7145fc537bfSLinus Walleij val = readl(d->regs + DSI_VID_VCA_SETTING2); 715c8d4a560SLinus Walleij val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK; 716c8d4a560SLinus Walleij val |= (blkline_pck - 6) << 717c8d4a560SLinus Walleij DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT; 7185fc537bfSLinus Walleij writel(val, d->regs + DSI_VID_VCA_SETTING2); 719c8d4a560SLinus Walleij dev_dbg(d->dev, "blkline pck: %d bytes\n", blkline_pck - 6); 7205fc537bfSLinus Walleij } 7215fc537bfSLinus Walleij 7225fc537bfSLinus Walleij static void mcde_dsi_start(struct mcde_dsi *d) 7235fc537bfSLinus Walleij { 7245fc537bfSLinus Walleij unsigned long hs_freq; 7255fc537bfSLinus Walleij u32 val; 7265fc537bfSLinus Walleij int i; 7275fc537bfSLinus Walleij 7285fc537bfSLinus Walleij /* No integration mode */ 7295fc537bfSLinus Walleij writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE); 7305fc537bfSLinus Walleij 7315fc537bfSLinus Walleij /* Enable the DSI port, from drivers/video/mcde/dsilink_v2.c */ 7325fc537bfSLinus Walleij val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN | 7335fc537bfSLinus Walleij DSI_MCTL_MAIN_DATA_CTL_BTA_EN | 7345fc537bfSLinus Walleij DSI_MCTL_MAIN_DATA_CTL_READ_EN | 7355fc537bfSLinus Walleij DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN; 7365fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 7375fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN; 7385fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 7395fc537bfSLinus Walleij 7405fc537bfSLinus Walleij /* Set a high command timeout, clear other fields */ 7415fc537bfSLinus Walleij val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT; 7425fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_CTL); 7435fc537bfSLinus Walleij 7445fc537bfSLinus Walleij /* 7455fc537bfSLinus Walleij * UI_X4 is described as "unit interval times four" 7465fc537bfSLinus Walleij * I guess since DSI packets are 4 bytes wide, one unit 7475fc537bfSLinus Walleij * is one byte. 7485fc537bfSLinus Walleij */ 7495fc537bfSLinus Walleij hs_freq = clk_get_rate(d->hs_clk); 7505fc537bfSLinus Walleij hs_freq /= 1000000; /* MHz */ 7515fc537bfSLinus Walleij val = 4000 / hs_freq; 7525fc537bfSLinus Walleij dev_dbg(d->dev, "UI value: %d\n", val); 7535fc537bfSLinus Walleij val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT; 7545fc537bfSLinus Walleij val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK; 7555fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_DPHY_STATIC); 7565fc537bfSLinus Walleij 7575fc537bfSLinus Walleij /* 7585fc537bfSLinus Walleij * Enable clocking: 0x0f (something?) between each burst, 7595fc537bfSLinus Walleij * enable the second lane if needed, enable continuous clock if 7605fc537bfSLinus Walleij * needed, enable switch into ULPM (ultra-low power mode) on 7615fc537bfSLinus Walleij * all the lines. 7625fc537bfSLinus Walleij */ 7635fc537bfSLinus Walleij val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT; 7645fc537bfSLinus Walleij if (d->mdsi->lanes == 2) 7655fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN; 7665fc537bfSLinus Walleij if (!(d->mdsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 7675fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS; 7685fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN | 7695fc537bfSLinus Walleij DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN | 7705fc537bfSLinus Walleij DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN; 7715fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL); 7725fc537bfSLinus Walleij 7735fc537bfSLinus Walleij val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) | 7745fc537bfSLinus Walleij (1 << DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT); 7755fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_ULPOUT_TIME); 7765fc537bfSLinus Walleij 7775fc537bfSLinus Walleij writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90, 7785fc537bfSLinus Walleij d->regs + DSI_DPHY_LANES_TRIM); 7795fc537bfSLinus Walleij 7805fc537bfSLinus Walleij /* High PHY timeout */ 7815fc537bfSLinus Walleij val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) | 7825fc537bfSLinus Walleij (0x3fff << DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT) | 7835fc537bfSLinus Walleij (0x3fff << DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT); 7845fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT); 7855fc537bfSLinus Walleij 7865fc537bfSLinus Walleij val = DSI_MCTL_MAIN_EN_PLL_START | 7875fc537bfSLinus Walleij DSI_MCTL_MAIN_EN_CKLANE_EN | 7885fc537bfSLinus Walleij DSI_MCTL_MAIN_EN_DAT1_EN | 7895fc537bfSLinus Walleij DSI_MCTL_MAIN_EN_IF1_EN; 7905fc537bfSLinus Walleij if (d->mdsi->lanes == 2) 7915fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_EN_DAT2_EN; 7925fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_EN); 7935fc537bfSLinus Walleij 7945fc537bfSLinus Walleij /* Wait for the PLL to lock and the clock and data lines to come up */ 7955fc537bfSLinus Walleij i = 0; 7965fc537bfSLinus Walleij val = DSI_MCTL_MAIN_STS_PLL_LOCK | 7975fc537bfSLinus Walleij DSI_MCTL_MAIN_STS_CLKLANE_READY | 7985fc537bfSLinus Walleij DSI_MCTL_MAIN_STS_DAT1_READY; 7995fc537bfSLinus Walleij if (d->mdsi->lanes == 2) 8005fc537bfSLinus Walleij val |= DSI_MCTL_MAIN_STS_DAT2_READY; 8015fc537bfSLinus Walleij while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) { 8025fc537bfSLinus Walleij /* Sleep for a millisecond */ 8035fc537bfSLinus Walleij usleep_range(1000, 1500); 8045fc537bfSLinus Walleij if (i++ == 100) { 8055fc537bfSLinus Walleij dev_warn(d->dev, "DSI lanes did not start up\n"); 8065fc537bfSLinus Walleij return; 8075fc537bfSLinus Walleij } 8085fc537bfSLinus Walleij } 8095fc537bfSLinus Walleij 8105fc537bfSLinus Walleij /* TODO needed? */ 8115fc537bfSLinus Walleij 8125fc537bfSLinus Walleij /* Command mode, clear IF1 ID */ 8135fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_CTL); 8145fc537bfSLinus Walleij /* 8155fc537bfSLinus Walleij * If we enable low-power mode here, with 8165fc537bfSLinus Walleij * val |= DSI_CMD_MODE_CTL_IF1_LP_EN 8175fc537bfSLinus Walleij * then display updates become really slow. 8185fc537bfSLinus Walleij */ 8195fc537bfSLinus Walleij val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 8205fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_CTL); 8215fc537bfSLinus Walleij 8225fc537bfSLinus Walleij /* Wait for DSI PHY to initialize */ 8235fc537bfSLinus Walleij usleep_range(100, 200); 8245fc537bfSLinus Walleij dev_info(d->dev, "DSI link enabled\n"); 8255fc537bfSLinus Walleij } 8265fc537bfSLinus Walleij 8275fc537bfSLinus Walleij 8285fc537bfSLinus Walleij static void mcde_dsi_bridge_enable(struct drm_bridge *bridge) 8295fc537bfSLinus Walleij { 8305fc537bfSLinus Walleij struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 8316ddfb00dSStephan Gerhold u32 val; 8326ddfb00dSStephan Gerhold 8336ddfb00dSStephan Gerhold if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8346ddfb00dSStephan Gerhold /* Enable video mode */ 8356ddfb00dSStephan Gerhold val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 8366ddfb00dSStephan Gerhold val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; 8376ddfb00dSStephan Gerhold writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 8386ddfb00dSStephan Gerhold } 8395fc537bfSLinus Walleij 8405fc537bfSLinus Walleij dev_info(d->dev, "enable DSI master\n"); 8415fc537bfSLinus Walleij }; 8425fc537bfSLinus Walleij 8433c5824bdSStephan Gerhold static void mcde_dsi_bridge_pre_enable(struct drm_bridge *bridge) 8445fc537bfSLinus Walleij { 8455fc537bfSLinus Walleij struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 8465fc537bfSLinus Walleij unsigned long hs_freq, lp_freq; 8475fc537bfSLinus Walleij u32 val; 8485fc537bfSLinus Walleij int ret; 8495fc537bfSLinus Walleij 8505fc537bfSLinus Walleij /* Copy maximum clock frequencies */ 8515fc537bfSLinus Walleij if (d->mdsi->lp_rate) 8525fc537bfSLinus Walleij lp_freq = d->mdsi->lp_rate; 8535fc537bfSLinus Walleij else 8545fc537bfSLinus Walleij lp_freq = DSI_DEFAULT_LP_FREQ_HZ; 8555fc537bfSLinus Walleij if (d->mdsi->hs_rate) 8565fc537bfSLinus Walleij hs_freq = d->mdsi->hs_rate; 8575fc537bfSLinus Walleij else 8585fc537bfSLinus Walleij hs_freq = DSI_DEFAULT_HS_FREQ_HZ; 8595fc537bfSLinus Walleij 8605fc537bfSLinus Walleij /* Enable LP (Low Power, Energy Save, ES) and HS (High Speed) clocks */ 8615fc537bfSLinus Walleij d->lp_freq = clk_round_rate(d->lp_clk, lp_freq); 8625fc537bfSLinus Walleij ret = clk_set_rate(d->lp_clk, d->lp_freq); 8635fc537bfSLinus Walleij if (ret) 8645fc537bfSLinus Walleij dev_err(d->dev, "failed to set LP clock rate %lu Hz\n", 8655fc537bfSLinus Walleij d->lp_freq); 8665fc537bfSLinus Walleij 8675fc537bfSLinus Walleij d->hs_freq = clk_round_rate(d->hs_clk, hs_freq); 8685fc537bfSLinus Walleij ret = clk_set_rate(d->hs_clk, d->hs_freq); 8695fc537bfSLinus Walleij if (ret) 8705fc537bfSLinus Walleij dev_err(d->dev, "failed to set HS clock rate %lu Hz\n", 8715fc537bfSLinus Walleij d->hs_freq); 8725fc537bfSLinus Walleij 8735fc537bfSLinus Walleij /* Start clocks */ 8745fc537bfSLinus Walleij ret = clk_prepare_enable(d->lp_clk); 8755fc537bfSLinus Walleij if (ret) 8765fc537bfSLinus Walleij dev_err(d->dev, "failed to enable LP clock\n"); 8775fc537bfSLinus Walleij else 8785fc537bfSLinus Walleij dev_info(d->dev, "DSI LP clock rate %lu Hz\n", 8795fc537bfSLinus Walleij d->lp_freq); 8805fc537bfSLinus Walleij ret = clk_prepare_enable(d->hs_clk); 8815fc537bfSLinus Walleij if (ret) 8825fc537bfSLinus Walleij dev_err(d->dev, "failed to enable HS clock\n"); 8835fc537bfSLinus Walleij else 8845fc537bfSLinus Walleij dev_info(d->dev, "DSI HS clock rate %lu Hz\n", 8855fc537bfSLinus Walleij d->hs_freq); 8865fc537bfSLinus Walleij 8875fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8883c5824bdSStephan Gerhold /* Put IF1 into video mode */ 8893c5824bdSStephan Gerhold val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 8903c5824bdSStephan Gerhold val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE; 8913c5824bdSStephan Gerhold writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 8923c5824bdSStephan Gerhold 8933c5824bdSStephan Gerhold /* Disable command mode on IF1 */ 8943c5824bdSStephan Gerhold val = readl(d->regs + DSI_CMD_MODE_CTL); 8953c5824bdSStephan Gerhold val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN; 8963c5824bdSStephan Gerhold writel(val, d->regs + DSI_CMD_MODE_CTL); 8973c5824bdSStephan Gerhold 8983c5824bdSStephan Gerhold /* Enable some error interrupts */ 8993c5824bdSStephan Gerhold val = readl(d->regs + DSI_VID_MODE_STS_CTL); 9003c5824bdSStephan Gerhold val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; 9013c5824bdSStephan Gerhold val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; 9023c5824bdSStephan Gerhold writel(val, d->regs + DSI_VID_MODE_STS_CTL); 9035fc537bfSLinus Walleij } else { 9045fc537bfSLinus Walleij /* Command mode, clear IF1 ID */ 9055fc537bfSLinus Walleij val = readl(d->regs + DSI_CMD_MODE_CTL); 9065fc537bfSLinus Walleij /* 9075fc537bfSLinus Walleij * If we enable low-power mode here with 9085fc537bfSLinus Walleij * val |= DSI_CMD_MODE_CTL_IF1_LP_EN 9095fc537bfSLinus Walleij * the display updates become really slow. 9105fc537bfSLinus Walleij */ 9115fc537bfSLinus Walleij val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; 9125fc537bfSLinus Walleij writel(val, d->regs + DSI_CMD_MODE_CTL); 9135fc537bfSLinus Walleij } 9145fc537bfSLinus Walleij } 9155fc537bfSLinus Walleij 9163c5824bdSStephan Gerhold static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge, 9173c5824bdSStephan Gerhold const struct drm_display_mode *mode, 9183c5824bdSStephan Gerhold const struct drm_display_mode *adj) 9193c5824bdSStephan Gerhold { 9203c5824bdSStephan Gerhold struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 9213c5824bdSStephan Gerhold 9223c5824bdSStephan Gerhold if (!d->mdsi) { 9233c5824bdSStephan Gerhold dev_err(d->dev, "no DSI device attached to encoder!\n"); 9243c5824bdSStephan Gerhold return; 9253c5824bdSStephan Gerhold } 9263c5824bdSStephan Gerhold 9273c5824bdSStephan Gerhold dev_info(d->dev, "set DSI master to %dx%d %u Hz %s mode\n", 9283c5824bdSStephan Gerhold mode->hdisplay, mode->vdisplay, mode->clock * 1000, 9293c5824bdSStephan Gerhold (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? "VIDEO" : "CMD" 9303c5824bdSStephan Gerhold ); 9313c5824bdSStephan Gerhold 9323c5824bdSStephan Gerhold if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) 9333c5824bdSStephan Gerhold mcde_dsi_setup_video_mode(d, mode); 9343c5824bdSStephan Gerhold } 9353c5824bdSStephan Gerhold 9365fc537bfSLinus Walleij static void mcde_dsi_wait_for_command_mode_stop(struct mcde_dsi *d) 9375fc537bfSLinus Walleij { 9385fc537bfSLinus Walleij u32 val; 9395fc537bfSLinus Walleij int i; 9405fc537bfSLinus Walleij 9415fc537bfSLinus Walleij /* 9425fc537bfSLinus Walleij * Wait until we get out of command mode 9435fc537bfSLinus Walleij * CSM = Command State Machine 9445fc537bfSLinus Walleij */ 9455fc537bfSLinus Walleij i = 0; 9465fc537bfSLinus Walleij val = DSI_CMD_MODE_STS_CSM_RUNNING; 9475fc537bfSLinus Walleij while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) { 9485fc537bfSLinus Walleij /* Sleep for a millisecond */ 9495fc537bfSLinus Walleij usleep_range(1000, 2000); 9505fc537bfSLinus Walleij if (i++ == 100) { 9515fc537bfSLinus Walleij dev_warn(d->dev, 9525fc537bfSLinus Walleij "could not get out of command mode\n"); 9535fc537bfSLinus Walleij return; 9545fc537bfSLinus Walleij } 9555fc537bfSLinus Walleij } 9565fc537bfSLinus Walleij } 9575fc537bfSLinus Walleij 9585fc537bfSLinus Walleij static void mcde_dsi_wait_for_video_mode_stop(struct mcde_dsi *d) 9595fc537bfSLinus Walleij { 9605fc537bfSLinus Walleij u32 val; 9615fc537bfSLinus Walleij int i; 9625fc537bfSLinus Walleij 9635fc537bfSLinus Walleij /* Wait until we get out og video mode */ 9645fc537bfSLinus Walleij i = 0; 9655fc537bfSLinus Walleij val = DSI_VID_MODE_STS_VSG_RUNNING; 9665fc537bfSLinus Walleij while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) { 9675fc537bfSLinus Walleij /* Sleep for a millisecond */ 9685fc537bfSLinus Walleij usleep_range(1000, 2000); 9695fc537bfSLinus Walleij if (i++ == 100) { 9705fc537bfSLinus Walleij dev_warn(d->dev, 9715fc537bfSLinus Walleij "could not get out of video mode\n"); 9725fc537bfSLinus Walleij return; 9735fc537bfSLinus Walleij } 9745fc537bfSLinus Walleij } 9755fc537bfSLinus Walleij } 9765fc537bfSLinus Walleij 9775fc537bfSLinus Walleij static void mcde_dsi_bridge_disable(struct drm_bridge *bridge) 9785fc537bfSLinus Walleij { 9795fc537bfSLinus Walleij struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 9805fc537bfSLinus Walleij u32 val; 9815fc537bfSLinus Walleij 9825fc537bfSLinus Walleij /* Disable all error interrupts */ 9835fc537bfSLinus Walleij writel(0, d->regs + DSI_VID_MODE_STS_CTL); 9845fc537bfSLinus Walleij 9855fc537bfSLinus Walleij if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 9865fc537bfSLinus Walleij /* Stop video mode */ 9875fc537bfSLinus Walleij val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); 9885fc537bfSLinus Walleij val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN; 9895fc537bfSLinus Walleij writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); 9905fc537bfSLinus Walleij mcde_dsi_wait_for_video_mode_stop(d); 9915fc537bfSLinus Walleij } else { 9925fc537bfSLinus Walleij /* Stop command mode */ 9935fc537bfSLinus Walleij mcde_dsi_wait_for_command_mode_stop(d); 9945fc537bfSLinus Walleij } 9955fc537bfSLinus Walleij 9965fc537bfSLinus Walleij /* Stop clocks */ 9975fc537bfSLinus Walleij clk_disable_unprepare(d->hs_clk); 9985fc537bfSLinus Walleij clk_disable_unprepare(d->lp_clk); 9995fc537bfSLinus Walleij } 10005fc537bfSLinus Walleij 1001a25b988fSLaurent Pinchart static int mcde_dsi_bridge_attach(struct drm_bridge *bridge, 1002a25b988fSLaurent Pinchart enum drm_bridge_attach_flags flags) 10035fc537bfSLinus Walleij { 10045fc537bfSLinus Walleij struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); 10055fc537bfSLinus Walleij struct drm_device *drm = bridge->dev; 10065fc537bfSLinus Walleij int ret; 10075fc537bfSLinus Walleij 10085fc537bfSLinus Walleij if (!drm_core_check_feature(drm, DRIVER_ATOMIC)) { 10095fc537bfSLinus Walleij dev_err(d->dev, "we need atomic updates\n"); 10105fc537bfSLinus Walleij return -ENOTSUPP; 10115fc537bfSLinus Walleij } 10125fc537bfSLinus Walleij 10131f79c60eSStephan Gerhold /* Attach the DSI bridge to the output (panel etc) bridge */ 1014a25b988fSLaurent Pinchart ret = drm_bridge_attach(bridge->encoder, d->bridge_out, bridge, flags); 10155fc537bfSLinus Walleij if (ret) { 10165fc537bfSLinus Walleij dev_err(d->dev, "failed to attach the DSI bridge\n"); 10175fc537bfSLinus Walleij return ret; 10185fc537bfSLinus Walleij } 10195fc537bfSLinus Walleij 10205fc537bfSLinus Walleij return 0; 10215fc537bfSLinus Walleij } 10225fc537bfSLinus Walleij 10235fc537bfSLinus Walleij static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = { 10245fc537bfSLinus Walleij .attach = mcde_dsi_bridge_attach, 10255fc537bfSLinus Walleij .mode_set = mcde_dsi_bridge_mode_set, 10265fc537bfSLinus Walleij .disable = mcde_dsi_bridge_disable, 10275fc537bfSLinus Walleij .enable = mcde_dsi_bridge_enable, 10283c5824bdSStephan Gerhold .pre_enable = mcde_dsi_bridge_pre_enable, 10295fc537bfSLinus Walleij }; 10305fc537bfSLinus Walleij 10315fc537bfSLinus Walleij static int mcde_dsi_bind(struct device *dev, struct device *master, 10325fc537bfSLinus Walleij void *data) 10335fc537bfSLinus Walleij { 10345fc537bfSLinus Walleij struct drm_device *drm = data; 1035fd7ee85cSDaniel Vetter struct mcde *mcde = to_mcde(drm); 10365fc537bfSLinus Walleij struct mcde_dsi *d = dev_get_drvdata(dev); 10375fc537bfSLinus Walleij struct device_node *child; 10385fc537bfSLinus Walleij struct drm_panel *panel = NULL; 10395fc537bfSLinus Walleij struct drm_bridge *bridge = NULL; 10405fc537bfSLinus Walleij 10415fc537bfSLinus Walleij if (!of_get_available_child_count(dev->of_node)) { 10425fc537bfSLinus Walleij dev_info(dev, "unused DSI interface\n"); 10435fc537bfSLinus Walleij d->unused = true; 10445fc537bfSLinus Walleij return 0; 10455fc537bfSLinus Walleij } 10465fc537bfSLinus Walleij d->mcde = mcde; 10475fc537bfSLinus Walleij /* If the display attached before binding, set this up */ 10485fc537bfSLinus Walleij if (d->mdsi) 1049d920e8daSStephan Gerhold mcde_dsi_attach_to_mcde(d); 10505fc537bfSLinus Walleij 10515fc537bfSLinus Walleij /* Obtain the clocks */ 10525fc537bfSLinus Walleij d->hs_clk = devm_clk_get(dev, "hs"); 10535fc537bfSLinus Walleij if (IS_ERR(d->hs_clk)) { 10545fc537bfSLinus Walleij dev_err(dev, "unable to get HS clock\n"); 10555fc537bfSLinus Walleij return PTR_ERR(d->hs_clk); 10565fc537bfSLinus Walleij } 10575fc537bfSLinus Walleij 10585fc537bfSLinus Walleij d->lp_clk = devm_clk_get(dev, "lp"); 10595fc537bfSLinus Walleij if (IS_ERR(d->lp_clk)) { 10605fc537bfSLinus Walleij dev_err(dev, "unable to get LP clock\n"); 10615fc537bfSLinus Walleij return PTR_ERR(d->lp_clk); 10625fc537bfSLinus Walleij } 10635fc537bfSLinus Walleij 10645fc537bfSLinus Walleij /* Assert RESET through the PRCMU, active low */ 10655fc537bfSLinus Walleij /* FIXME: which DSI block? */ 10665fc537bfSLinus Walleij regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 10675fc537bfSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 10685fc537bfSLinus Walleij 10695fc537bfSLinus Walleij usleep_range(100, 200); 10705fc537bfSLinus Walleij 10715fc537bfSLinus Walleij /* De-assert RESET again */ 10725fc537bfSLinus Walleij regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 10735fc537bfSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 10745fc537bfSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN); 10755fc537bfSLinus Walleij 10765fc537bfSLinus Walleij /* Start up the hardware */ 10775fc537bfSLinus Walleij mcde_dsi_start(d); 10785fc537bfSLinus Walleij 10795fc537bfSLinus Walleij /* Look for a panel as a child to this node */ 10805fc537bfSLinus Walleij for_each_available_child_of_node(dev->of_node, child) { 10815fc537bfSLinus Walleij panel = of_drm_find_panel(child); 10825fc537bfSLinus Walleij if (IS_ERR(panel)) { 1083c131280cSStephan Gerhold dev_err(dev, "failed to find panel try bridge (%ld)\n", 10845fc537bfSLinus Walleij PTR_ERR(panel)); 1085c131280cSStephan Gerhold panel = NULL; 1086c131280cSStephan Gerhold 10875fc537bfSLinus Walleij bridge = of_drm_find_bridge(child); 1088761e9f4fSWei Yongjun if (!bridge) { 1089761e9f4fSWei Yongjun dev_err(dev, "failed to find bridge\n"); 1090761e9f4fSWei Yongjun return -EINVAL; 10915fc537bfSLinus Walleij } 10925fc537bfSLinus Walleij } 10935fc537bfSLinus Walleij } 10945fc537bfSLinus Walleij if (panel) { 109589958b7cSLaurent Pinchart bridge = drm_panel_bridge_add_typed(panel, 10965fc537bfSLinus Walleij DRM_MODE_CONNECTOR_DSI); 10975fc537bfSLinus Walleij if (IS_ERR(bridge)) { 10985fc537bfSLinus Walleij dev_err(dev, "error adding panel bridge\n"); 10995fc537bfSLinus Walleij return PTR_ERR(bridge); 11005fc537bfSLinus Walleij } 11015fc537bfSLinus Walleij dev_info(dev, "connected to panel\n"); 11025fc537bfSLinus Walleij d->panel = panel; 11035fc537bfSLinus Walleij } else if (bridge) { 11045fc537bfSLinus Walleij /* TODO: AV8100 HDMI encoder goes here for example */ 11055fc537bfSLinus Walleij dev_info(dev, "connected to non-panel bridge (unsupported)\n"); 11065fc537bfSLinus Walleij return -ENODEV; 11075fc537bfSLinus Walleij } else { 11085fc537bfSLinus Walleij dev_err(dev, "no panel or bridge\n"); 11095fc537bfSLinus Walleij return -ENODEV; 11105fc537bfSLinus Walleij } 11115fc537bfSLinus Walleij 11125fc537bfSLinus Walleij d->bridge_out = bridge; 11135fc537bfSLinus Walleij 11145fc537bfSLinus Walleij /* Create a bridge for this DSI channel */ 11155fc537bfSLinus Walleij d->bridge.funcs = &mcde_dsi_bridge_funcs; 11165fc537bfSLinus Walleij d->bridge.of_node = dev->of_node; 11175fc537bfSLinus Walleij drm_bridge_add(&d->bridge); 11185fc537bfSLinus Walleij 11195fc537bfSLinus Walleij /* TODO: first come first serve, use a list */ 11205fc537bfSLinus Walleij mcde->bridge = &d->bridge; 11215fc537bfSLinus Walleij 11225fc537bfSLinus Walleij dev_info(dev, "initialized MCDE DSI bridge\n"); 11235fc537bfSLinus Walleij 11245fc537bfSLinus Walleij return 0; 11255fc537bfSLinus Walleij } 11265fc537bfSLinus Walleij 11275fc537bfSLinus Walleij static void mcde_dsi_unbind(struct device *dev, struct device *master, 11285fc537bfSLinus Walleij void *data) 11295fc537bfSLinus Walleij { 11305fc537bfSLinus Walleij struct mcde_dsi *d = dev_get_drvdata(dev); 11315fc537bfSLinus Walleij 11325fc537bfSLinus Walleij if (d->panel) 11335fc537bfSLinus Walleij drm_panel_bridge_remove(d->bridge_out); 11345fc537bfSLinus Walleij regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET, 11355fc537bfSLinus Walleij PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0); 11365fc537bfSLinus Walleij } 11375fc537bfSLinus Walleij 11385fc537bfSLinus Walleij static const struct component_ops mcde_dsi_component_ops = { 11395fc537bfSLinus Walleij .bind = mcde_dsi_bind, 11405fc537bfSLinus Walleij .unbind = mcde_dsi_unbind, 11415fc537bfSLinus Walleij }; 11425fc537bfSLinus Walleij 11435fc537bfSLinus Walleij static int mcde_dsi_probe(struct platform_device *pdev) 11445fc537bfSLinus Walleij { 11455fc537bfSLinus Walleij struct device *dev = &pdev->dev; 11465fc537bfSLinus Walleij struct mcde_dsi *d; 11475fc537bfSLinus Walleij struct mipi_dsi_host *host; 11485fc537bfSLinus Walleij struct resource *res; 11495fc537bfSLinus Walleij u32 dsi_id; 11505fc537bfSLinus Walleij int ret; 11515fc537bfSLinus Walleij 11525fc537bfSLinus Walleij d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL); 11535fc537bfSLinus Walleij if (!d) 11545fc537bfSLinus Walleij return -ENOMEM; 11555fc537bfSLinus Walleij d->dev = dev; 11565fc537bfSLinus Walleij platform_set_drvdata(pdev, d); 11575fc537bfSLinus Walleij 11585fc537bfSLinus Walleij /* Get a handle on the PRCMU so we can do reset */ 11595fc537bfSLinus Walleij d->prcmu = 11605fc537bfSLinus Walleij syscon_regmap_lookup_by_compatible("stericsson,db8500-prcmu"); 11615fc537bfSLinus Walleij if (IS_ERR(d->prcmu)) { 11625fc537bfSLinus Walleij dev_err(dev, "no PRCMU regmap\n"); 11635fc537bfSLinus Walleij return PTR_ERR(d->prcmu); 11645fc537bfSLinus Walleij } 11655fc537bfSLinus Walleij 11665fc537bfSLinus Walleij res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 11675fc537bfSLinus Walleij d->regs = devm_ioremap_resource(dev, res); 11685fc537bfSLinus Walleij if (IS_ERR(d->regs)) { 11695fc537bfSLinus Walleij dev_err(dev, "no DSI regs\n"); 11705fc537bfSLinus Walleij return PTR_ERR(d->regs); 11715fc537bfSLinus Walleij } 11725fc537bfSLinus Walleij 11735fc537bfSLinus Walleij dsi_id = readl(d->regs + DSI_ID_REG); 11745fc537bfSLinus Walleij dev_info(dev, "HW revision 0x%08x\n", dsi_id); 11755fc537bfSLinus Walleij 11765fc537bfSLinus Walleij host = &d->dsi_host; 11775fc537bfSLinus Walleij host->dev = dev; 11785fc537bfSLinus Walleij host->ops = &mcde_dsi_host_ops; 11795fc537bfSLinus Walleij ret = mipi_dsi_host_register(host); 11805fc537bfSLinus Walleij if (ret < 0) { 11815fc537bfSLinus Walleij dev_err(dev, "failed to register DSI host: %d\n", ret); 11825fc537bfSLinus Walleij return ret; 11835fc537bfSLinus Walleij } 11845fc537bfSLinus Walleij dev_info(dev, "registered DSI host\n"); 11855fc537bfSLinus Walleij 11865fc537bfSLinus Walleij platform_set_drvdata(pdev, d); 11875fc537bfSLinus Walleij return component_add(dev, &mcde_dsi_component_ops); 11885fc537bfSLinus Walleij } 11895fc537bfSLinus Walleij 11905fc537bfSLinus Walleij static int mcde_dsi_remove(struct platform_device *pdev) 11915fc537bfSLinus Walleij { 11925fc537bfSLinus Walleij struct mcde_dsi *d = platform_get_drvdata(pdev); 11935fc537bfSLinus Walleij 11945fc537bfSLinus Walleij component_del(&pdev->dev, &mcde_dsi_component_ops); 11955fc537bfSLinus Walleij mipi_dsi_host_unregister(&d->dsi_host); 11965fc537bfSLinus Walleij 11975fc537bfSLinus Walleij return 0; 11985fc537bfSLinus Walleij } 11995fc537bfSLinus Walleij 12005fc537bfSLinus Walleij static const struct of_device_id mcde_dsi_of_match[] = { 12015fc537bfSLinus Walleij { 12025fc537bfSLinus Walleij .compatible = "ste,mcde-dsi", 12035fc537bfSLinus Walleij }, 12045fc537bfSLinus Walleij {}, 12055fc537bfSLinus Walleij }; 12065fc537bfSLinus Walleij 12075fc537bfSLinus Walleij struct platform_driver mcde_dsi_driver = { 12085fc537bfSLinus Walleij .driver = { 12095fc537bfSLinus Walleij .name = "mcde-dsi", 12105fc537bfSLinus Walleij .of_match_table = of_match_ptr(mcde_dsi_of_match), 12115fc537bfSLinus Walleij }, 12125fc537bfSLinus Walleij .probe = mcde_dsi_probe, 12135fc537bfSLinus Walleij .remove = mcde_dsi_remove, 12145fc537bfSLinus Walleij }; 1215