1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org> 4 * Parts of this file were based on the MCDE driver by Marcus Lorentzon 5 * (C) ST-Ericsson SA 2013 6 */ 7 8 /** 9 * DOC: ST-Ericsson MCDE Driver 10 * 11 * The MCDE (short for multi-channel display engine) is a graphics 12 * controller found in the Ux500 chipsets, such as NovaThor U8500. 13 * It was initially conceptualized by ST Microelectronics for the 14 * successor of the Nomadik line, STn8500 but productified in the 15 * ST-Ericsson U8500 where is was used for mass-market deployments 16 * in Android phones from Samsung and Sony Ericsson. 17 * 18 * It can do 1080p30 on SDTV CCIR656, DPI-2, DBI-2 or DSI for 19 * panels with or without frame buffering and can convert most 20 * input formats including most variants of RGB and YUV. 21 * 22 * The hardware has four display pipes, and the layout is a little 23 * bit like this:: 24 * 25 * Memory -> Overlay -> Channel -> FIFO -> 5 formatters -> DSI/DPI 26 * External 0..5 0..3 A,B, 3 x DSI bridge 27 * source 0..9 C0,C1 2 x DPI 28 * 29 * FIFOs A and B are for LCD and HDMI while FIFO CO/C1 are for 30 * panels with embedded buffer. 31 * 3 of the formatters are for DSI. 32 * 2 of the formatters are for DPI. 33 * 34 * Behind the formatters are the DSI or DPI ports that route to 35 * the external pins of the chip. As there are 3 DSI ports and one 36 * DPI port, it is possible to configure up to 4 display pipelines 37 * (effectively using channels 0..3) for concurrent use. 38 * 39 * In the current DRM/KMS setup, we use one external source, one overlay, 40 * one FIFO and one formatter which we connect to the simple CMA framebuffer 41 * helpers. We then provide a bridge to the DSI port, and on the DSI port 42 * bridge we connect hang a panel bridge or other bridge. This may be subject 43 * to change as we exploit more of the hardware capabilities. 44 * 45 * TODO: 46 * 47 * - Enabled damaged rectangles using drm_plane_enable_fb_damage_clips() 48 * so we can selectively just transmit the damaged area to a 49 * command-only display. 50 * - Enable mixing of more planes, possibly at the cost of moving away 51 * from using the simple framebuffer pipeline. 52 * - Enable output to bridges such as the AV8100 HDMI encoder from 53 * the DSI bridge. 54 */ 55 56 #include <linux/clk.h> 57 #include <linux/component.h> 58 #include <linux/dma-buf.h> 59 #include <linux/irq.h> 60 #include <linux/io.h> 61 #include <linux/module.h> 62 #include <linux/of_platform.h> 63 #include <linux/platform_device.h> 64 #include <linux/regulator/consumer.h> 65 #include <linux/slab.h> 66 67 #include <drm/drm_atomic_helper.h> 68 #include <drm/drm_bridge.h> 69 #include <drm/drm_drv.h> 70 #include <drm/drm_fb_cma_helper.h> 71 #include <drm/drm_fb_helper.h> 72 #include <drm/drm_gem.h> 73 #include <drm/drm_gem_cma_helper.h> 74 #include <drm/drm_gem_framebuffer_helper.h> 75 #include <drm/drm_managed.h> 76 #include <drm/drm_of.h> 77 #include <drm/drm_probe_helper.h> 78 #include <drm/drm_panel.h> 79 #include <drm/drm_vblank.h> 80 81 #include "mcde_drm.h" 82 83 #define DRIVER_DESC "DRM module for MCDE" 84 85 #define MCDE_CR 0x00000000 86 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0 87 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F 88 #define MCDE_CR_IFIFOCTRLEN BIT(15) 89 #define MCDE_CR_UFRECOVERY_MODE_V422 BIT(16) 90 #define MCDE_CR_WRAP_MODE_V422_SHIFT BIT(17) 91 #define MCDE_CR_AUTOCLKG_EN BIT(30) 92 #define MCDE_CR_MCDEEN BIT(31) 93 94 #define MCDE_CONF0 0x00000004 95 #define MCDE_CONF0_SYNCMUX0 BIT(0) 96 #define MCDE_CONF0_SYNCMUX1 BIT(1) 97 #define MCDE_CONF0_SYNCMUX2 BIT(2) 98 #define MCDE_CONF0_SYNCMUX3 BIT(3) 99 #define MCDE_CONF0_SYNCMUX4 BIT(4) 100 #define MCDE_CONF0_SYNCMUX5 BIT(5) 101 #define MCDE_CONF0_SYNCMUX6 BIT(6) 102 #define MCDE_CONF0_SYNCMUX7 BIT(7) 103 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12 104 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000 105 #define MCDE_CONF0_OUTMUX0_SHIFT 16 106 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000 107 #define MCDE_CONF0_OUTMUX1_SHIFT 19 108 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000 109 #define MCDE_CONF0_OUTMUX2_SHIFT 22 110 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000 111 #define MCDE_CONF0_OUTMUX3_SHIFT 25 112 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000 113 #define MCDE_CONF0_OUTMUX4_SHIFT 28 114 #define MCDE_CONF0_OUTMUX4_MASK 0x70000000 115 116 #define MCDE_SSP 0x00000008 117 #define MCDE_AIS 0x00000100 118 #define MCDE_IMSCERR 0x00000110 119 #define MCDE_RISERR 0x00000120 120 #define MCDE_MISERR 0x00000130 121 #define MCDE_SISERR 0x00000140 122 123 #define MCDE_PID 0x000001FC 124 #define MCDE_PID_METALFIX_VERSION_SHIFT 0 125 #define MCDE_PID_METALFIX_VERSION_MASK 0x000000FF 126 #define MCDE_PID_DEVELOPMENT_VERSION_SHIFT 8 127 #define MCDE_PID_DEVELOPMENT_VERSION_MASK 0x0000FF00 128 #define MCDE_PID_MINOR_VERSION_SHIFT 16 129 #define MCDE_PID_MINOR_VERSION_MASK 0x00FF0000 130 #define MCDE_PID_MAJOR_VERSION_SHIFT 24 131 #define MCDE_PID_MAJOR_VERSION_MASK 0xFF000000 132 133 static const struct drm_mode_config_funcs mcde_mode_config_funcs = { 134 .fb_create = drm_gem_fb_create_with_dirty, 135 .atomic_check = drm_atomic_helper_check, 136 .atomic_commit = drm_atomic_helper_commit, 137 }; 138 139 static const struct drm_mode_config_helper_funcs mcde_mode_config_helpers = { 140 /* 141 * Using this function is necessary to commit atomic updates 142 * that need the CRTC to be enabled before a commit, as is 143 * the case with e.g. DSI displays. 144 */ 145 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 146 }; 147 148 static irqreturn_t mcde_irq(int irq, void *data) 149 { 150 struct mcde *mcde = data; 151 u32 val; 152 153 val = readl(mcde->regs + MCDE_MISERR); 154 155 mcde_display_irq(mcde); 156 157 if (val) 158 dev_info(mcde->dev, "some error IRQ\n"); 159 writel(val, mcde->regs + MCDE_RISERR); 160 161 return IRQ_HANDLED; 162 } 163 164 static int mcde_modeset_init(struct drm_device *drm) 165 { 166 struct drm_mode_config *mode_config; 167 struct mcde *mcde = to_mcde(drm); 168 int ret; 169 170 if (!mcde->bridge) { 171 dev_err(drm->dev, "no display output bridge yet\n"); 172 return -EPROBE_DEFER; 173 } 174 175 mode_config = &drm->mode_config; 176 mode_config->funcs = &mcde_mode_config_funcs; 177 mode_config->helper_private = &mcde_mode_config_helpers; 178 /* This hardware can do 1080p */ 179 mode_config->min_width = 1; 180 mode_config->max_width = 1920; 181 mode_config->min_height = 1; 182 mode_config->max_height = 1080; 183 184 ret = drm_vblank_init(drm, 1); 185 if (ret) { 186 dev_err(drm->dev, "failed to init vblank\n"); 187 return ret; 188 } 189 190 ret = mcde_display_init(drm); 191 if (ret) { 192 dev_err(drm->dev, "failed to init display\n"); 193 return ret; 194 } 195 196 /* 197 * Attach the DSI bridge 198 * 199 * TODO: when adding support for the DPI bridge or several DSI bridges, 200 * we selectively connect the bridge(s) here instead of this simple 201 * attachment. 202 */ 203 ret = drm_simple_display_pipe_attach_bridge(&mcde->pipe, 204 mcde->bridge); 205 if (ret) { 206 dev_err(drm->dev, "failed to attach display output bridge\n"); 207 return ret; 208 } 209 210 drm_mode_config_reset(drm); 211 drm_kms_helper_poll_init(drm); 212 213 return 0; 214 } 215 216 DEFINE_DRM_GEM_CMA_FOPS(drm_fops); 217 218 static struct drm_driver mcde_drm_driver = { 219 .driver_features = 220 DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 221 .lastclose = drm_fb_helper_lastclose, 222 .ioctls = NULL, 223 .fops = &drm_fops, 224 .name = "mcde", 225 .desc = DRIVER_DESC, 226 .date = "20180529", 227 .major = 1, 228 .minor = 0, 229 .patchlevel = 0, 230 DRM_GEM_CMA_DRIVER_OPS, 231 }; 232 233 static int mcde_drm_bind(struct device *dev) 234 { 235 struct drm_device *drm = dev_get_drvdata(dev); 236 int ret; 237 238 ret = drmm_mode_config_init(drm); 239 if (ret) 240 return ret; 241 242 ret = component_bind_all(drm->dev, drm); 243 if (ret) { 244 dev_err(dev, "can't bind component devices\n"); 245 return ret; 246 } 247 248 ret = mcde_modeset_init(drm); 249 if (ret) 250 goto unbind; 251 252 ret = drm_dev_register(drm, 0); 253 if (ret < 0) 254 goto unbind; 255 256 drm_fbdev_generic_setup(drm, 32); 257 258 return 0; 259 260 unbind: 261 component_unbind_all(drm->dev, drm); 262 return ret; 263 } 264 265 static void mcde_drm_unbind(struct device *dev) 266 { 267 struct drm_device *drm = dev_get_drvdata(dev); 268 269 drm_dev_unregister(drm); 270 drm_atomic_helper_shutdown(drm); 271 component_unbind_all(drm->dev, drm); 272 } 273 274 static const struct component_master_ops mcde_drm_comp_ops = { 275 .bind = mcde_drm_bind, 276 .unbind = mcde_drm_unbind, 277 }; 278 279 static struct platform_driver *const mcde_component_drivers[] = { 280 &mcde_dsi_driver, 281 }; 282 283 static int mcde_compare_dev(struct device *dev, void *data) 284 { 285 return dev == data; 286 } 287 288 static int mcde_probe(struct platform_device *pdev) 289 { 290 struct device *dev = &pdev->dev; 291 struct drm_device *drm; 292 struct mcde *mcde; 293 struct component_match *match = NULL; 294 struct resource *res; 295 u32 pid; 296 u32 val; 297 int irq; 298 int ret; 299 int i; 300 301 mcde = devm_drm_dev_alloc(dev, &mcde_drm_driver, struct mcde, drm); 302 if (IS_ERR(mcde)) 303 return PTR_ERR(mcde); 304 drm = &mcde->drm; 305 mcde->dev = dev; 306 platform_set_drvdata(pdev, drm); 307 308 /* Enable continuous updates: this is what Linux' framebuffer expects */ 309 mcde->oneshot_mode = false; 310 311 /* First obtain and turn on the main power */ 312 mcde->epod = devm_regulator_get(dev, "epod"); 313 if (IS_ERR(mcde->epod)) { 314 ret = PTR_ERR(mcde->epod); 315 dev_err(dev, "can't get EPOD regulator\n"); 316 return ret; 317 } 318 ret = regulator_enable(mcde->epod); 319 if (ret) { 320 dev_err(dev, "can't enable EPOD regulator\n"); 321 return ret; 322 } 323 mcde->vana = devm_regulator_get(dev, "vana"); 324 if (IS_ERR(mcde->vana)) { 325 ret = PTR_ERR(mcde->vana); 326 dev_err(dev, "can't get VANA regulator\n"); 327 goto regulator_epod_off; 328 } 329 ret = regulator_enable(mcde->vana); 330 if (ret) { 331 dev_err(dev, "can't enable VANA regulator\n"); 332 goto regulator_epod_off; 333 } 334 /* 335 * The vendor code uses ESRAM (onchip RAM) and need to activate 336 * the v-esram34 regulator, but we don't use that yet 337 */ 338 339 /* Clock the silicon so we can access the registers */ 340 mcde->mcde_clk = devm_clk_get(dev, "mcde"); 341 if (IS_ERR(mcde->mcde_clk)) { 342 dev_err(dev, "unable to get MCDE main clock\n"); 343 ret = PTR_ERR(mcde->mcde_clk); 344 goto regulator_off; 345 } 346 ret = clk_prepare_enable(mcde->mcde_clk); 347 if (ret) { 348 dev_err(dev, "failed to enable MCDE main clock\n"); 349 goto regulator_off; 350 } 351 dev_info(dev, "MCDE clk rate %lu Hz\n", clk_get_rate(mcde->mcde_clk)); 352 353 mcde->lcd_clk = devm_clk_get(dev, "lcd"); 354 if (IS_ERR(mcde->lcd_clk)) { 355 dev_err(dev, "unable to get LCD clock\n"); 356 ret = PTR_ERR(mcde->lcd_clk); 357 goto clk_disable; 358 } 359 mcde->hdmi_clk = devm_clk_get(dev, "hdmi"); 360 if (IS_ERR(mcde->hdmi_clk)) { 361 dev_err(dev, "unable to get HDMI clock\n"); 362 ret = PTR_ERR(mcde->hdmi_clk); 363 goto clk_disable; 364 } 365 366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 367 mcde->regs = devm_ioremap_resource(dev, res); 368 if (IS_ERR(mcde->regs)) { 369 dev_err(dev, "no MCDE regs\n"); 370 ret = -EINVAL; 371 goto clk_disable; 372 } 373 374 irq = platform_get_irq(pdev, 0); 375 if (!irq) { 376 ret = -EINVAL; 377 goto clk_disable; 378 } 379 380 ret = devm_request_irq(dev, irq, mcde_irq, 0, "mcde", mcde); 381 if (ret) { 382 dev_err(dev, "failed to request irq %d\n", ret); 383 goto clk_disable; 384 } 385 386 /* 387 * Check hardware revision, we only support U8500v2 version 388 * as this was the only version used for mass market deployment, 389 * but surely you can add more versions if you have them and 390 * need them. 391 */ 392 pid = readl(mcde->regs + MCDE_PID); 393 dev_info(dev, "found MCDE HW revision %d.%d (dev %d, metal fix %d)\n", 394 (pid & MCDE_PID_MAJOR_VERSION_MASK) 395 >> MCDE_PID_MAJOR_VERSION_SHIFT, 396 (pid & MCDE_PID_MINOR_VERSION_MASK) 397 >> MCDE_PID_MINOR_VERSION_SHIFT, 398 (pid & MCDE_PID_DEVELOPMENT_VERSION_MASK) 399 >> MCDE_PID_DEVELOPMENT_VERSION_SHIFT, 400 (pid & MCDE_PID_METALFIX_VERSION_MASK) 401 >> MCDE_PID_METALFIX_VERSION_SHIFT); 402 if (pid != 0x03000800) { 403 dev_err(dev, "unsupported hardware revision\n"); 404 ret = -ENODEV; 405 goto clk_disable; 406 } 407 408 /* Set up the main control, watermark level at 7 */ 409 val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT; 410 /* 24 bits DPI: connect LSB Ch B to D[0:7] */ 411 val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT; 412 /* TV out: connect LSB Ch B to D[8:15] */ 413 val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT; 414 /* Don't care about this muxing */ 415 val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT; 416 /* 24 bits DPI: connect MID Ch B to D[24:31] */ 417 val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT; 418 /* 5: 24 bits DPI: connect MSB Ch B to D[32:39] */ 419 val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT; 420 /* Syncmux bits zero: DPI channel A and B on output pins A and B resp */ 421 writel(val, mcde->regs + MCDE_CONF0); 422 423 /* Enable automatic clock gating */ 424 val = readl(mcde->regs + MCDE_CR); 425 val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN; 426 writel(val, mcde->regs + MCDE_CR); 427 428 /* Clear any pending interrupts */ 429 mcde_display_disable_irqs(mcde); 430 writel(0, mcde->regs + MCDE_IMSCERR); 431 writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR); 432 433 /* Spawn child devices for the DSI ports */ 434 devm_of_platform_populate(dev); 435 436 /* Create something that will match the subdrivers when we bind */ 437 for (i = 0; i < ARRAY_SIZE(mcde_component_drivers); i++) { 438 struct device_driver *drv = &mcde_component_drivers[i]->driver; 439 struct device *p = NULL, *d; 440 441 while ((d = platform_find_device_by_driver(p, drv))) { 442 put_device(p); 443 component_match_add(dev, &match, mcde_compare_dev, d); 444 p = d; 445 } 446 put_device(p); 447 } 448 if (!match) { 449 dev_err(dev, "no matching components\n"); 450 ret = -ENODEV; 451 goto clk_disable; 452 } 453 if (IS_ERR(match)) { 454 dev_err(dev, "could not create component match\n"); 455 ret = PTR_ERR(match); 456 goto clk_disable; 457 } 458 ret = component_master_add_with_match(&pdev->dev, &mcde_drm_comp_ops, 459 match); 460 if (ret) { 461 dev_err(dev, "failed to add component master\n"); 462 goto clk_disable; 463 } 464 return 0; 465 466 clk_disable: 467 clk_disable_unprepare(mcde->mcde_clk); 468 regulator_off: 469 regulator_disable(mcde->vana); 470 regulator_epod_off: 471 regulator_disable(mcde->epod); 472 return ret; 473 474 } 475 476 static int mcde_remove(struct platform_device *pdev) 477 { 478 struct drm_device *drm = platform_get_drvdata(pdev); 479 struct mcde *mcde = to_mcde(drm); 480 481 component_master_del(&pdev->dev, &mcde_drm_comp_ops); 482 clk_disable_unprepare(mcde->mcde_clk); 483 regulator_disable(mcde->vana); 484 regulator_disable(mcde->epod); 485 486 return 0; 487 } 488 489 static const struct of_device_id mcde_of_match[] = { 490 { 491 .compatible = "ste,mcde", 492 }, 493 {}, 494 }; 495 496 static struct platform_driver mcde_driver = { 497 .driver = { 498 .name = "mcde", 499 .of_match_table = of_match_ptr(mcde_of_match), 500 }, 501 .probe = mcde_probe, 502 .remove = mcde_remove, 503 }; 504 505 static struct platform_driver *const component_drivers[] = { 506 &mcde_dsi_driver, 507 }; 508 509 static int __init mcde_drm_register(void) 510 { 511 int ret; 512 513 ret = platform_register_drivers(component_drivers, 514 ARRAY_SIZE(component_drivers)); 515 if (ret) 516 return ret; 517 518 return platform_driver_register(&mcde_driver); 519 } 520 521 static void __exit mcde_drm_unregister(void) 522 { 523 platform_unregister_drivers(component_drivers, 524 ARRAY_SIZE(component_drivers)); 525 platform_driver_unregister(&mcde_driver); 526 } 527 528 module_init(mcde_drm_register); 529 module_exit(mcde_drm_unregister); 530 531 MODULE_ALIAS("platform:mcde-drm"); 532 MODULE_DESCRIPTION(DRIVER_DESC); 533 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 534 MODULE_LICENSE("GPL"); 535