1*f39db26cSSui Jingfeng /* SPDX-License-Identifier: GPL-2.0+ */ 2*f39db26cSSui Jingfeng /* 3*f39db26cSSui Jingfeng * Copyright (C) 2023 Loongson Technology Corporation Limited 4*f39db26cSSui Jingfeng */ 5*f39db26cSSui Jingfeng 6*f39db26cSSui Jingfeng #ifndef __LSDC_REGS_H__ 7*f39db26cSSui Jingfeng #define __LSDC_REGS_H__ 8*f39db26cSSui Jingfeng 9*f39db26cSSui Jingfeng #include <linux/bitops.h> 10*f39db26cSSui Jingfeng #include <linux/types.h> 11*f39db26cSSui Jingfeng 12*f39db26cSSui Jingfeng /* 13*f39db26cSSui Jingfeng * PIXEL PLL Reference clock 14*f39db26cSSui Jingfeng */ 15*f39db26cSSui Jingfeng #define LSDC_PLL_REF_CLK_KHZ 100000 16*f39db26cSSui Jingfeng 17*f39db26cSSui Jingfeng /* 18*f39db26cSSui Jingfeng * Those PLL registers are relative to LSxxxxx_CFG_REG_BASE. xxxxx = 7A1000, 19*f39db26cSSui Jingfeng * 7A2000, 2K2000, 2K1000 etc. 20*f39db26cSSui Jingfeng */ 21*f39db26cSSui Jingfeng 22*f39db26cSSui Jingfeng /* LS7A1000 */ 23*f39db26cSSui Jingfeng 24*f39db26cSSui Jingfeng #define LS7A1000_PIXPLL0_REG 0x04B0 25*f39db26cSSui Jingfeng #define LS7A1000_PIXPLL1_REG 0x04C0 26*f39db26cSSui Jingfeng 27*f39db26cSSui Jingfeng /* The DC, GPU, Graphic Memory Controller share the single gfxpll */ 28*f39db26cSSui Jingfeng #define LS7A1000_PLL_GFX_REG 0x0490 29*f39db26cSSui Jingfeng 30*f39db26cSSui Jingfeng #define LS7A1000_CONF_REG_BASE 0x10010000 31*f39db26cSSui Jingfeng 32*f39db26cSSui Jingfeng /* LS7A2000 */ 33*f39db26cSSui Jingfeng 34*f39db26cSSui Jingfeng #define LS7A2000_PIXPLL0_REG 0x04B0 35*f39db26cSSui Jingfeng #define LS7A2000_PIXPLL1_REG 0x04C0 36*f39db26cSSui Jingfeng 37*f39db26cSSui Jingfeng /* The DC, GPU, Graphic Memory Controller share the single gfxpll */ 38*f39db26cSSui Jingfeng #define LS7A2000_PLL_GFX_REG 0x0490 39*f39db26cSSui Jingfeng 40*f39db26cSSui Jingfeng #define LS7A2000_CONF_REG_BASE 0x10010000 41*f39db26cSSui Jingfeng 42*f39db26cSSui Jingfeng /* For LSDC_CRTCx_CFG_REG */ 43*f39db26cSSui Jingfeng #define CFG_PIX_FMT_MASK GENMASK(2, 0) 44*f39db26cSSui Jingfeng 45*f39db26cSSui Jingfeng enum lsdc_pixel_format { 46*f39db26cSSui Jingfeng LSDC_PF_NONE = 0, 47*f39db26cSSui Jingfeng LSDC_PF_XRGB444 = 1, /* [12 bits] */ 48*f39db26cSSui Jingfeng LSDC_PF_XRGB555 = 2, /* [15 bits] */ 49*f39db26cSSui Jingfeng LSDC_PF_XRGB565 = 3, /* RGB [16 bits] */ 50*f39db26cSSui Jingfeng LSDC_PF_XRGB8888 = 4, /* XRGB [32 bits] */ 51*f39db26cSSui Jingfeng }; 52*f39db26cSSui Jingfeng 53*f39db26cSSui Jingfeng /* 54*f39db26cSSui Jingfeng * Each crtc has two set fb address registers usable, FB_REG_IN_USING bit of 55*f39db26cSSui Jingfeng * LSDC_CRTCx_CFG_REG indicate which fb address register is in using by the 56*f39db26cSSui Jingfeng * CRTC currently. CFG_PAGE_FLIP is used to trigger the switch, the switching 57*f39db26cSSui Jingfeng * will be finished at the very next vblank. Trigger it again if you want to 58*f39db26cSSui Jingfeng * switch back. 59*f39db26cSSui Jingfeng * 60*f39db26cSSui Jingfeng * If FB0_ADDR_REG is in using, we write the address to FB0_ADDR_REG, 61*f39db26cSSui Jingfeng * if FB1_ADDR_REG is in using, we write the address to FB1_ADDR_REG. 62*f39db26cSSui Jingfeng */ 63*f39db26cSSui Jingfeng #define CFG_PAGE_FLIP BIT(7) 64*f39db26cSSui Jingfeng #define CFG_OUTPUT_ENABLE BIT(8) 65*f39db26cSSui Jingfeng #define CFG_HW_CLONE BIT(9) 66*f39db26cSSui Jingfeng /* Indicate witch fb addr reg is in using, currently. read only */ 67*f39db26cSSui Jingfeng #define FB_REG_IN_USING BIT(11) 68*f39db26cSSui Jingfeng #define CFG_GAMMA_EN BIT(12) 69*f39db26cSSui Jingfeng 70*f39db26cSSui Jingfeng /* The DC get soft reset if this bit changed from "1" to "0", active low */ 71*f39db26cSSui Jingfeng #define CFG_RESET_N BIT(20) 72*f39db26cSSui Jingfeng /* If this bit is set, it say that the CRTC stop working anymore, anchored. */ 73*f39db26cSSui Jingfeng #define CRTC_ANCHORED BIT(24) 74*f39db26cSSui Jingfeng 75*f39db26cSSui Jingfeng /* 76*f39db26cSSui Jingfeng * The DMA step of the DC in LS7A2000/LS2K2000 is configurable, 77*f39db26cSSui Jingfeng * setting those bits on ls7a1000 platform make no effect. 78*f39db26cSSui Jingfeng */ 79*f39db26cSSui Jingfeng #define CFG_DMA_STEP_MASK GENMASK(17, 16) 80*f39db26cSSui Jingfeng #define CFG_DMA_STEP_SHIFT 16 81*f39db26cSSui Jingfeng enum lsdc_dma_steps { 82*f39db26cSSui Jingfeng LSDC_DMA_STEP_256_BYTES = 0, 83*f39db26cSSui Jingfeng LSDC_DMA_STEP_128_BYTES = 1, 84*f39db26cSSui Jingfeng LSDC_DMA_STEP_64_BYTES = 2, 85*f39db26cSSui Jingfeng LSDC_DMA_STEP_32_BYTES = 3, 86*f39db26cSSui Jingfeng }; 87*f39db26cSSui Jingfeng 88*f39db26cSSui Jingfeng #define CFG_VALID_BITS_MASK GENMASK(20, 0) 89*f39db26cSSui Jingfeng 90*f39db26cSSui Jingfeng /* For LSDC_CRTCx_HSYNC_REG */ 91*f39db26cSSui Jingfeng #define HSYNC_INV BIT(31) 92*f39db26cSSui Jingfeng #define HSYNC_EN BIT(30) 93*f39db26cSSui Jingfeng #define HSYNC_END_MASK GENMASK(28, 16) 94*f39db26cSSui Jingfeng #define HSYNC_END_SHIFT 16 95*f39db26cSSui Jingfeng #define HSYNC_START_MASK GENMASK(12, 0) 96*f39db26cSSui Jingfeng #define HSYNC_START_SHIFT 0 97*f39db26cSSui Jingfeng 98*f39db26cSSui Jingfeng /* For LSDC_CRTCx_VSYNC_REG */ 99*f39db26cSSui Jingfeng #define VSYNC_INV BIT(31) 100*f39db26cSSui Jingfeng #define VSYNC_EN BIT(30) 101*f39db26cSSui Jingfeng #define VSYNC_END_MASK GENMASK(27, 16) 102*f39db26cSSui Jingfeng #define VSYNC_END_SHIFT 16 103*f39db26cSSui Jingfeng #define VSYNC_START_MASK GENMASK(11, 0) 104*f39db26cSSui Jingfeng #define VSYNC_START_SHIFT 0 105*f39db26cSSui Jingfeng 106*f39db26cSSui Jingfeng /*********** CRTC0 ***********/ 107*f39db26cSSui Jingfeng #define LSDC_CRTC0_CFG_REG 0x1240 108*f39db26cSSui Jingfeng #define LSDC_CRTC0_FB0_ADDR_LO_REG 0x1260 109*f39db26cSSui Jingfeng #define LSDC_CRTC0_FB0_ADDR_HI_REG 0x15A0 110*f39db26cSSui Jingfeng #define LSDC_CRTC0_STRIDE_REG 0x1280 111*f39db26cSSui Jingfeng #define LSDC_CRTC0_FB_ORIGIN_REG 0x1300 112*f39db26cSSui Jingfeng #define LSDC_CRTC0_HDISPLAY_REG 0x1400 113*f39db26cSSui Jingfeng #define LSDC_CRTC0_HSYNC_REG 0x1420 114*f39db26cSSui Jingfeng #define LSDC_CRTC0_VDISPLAY_REG 0x1480 115*f39db26cSSui Jingfeng #define LSDC_CRTC0_VSYNC_REG 0x14A0 116*f39db26cSSui Jingfeng #define LSDC_CRTC0_GAMMA_INDEX_REG 0x14E0 117*f39db26cSSui Jingfeng #define LSDC_CRTC0_GAMMA_DATA_REG 0x1500 118*f39db26cSSui Jingfeng #define LSDC_CRTC0_FB1_ADDR_LO_REG 0x1580 119*f39db26cSSui Jingfeng #define LSDC_CRTC0_FB1_ADDR_HI_REG 0x15C0 120*f39db26cSSui Jingfeng 121*f39db26cSSui Jingfeng /*********** CRTC1 ***********/ 122*f39db26cSSui Jingfeng #define LSDC_CRTC1_CFG_REG 0x1250 123*f39db26cSSui Jingfeng #define LSDC_CRTC1_FB0_ADDR_LO_REG 0x1270 124*f39db26cSSui Jingfeng #define LSDC_CRTC1_FB0_ADDR_HI_REG 0x15B0 125*f39db26cSSui Jingfeng #define LSDC_CRTC1_STRIDE_REG 0x1290 126*f39db26cSSui Jingfeng #define LSDC_CRTC1_FB_ORIGIN_REG 0x1310 127*f39db26cSSui Jingfeng #define LSDC_CRTC1_HDISPLAY_REG 0x1410 128*f39db26cSSui Jingfeng #define LSDC_CRTC1_HSYNC_REG 0x1430 129*f39db26cSSui Jingfeng #define LSDC_CRTC1_VDISPLAY_REG 0x1490 130*f39db26cSSui Jingfeng #define LSDC_CRTC1_VSYNC_REG 0x14B0 131*f39db26cSSui Jingfeng #define LSDC_CRTC1_GAMMA_INDEX_REG 0x14F0 132*f39db26cSSui Jingfeng #define LSDC_CRTC1_GAMMA_DATA_REG 0x1510 133*f39db26cSSui Jingfeng #define LSDC_CRTC1_FB1_ADDR_LO_REG 0x1590 134*f39db26cSSui Jingfeng #define LSDC_CRTC1_FB1_ADDR_HI_REG 0x15D0 135*f39db26cSSui Jingfeng 136*f39db26cSSui Jingfeng /* For LSDC_CRTCx_DVO_CONF_REG */ 137*f39db26cSSui Jingfeng #define PHY_CLOCK_POL BIT(9) 138*f39db26cSSui Jingfeng #define PHY_CLOCK_EN BIT(8) 139*f39db26cSSui Jingfeng #define PHY_DE_POL BIT(1) 140*f39db26cSSui Jingfeng #define PHY_DATA_EN BIT(0) 141*f39db26cSSui Jingfeng 142*f39db26cSSui Jingfeng /*********** DVO0 ***********/ 143*f39db26cSSui Jingfeng #define LSDC_CRTC0_DVO_CONF_REG 0x13C0 144*f39db26cSSui Jingfeng 145*f39db26cSSui Jingfeng /*********** DVO1 ***********/ 146*f39db26cSSui Jingfeng #define LSDC_CRTC1_DVO_CONF_REG 0x13D0 147*f39db26cSSui Jingfeng 148*f39db26cSSui Jingfeng /* 149*f39db26cSSui Jingfeng * All of the DC variants has the hardware which record the scan position 150*f39db26cSSui Jingfeng * of the CRTC, [31:16] : current X position, [15:0] : current Y position 151*f39db26cSSui Jingfeng */ 152*f39db26cSSui Jingfeng #define LSDC_CRTC0_SCAN_POS_REG 0x14C0 153*f39db26cSSui Jingfeng #define LSDC_CRTC1_SCAN_POS_REG 0x14D0 154*f39db26cSSui Jingfeng 155*f39db26cSSui Jingfeng /* 156*f39db26cSSui Jingfeng * LS7A2000 has Sync Deviation register. 157*f39db26cSSui Jingfeng */ 158*f39db26cSSui Jingfeng #define SYNC_DEVIATION_EN BIT(31) 159*f39db26cSSui Jingfeng #define SYNC_DEVIATION_NUM GENMASK(12, 0) 160*f39db26cSSui Jingfeng #define LSDC_CRTC0_SYNC_DEVIATION_REG 0x1B80 161*f39db26cSSui Jingfeng #define LSDC_CRTC1_SYNC_DEVIATION_REG 0x1B90 162*f39db26cSSui Jingfeng 163*f39db26cSSui Jingfeng /* 164*f39db26cSSui Jingfeng * In gross, LSDC_CRTC1_XXX_REG - LSDC_CRTC0_XXX_REG = 0x10, but not all of 165*f39db26cSSui Jingfeng * the registers obey this rule, LSDC_CURSORx_XXX_REG just don't honor this. 166*f39db26cSSui Jingfeng * This is the root cause we can't untangle the code by manpulating offset 167*f39db26cSSui Jingfeng * of the register access simply. Our hardware engineers are lack experiance 168*f39db26cSSui Jingfeng * when they design this... 169*f39db26cSSui Jingfeng */ 170*f39db26cSSui Jingfeng #define CRTC_PIPE_OFFSET 0x10 171*f39db26cSSui Jingfeng 172*f39db26cSSui Jingfeng /* 173*f39db26cSSui Jingfeng * There is only one hardware cursor unit in LS7A1000 and LS2K1000, let 174*f39db26cSSui Jingfeng * CFG_HW_CLONE_EN bit be "1" could eliminate this embarrassment, we made 175*f39db26cSSui Jingfeng * it on custom clone mode application. While LS7A2000 has two hardware 176*f39db26cSSui Jingfeng * cursor unit which is good enough. 177*f39db26cSSui Jingfeng */ 178*f39db26cSSui Jingfeng #define CURSOR_FORMAT_MASK GENMASK(1, 0) 179*f39db26cSSui Jingfeng #define CURSOR_FORMAT_SHIFT 0 180*f39db26cSSui Jingfeng enum lsdc_cursor_format { 181*f39db26cSSui Jingfeng CURSOR_FORMAT_DISABLE = 0, 182*f39db26cSSui Jingfeng CURSOR_FORMAT_MONOCHROME = 1, /* masked */ 183*f39db26cSSui Jingfeng CURSOR_FORMAT_ARGB8888 = 2, /* A8R8G8B8 */ 184*f39db26cSSui Jingfeng }; 185*f39db26cSSui Jingfeng 186*f39db26cSSui Jingfeng /* 187*f39db26cSSui Jingfeng * LS7A1000 and LS2K1000 only support 32x32, LS2K2000 and LS7A2000 support 188*f39db26cSSui Jingfeng * 64x64, but it seems that setting this bit make no harms on LS7A1000, it 189*f39db26cSSui Jingfeng * just don't take effects. 190*f39db26cSSui Jingfeng */ 191*f39db26cSSui Jingfeng #define CURSOR_SIZE_SHIFT 2 192*f39db26cSSui Jingfeng enum lsdc_cursor_size { 193*f39db26cSSui Jingfeng CURSOR_SIZE_32X32 = 0, 194*f39db26cSSui Jingfeng CURSOR_SIZE_64X64 = 1, 195*f39db26cSSui Jingfeng }; 196*f39db26cSSui Jingfeng 197*f39db26cSSui Jingfeng #define CURSOR_LOCATION_SHIFT 4 198*f39db26cSSui Jingfeng enum lsdc_cursor_location { 199*f39db26cSSui Jingfeng CURSOR_ON_CRTC0 = 0, 200*f39db26cSSui Jingfeng CURSOR_ON_CRTC1 = 1, 201*f39db26cSSui Jingfeng }; 202*f39db26cSSui Jingfeng 203*f39db26cSSui Jingfeng #define LSDC_CURSOR0_CFG_REG 0x1520 204*f39db26cSSui Jingfeng #define LSDC_CURSOR0_ADDR_LO_REG 0x1530 205*f39db26cSSui Jingfeng #define LSDC_CURSOR0_ADDR_HI_REG 0x15e0 206*f39db26cSSui Jingfeng #define LSDC_CURSOR0_POSITION_REG 0x1540 /* [31:16] Y, [15:0] X */ 207*f39db26cSSui Jingfeng #define LSDC_CURSOR0_BG_COLOR_REG 0x1550 /* background color */ 208*f39db26cSSui Jingfeng #define LSDC_CURSOR0_FG_COLOR_REG 0x1560 /* foreground color */ 209*f39db26cSSui Jingfeng 210*f39db26cSSui Jingfeng #define LSDC_CURSOR1_CFG_REG 0x1670 211*f39db26cSSui Jingfeng #define LSDC_CURSOR1_ADDR_LO_REG 0x1680 212*f39db26cSSui Jingfeng #define LSDC_CURSOR1_ADDR_HI_REG 0x16e0 213*f39db26cSSui Jingfeng #define LSDC_CURSOR1_POSITION_REG 0x1690 /* [31:16] Y, [15:0] X */ 214*f39db26cSSui Jingfeng #define LSDC_CURSOR1_BG_COLOR_REG 0x16A0 /* background color */ 215*f39db26cSSui Jingfeng #define LSDC_CURSOR1_FG_COLOR_REG 0x16B0 /* foreground color */ 216*f39db26cSSui Jingfeng 217*f39db26cSSui Jingfeng /* 218*f39db26cSSui Jingfeng * DC Interrupt Control Register, 32bit, Address Offset: 1570 219*f39db26cSSui Jingfeng * 220*f39db26cSSui Jingfeng * Bits 15:0 inidicate the interrupt status 221*f39db26cSSui Jingfeng * Bits 31:16 control enable interrupts corresponding to bit 15:0 or not 222*f39db26cSSui Jingfeng * Write 1 to enable, write 0 to disable 223*f39db26cSSui Jingfeng * 224*f39db26cSSui Jingfeng * RF: Read Finished 225*f39db26cSSui Jingfeng * IDBU: Internal Data Buffer Underflow 226*f39db26cSSui Jingfeng * IDBFU: Internal Data Buffer Fatal Underflow 227*f39db26cSSui Jingfeng * CBRF: Cursor Buffer Read Finished Flag, no use. 228*f39db26cSSui Jingfeng * FBRF0: CRTC-0 reading from its framebuffer finished. 229*f39db26cSSui Jingfeng * FBRF1: CRTC-1 reading from its framebuffer finished. 230*f39db26cSSui Jingfeng * 231*f39db26cSSui Jingfeng * +-------+--------------------------+-------+--------+--------+-------+ 232*f39db26cSSui Jingfeng * | 31:27 | 26:16 | 15:11 | 10 | 9 | 8 | 233*f39db26cSSui Jingfeng * +-------+--------------------------+-------+--------+--------+-------+ 234*f39db26cSSui Jingfeng * | N/A | Interrupt Enable Control | N/A | IDBFU0 | IDBFU1 | IDBU0 | 235*f39db26cSSui Jingfeng * +-------+--------------------------+-------+--------+--------+-------+ 236*f39db26cSSui Jingfeng * 237*f39db26cSSui Jingfeng * +-------+-------+-------+------+--------+--------+--------+--------+ 238*f39db26cSSui Jingfeng * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 239*f39db26cSSui Jingfeng * +-------+-------+-------+------+--------+--------+--------+--------+ 240*f39db26cSSui Jingfeng * | IDBU1 | FBRF0 | FBRF1 | CRRF | HSYNC0 | VSYNC0 | HSYNC1 | VSYNC1 | 241*f39db26cSSui Jingfeng * +-------+-------+-------+------+--------+--------+--------+--------+ 242*f39db26cSSui Jingfeng * 243*f39db26cSSui Jingfeng * unfortunately, CRTC0's interrupt is mess with CRTC1's interrupt in one 244*f39db26cSSui Jingfeng * register again. 245*f39db26cSSui Jingfeng */ 246*f39db26cSSui Jingfeng 247*f39db26cSSui Jingfeng #define LSDC_INT_REG 0x1570 248*f39db26cSSui Jingfeng 249*f39db26cSSui Jingfeng #define INT_CRTC0_VSYNC BIT(2) 250*f39db26cSSui Jingfeng #define INT_CRTC0_HSYNC BIT(3) 251*f39db26cSSui Jingfeng #define INT_CRTC0_RF BIT(6) 252*f39db26cSSui Jingfeng #define INT_CRTC0_IDBU BIT(8) 253*f39db26cSSui Jingfeng #define INT_CRTC0_IDBFU BIT(10) 254*f39db26cSSui Jingfeng 255*f39db26cSSui Jingfeng #define INT_CRTC1_VSYNC BIT(0) 256*f39db26cSSui Jingfeng #define INT_CRTC1_HSYNC BIT(1) 257*f39db26cSSui Jingfeng #define INT_CRTC1_RF BIT(5) 258*f39db26cSSui Jingfeng #define INT_CRTC1_IDBU BIT(7) 259*f39db26cSSui Jingfeng #define INT_CRTC1_IDBFU BIT(9) 260*f39db26cSSui Jingfeng 261*f39db26cSSui Jingfeng #define INT_CRTC0_VSYNC_EN BIT(18) 262*f39db26cSSui Jingfeng #define INT_CRTC0_HSYNC_EN BIT(19) 263*f39db26cSSui Jingfeng #define INT_CRTC0_RF_EN BIT(22) 264*f39db26cSSui Jingfeng #define INT_CRTC0_IDBU_EN BIT(24) 265*f39db26cSSui Jingfeng #define INT_CRTC0_IDBFU_EN BIT(26) 266*f39db26cSSui Jingfeng 267*f39db26cSSui Jingfeng #define INT_CRTC1_VSYNC_EN BIT(16) 268*f39db26cSSui Jingfeng #define INT_CRTC1_HSYNC_EN BIT(17) 269*f39db26cSSui Jingfeng #define INT_CRTC1_RF_EN BIT(21) 270*f39db26cSSui Jingfeng #define INT_CRTC1_IDBU_EN BIT(23) 271*f39db26cSSui Jingfeng #define INT_CRTC1_IDBFU_EN BIT(25) 272*f39db26cSSui Jingfeng 273*f39db26cSSui Jingfeng #define INT_STATUS_MASK GENMASK(15, 0) 274*f39db26cSSui Jingfeng 275*f39db26cSSui Jingfeng /* 276*f39db26cSSui Jingfeng * LS7A1000/LS7A2000 have 4 gpios which are used to emulated I2C. 277*f39db26cSSui Jingfeng * They are under control of the LS7A_DC_GPIO_DAT_REG and LS7A_DC_GPIO_DIR_REG 278*f39db26cSSui Jingfeng * register, Those GPIOs has no relationship whth the GPIO hardware on the 279*f39db26cSSui Jingfeng * bridge chip itself. Those offsets are relative to DC register base address 280*f39db26cSSui Jingfeng * 281*f39db26cSSui Jingfeng * LS2k1000 don't have those registers, they use hardware i2c or general GPIO 282*f39db26cSSui Jingfeng * emulated i2c from linux i2c subsystem. 283*f39db26cSSui Jingfeng * 284*f39db26cSSui Jingfeng * GPIO data register, address offset: 0x1650 285*f39db26cSSui Jingfeng * +---------------+-----------+-----------+ 286*f39db26cSSui Jingfeng * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 287*f39db26cSSui Jingfeng * +---------------+-----------+-----------+ 288*f39db26cSSui Jingfeng * | | DVO1 | DVO0 | 289*f39db26cSSui Jingfeng * + N/A +-----------+-----------+ 290*f39db26cSSui Jingfeng * | | SCL | SDA | SCL | SDA | 291*f39db26cSSui Jingfeng * +---------------+-----------+-----------+ 292*f39db26cSSui Jingfeng */ 293*f39db26cSSui Jingfeng #define LS7A_DC_GPIO_DAT_REG 0x1650 294*f39db26cSSui Jingfeng 295*f39db26cSSui Jingfeng /* 296*f39db26cSSui Jingfeng * GPIO Input/Output direction control register, address offset: 0x1660 297*f39db26cSSui Jingfeng */ 298*f39db26cSSui Jingfeng #define LS7A_DC_GPIO_DIR_REG 0x1660 299*f39db26cSSui Jingfeng 300*f39db26cSSui Jingfeng /* 301*f39db26cSSui Jingfeng * LS7A2000 has two built-in HDMI Encoder and one VGA encoder 302*f39db26cSSui Jingfeng */ 303*f39db26cSSui Jingfeng 304*f39db26cSSui Jingfeng /* 305*f39db26cSSui Jingfeng * Number of continuous packets may be present 306*f39db26cSSui Jingfeng * in HDMI hblank and vblank zone, should >= 48 307*f39db26cSSui Jingfeng */ 308*f39db26cSSui Jingfeng #define LSDC_HDMI0_ZONE_REG 0x1700 309*f39db26cSSui Jingfeng #define LSDC_HDMI1_ZONE_REG 0x1710 310*f39db26cSSui Jingfeng 311*f39db26cSSui Jingfeng #define HDMI_H_ZONE_IDLE_SHIFT 0 312*f39db26cSSui Jingfeng #define HDMI_V_ZONE_IDLE_SHIFT 16 313*f39db26cSSui Jingfeng 314*f39db26cSSui Jingfeng /* HDMI Iterface Control Reg */ 315*f39db26cSSui Jingfeng #define HDMI_INTERFACE_EN BIT(0) 316*f39db26cSSui Jingfeng #define HDMI_PACKET_EN BIT(1) 317*f39db26cSSui Jingfeng #define HDMI_AUDIO_EN BIT(2) 318*f39db26cSSui Jingfeng /* 319*f39db26cSSui Jingfeng * Preamble: 320*f39db26cSSui Jingfeng * Immediately preceding each video data period or data island period is the 321*f39db26cSSui Jingfeng * preamble. This is a sequence of eight identical control characters that 322*f39db26cSSui Jingfeng * indicate whether the upcoming data period is a video data period or is a 323*f39db26cSSui Jingfeng * data island. The values of CTL0, CTL1, CTL2, and CTL3 indicate the type of 324*f39db26cSSui Jingfeng * data period that follows. 325*f39db26cSSui Jingfeng */ 326*f39db26cSSui Jingfeng #define HDMI_VIDEO_PREAMBLE_MASK GENMASK(7, 4) 327*f39db26cSSui Jingfeng #define HDMI_VIDEO_PREAMBLE_SHIFT 4 328*f39db26cSSui Jingfeng /* 1: hw i2c, 0: gpio emu i2c, shouldn't put in LSDC_HDMIx_INTF_CTRL_REG */ 329*f39db26cSSui Jingfeng #define HW_I2C_EN BIT(8) 330*f39db26cSSui Jingfeng #define HDMI_CTL_PERIOD_MODE BIT(9) 331*f39db26cSSui Jingfeng #define LSDC_HDMI0_INTF_CTRL_REG 0x1720 332*f39db26cSSui Jingfeng #define LSDC_HDMI1_INTF_CTRL_REG 0x1730 333*f39db26cSSui Jingfeng 334*f39db26cSSui Jingfeng #define HDMI_PHY_EN BIT(0) 335*f39db26cSSui Jingfeng #define HDMI_PHY_RESET_N BIT(1) 336*f39db26cSSui Jingfeng #define HDMI_PHY_TERM_L_EN BIT(8) 337*f39db26cSSui Jingfeng #define HDMI_PHY_TERM_H_EN BIT(9) 338*f39db26cSSui Jingfeng #define HDMI_PHY_TERM_DET_EN BIT(10) 339*f39db26cSSui Jingfeng #define HDMI_PHY_TERM_STATUS BIT(11) 340*f39db26cSSui Jingfeng #define LSDC_HDMI0_PHY_CTRL_REG 0x1800 341*f39db26cSSui Jingfeng #define LSDC_HDMI1_PHY_CTRL_REG 0x1810 342*f39db26cSSui Jingfeng 343*f39db26cSSui Jingfeng /* High level duration need > 1us */ 344*f39db26cSSui Jingfeng #define HDMI_PLL_ENABLE BIT(0) 345*f39db26cSSui Jingfeng #define HDMI_PLL_LOCKED BIT(16) 346*f39db26cSSui Jingfeng /* Bypass the software configured values, using default source from somewhere */ 347*f39db26cSSui Jingfeng #define HDMI_PLL_BYPASS BIT(17) 348*f39db26cSSui Jingfeng 349*f39db26cSSui Jingfeng #define HDMI_PLL_IDF_SHIFT 1 350*f39db26cSSui Jingfeng #define HDMI_PLL_IDF_MASK GENMASK(5, 1) 351*f39db26cSSui Jingfeng #define HDMI_PLL_LF_SHIFT 6 352*f39db26cSSui Jingfeng #define HDMI_PLL_LF_MASK GENMASK(12, 6) 353*f39db26cSSui Jingfeng #define HDMI_PLL_ODF_SHIFT 13 354*f39db26cSSui Jingfeng #define HDMI_PLL_ODF_MASK GENMASK(15, 13) 355*f39db26cSSui Jingfeng #define LSDC_HDMI0_PHY_PLL_REG 0x1820 356*f39db26cSSui Jingfeng #define LSDC_HDMI1_PHY_PLL_REG 0x1830 357*f39db26cSSui Jingfeng 358*f39db26cSSui Jingfeng /* LS7A2000/LS2K2000 has hpd status reg, while the two hdmi's status 359*f39db26cSSui Jingfeng * located at the one register again. 360*f39db26cSSui Jingfeng */ 361*f39db26cSSui Jingfeng #define LSDC_HDMI_HPD_STATUS_REG 0x1BA0 362*f39db26cSSui Jingfeng #define HDMI0_HPD_FLAG BIT(0) 363*f39db26cSSui Jingfeng #define HDMI1_HPD_FLAG BIT(1) 364*f39db26cSSui Jingfeng 365*f39db26cSSui Jingfeng #define LSDC_HDMI0_PHY_CAL_REG 0x18C0 366*f39db26cSSui Jingfeng #define LSDC_HDMI1_PHY_CAL_REG 0x18D0 367*f39db26cSSui Jingfeng 368*f39db26cSSui Jingfeng /* AVI InfoFrame */ 369*f39db26cSSui Jingfeng #define LSDC_HDMI0_AVI_CONTENT0 0x18E0 370*f39db26cSSui Jingfeng #define LSDC_HDMI1_AVI_CONTENT0 0x18D0 371*f39db26cSSui Jingfeng #define LSDC_HDMI0_AVI_CONTENT1 0x1900 372*f39db26cSSui Jingfeng #define LSDC_HDMI1_AVI_CONTENT1 0x1910 373*f39db26cSSui Jingfeng #define LSDC_HDMI0_AVI_CONTENT2 0x1920 374*f39db26cSSui Jingfeng #define LSDC_HDMI1_AVI_CONTENT2 0x1930 375*f39db26cSSui Jingfeng #define LSDC_HDMI0_AVI_CONTENT3 0x1940 376*f39db26cSSui Jingfeng #define LSDC_HDMI1_AVI_CONTENT3 0x1950 377*f39db26cSSui Jingfeng 378*f39db26cSSui Jingfeng /* 1: enable avi infoframe packet, 0: disable avi infoframe packet */ 379*f39db26cSSui Jingfeng #define AVI_PKT_ENABLE BIT(0) 380*f39db26cSSui Jingfeng /* 1: send one every two frame, 0: send one each frame */ 381*f39db26cSSui Jingfeng #define AVI_PKT_SEND_FREQ BIT(1) 382*f39db26cSSui Jingfeng /* 383*f39db26cSSui Jingfeng * 1: write 1 to flush avi reg content0 ~ content3 to the packet to be send, 384*f39db26cSSui Jingfeng * The hardware will clear this bit automatically. 385*f39db26cSSui Jingfeng */ 386*f39db26cSSui Jingfeng #define AVI_PKT_UPDATE BIT(2) 387*f39db26cSSui Jingfeng 388*f39db26cSSui Jingfeng #define LSDC_HDMI0_AVI_INFO_CRTL_REG 0x1960 389*f39db26cSSui Jingfeng #define LSDC_HDMI1_AVI_INFO_CRTL_REG 0x1970 390*f39db26cSSui Jingfeng 391*f39db26cSSui Jingfeng /* 392*f39db26cSSui Jingfeng * LS7A2000 has the hardware which count the number of vblank generated 393*f39db26cSSui Jingfeng */ 394*f39db26cSSui Jingfeng #define LSDC_CRTC0_VSYNC_COUNTER_REG 0x1A00 395*f39db26cSSui Jingfeng #define LSDC_CRTC1_VSYNC_COUNTER_REG 0x1A10 396*f39db26cSSui Jingfeng 397*f39db26cSSui Jingfeng /* 398*f39db26cSSui Jingfeng * LS7A2000 has the audio hardware associate with the HDMI encoder. 399*f39db26cSSui Jingfeng */ 400*f39db26cSSui Jingfeng #define LSDC_HDMI0_AUDIO_PLL_LO_REG 0x1A20 401*f39db26cSSui Jingfeng #define LSDC_HDMI1_AUDIO_PLL_LO_REG 0x1A30 402*f39db26cSSui Jingfeng 403*f39db26cSSui Jingfeng #define LSDC_HDMI0_AUDIO_PLL_HI_REG 0x1A40 404*f39db26cSSui Jingfeng #define LSDC_HDMI1_AUDIO_PLL_HI_REG 0x1A50 405*f39db26cSSui Jingfeng 406*f39db26cSSui Jingfeng #endif 407