1*f39db26cSSui Jingfeng // SPDX-License-Identifier: GPL-2.0+
2*f39db26cSSui Jingfeng /*
3*f39db26cSSui Jingfeng  * Copyright (C) 2023 Loongson Technology Corporation Limited
4*f39db26cSSui Jingfeng  */
5*f39db26cSSui Jingfeng 
6*f39db26cSSui Jingfeng #include "lsdc_drv.h"
7*f39db26cSSui Jingfeng #include "lsdc_probe.h"
8*f39db26cSSui Jingfeng 
9*f39db26cSSui Jingfeng /*
10*f39db26cSSui Jingfeng  * Processor ID (implementation) values for bits 15:8 of the PRID register.
11*f39db26cSSui Jingfeng  */
12*f39db26cSSui Jingfeng #define LOONGSON_CPU_IMP_MASK           0xff00
13*f39db26cSSui Jingfeng #define LOONGSON_CPU_IMP_SHIFT          8
14*f39db26cSSui Jingfeng 
15*f39db26cSSui Jingfeng #define LOONGARCH_CPU_IMP_LS2K1000      0xa0
16*f39db26cSSui Jingfeng #define LOONGARCH_CPU_IMP_LS2K2000      0xb0
17*f39db26cSSui Jingfeng #define LOONGARCH_CPU_IMP_LS3A5000      0xc0
18*f39db26cSSui Jingfeng 
19*f39db26cSSui Jingfeng #define LOONGSON_CPU_MIPS_IMP_LS2K      0x61 /* Loongson 2K Mips series SoC */
20*f39db26cSSui Jingfeng 
21*f39db26cSSui Jingfeng /*
22*f39db26cSSui Jingfeng  * Particular Revision values for bits 7:0 of the PRID register.
23*f39db26cSSui Jingfeng  */
24*f39db26cSSui Jingfeng #define LOONGSON_CPU_REV_MASK           0x00ff
25*f39db26cSSui Jingfeng 
26*f39db26cSSui Jingfeng #define LOONGARCH_CPUCFG_PRID_REG       0x0
27*f39db26cSSui Jingfeng 
28*f39db26cSSui Jingfeng /*
29*f39db26cSSui Jingfeng  * We can achieve fine-grained control with the information about the host.
30*f39db26cSSui Jingfeng  */
31*f39db26cSSui Jingfeng 
loongson_cpu_get_prid(u8 * imp,u8 * rev)32*f39db26cSSui Jingfeng unsigned int loongson_cpu_get_prid(u8 *imp, u8 *rev)
33*f39db26cSSui Jingfeng {
34*f39db26cSSui Jingfeng 	unsigned int prid = 0;
35*f39db26cSSui Jingfeng 
36*f39db26cSSui Jingfeng #if defined(__loongarch__)
37*f39db26cSSui Jingfeng 	__asm__ volatile("cpucfg %0, %1\n\t"
38*f39db26cSSui Jingfeng 			: "=&r"(prid)
39*f39db26cSSui Jingfeng 			: "r"(LOONGARCH_CPUCFG_PRID_REG)
40*f39db26cSSui Jingfeng 			);
41*f39db26cSSui Jingfeng #endif
42*f39db26cSSui Jingfeng 
43*f39db26cSSui Jingfeng #if defined(__mips__)
44*f39db26cSSui Jingfeng 	__asm__ volatile("mfc0\t%0, $15\n\t"
45*f39db26cSSui Jingfeng 			: "=r" (prid)
46*f39db26cSSui Jingfeng 			);
47*f39db26cSSui Jingfeng #endif
48*f39db26cSSui Jingfeng 
49*f39db26cSSui Jingfeng 	if (imp)
50*f39db26cSSui Jingfeng 		*imp = (prid & LOONGSON_CPU_IMP_MASK) >> LOONGSON_CPU_IMP_SHIFT;
51*f39db26cSSui Jingfeng 
52*f39db26cSSui Jingfeng 	if (rev)
53*f39db26cSSui Jingfeng 		*rev = prid & LOONGSON_CPU_REV_MASK;
54*f39db26cSSui Jingfeng 
55*f39db26cSSui Jingfeng 	return prid;
56*f39db26cSSui Jingfeng }
57