1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */ 3 4 #include <linux/interrupt.h> 5 #include <linux/iopoll.h> 6 #include <linux/device.h> 7 #include <linux/slab.h> 8 9 #include <drm/lima_drm.h> 10 11 #include "lima_device.h" 12 #include "lima_gp.h" 13 #include "lima_regs.h" 14 #include "lima_gem.h" 15 #include "lima_vm.h" 16 17 #define gp_write(reg, data) writel(data, ip->iomem + reg) 18 #define gp_read(reg) readl(ip->iomem + reg) 19 20 static irqreturn_t lima_gp_irq_handler(int irq, void *data) 21 { 22 struct lima_ip *ip = data; 23 struct lima_device *dev = ip->dev; 24 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp; 25 struct lima_sched_task *task = pipe->current_task; 26 u32 state = gp_read(LIMA_GP_INT_STAT); 27 u32 status = gp_read(LIMA_GP_STATUS); 28 bool done = false; 29 30 /* for shared irq case */ 31 if (!state) 32 return IRQ_NONE; 33 34 if (state & LIMA_GP_IRQ_MASK_ERROR) { 35 if ((state & LIMA_GP_IRQ_MASK_ERROR) == 36 LIMA_GP_IRQ_PLBU_OUT_OF_MEM) { 37 dev_dbg(dev->dev, "gp out of heap irq status=%x\n", 38 status); 39 } else { 40 dev_err(dev->dev, "gp error irq state=%x status=%x\n", 41 state, status); 42 if (task) 43 task->recoverable = false; 44 } 45 46 /* mask all interrupts before hard reset */ 47 gp_write(LIMA_GP_INT_MASK, 0); 48 49 pipe->error = true; 50 done = true; 51 } else { 52 bool valid = state & (LIMA_GP_IRQ_VS_END_CMD_LST | 53 LIMA_GP_IRQ_PLBU_END_CMD_LST); 54 bool active = status & (LIMA_GP_STATUS_VS_ACTIVE | 55 LIMA_GP_STATUS_PLBU_ACTIVE); 56 done = valid && !active; 57 pipe->error = false; 58 } 59 60 gp_write(LIMA_GP_INT_CLEAR, state); 61 62 if (done) 63 lima_sched_pipe_task_done(pipe); 64 65 return IRQ_HANDLED; 66 } 67 68 static void lima_gp_soft_reset_async(struct lima_ip *ip) 69 { 70 if (ip->data.async_reset) 71 return; 72 73 gp_write(LIMA_GP_INT_MASK, 0); 74 gp_write(LIMA_GP_INT_CLEAR, LIMA_GP_IRQ_RESET_COMPLETED); 75 gp_write(LIMA_GP_CMD, LIMA_GP_CMD_SOFT_RESET); 76 ip->data.async_reset = true; 77 } 78 79 static int lima_gp_soft_reset_async_wait(struct lima_ip *ip) 80 { 81 struct lima_device *dev = ip->dev; 82 int err; 83 u32 v; 84 85 if (!ip->data.async_reset) 86 return 0; 87 88 err = readl_poll_timeout(ip->iomem + LIMA_GP_INT_RAWSTAT, v, 89 v & LIMA_GP_IRQ_RESET_COMPLETED, 90 0, 100); 91 if (err) { 92 dev_err(dev->dev, "gp soft reset time out\n"); 93 return err; 94 } 95 96 gp_write(LIMA_GP_INT_CLEAR, LIMA_GP_IRQ_MASK_ALL); 97 gp_write(LIMA_GP_INT_MASK, LIMA_GP_IRQ_MASK_USED); 98 99 ip->data.async_reset = false; 100 return 0; 101 } 102 103 static int lima_gp_task_validate(struct lima_sched_pipe *pipe, 104 struct lima_sched_task *task) 105 { 106 struct drm_lima_gp_frame *frame = task->frame; 107 u32 *f = frame->frame; 108 (void)pipe; 109 110 if (f[LIMA_GP_VSCL_START_ADDR >> 2] > 111 f[LIMA_GP_VSCL_END_ADDR >> 2] || 112 f[LIMA_GP_PLBUCL_START_ADDR >> 2] > 113 f[LIMA_GP_PLBUCL_END_ADDR >> 2] || 114 f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2] > 115 f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2]) 116 return -EINVAL; 117 118 if (f[LIMA_GP_VSCL_START_ADDR >> 2] == 119 f[LIMA_GP_VSCL_END_ADDR >> 2] && 120 f[LIMA_GP_PLBUCL_START_ADDR >> 2] == 121 f[LIMA_GP_PLBUCL_END_ADDR >> 2]) 122 return -EINVAL; 123 124 return 0; 125 } 126 127 static void lima_gp_task_run(struct lima_sched_pipe *pipe, 128 struct lima_sched_task *task) 129 { 130 struct lima_ip *ip = pipe->processor[0]; 131 struct drm_lima_gp_frame *frame = task->frame; 132 u32 *f = frame->frame; 133 u32 cmd = 0; 134 int i; 135 136 /* update real heap buffer size for GP */ 137 for (i = 0; i < task->num_bos; i++) { 138 struct lima_bo *bo = task->bos[i]; 139 140 if (bo->heap_size && 141 lima_vm_get_va(task->vm, bo) == 142 f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2]) { 143 f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2] = 144 f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2] + 145 bo->heap_size; 146 task->recoverable = true; 147 task->heap = bo; 148 break; 149 } 150 } 151 152 if (f[LIMA_GP_VSCL_START_ADDR >> 2] != 153 f[LIMA_GP_VSCL_END_ADDR >> 2]) 154 cmd |= LIMA_GP_CMD_START_VS; 155 if (f[LIMA_GP_PLBUCL_START_ADDR >> 2] != 156 f[LIMA_GP_PLBUCL_END_ADDR >> 2]) 157 cmd |= LIMA_GP_CMD_START_PLBU; 158 159 /* before any hw ops, wait last success task async soft reset */ 160 lima_gp_soft_reset_async_wait(ip); 161 162 for (i = 0; i < LIMA_GP_FRAME_REG_NUM; i++) 163 writel(f[i], ip->iomem + LIMA_GP_VSCL_START_ADDR + i * 4); 164 165 gp_write(LIMA_GP_CMD, LIMA_GP_CMD_UPDATE_PLBU_ALLOC); 166 gp_write(LIMA_GP_CMD, cmd); 167 } 168 169 static int lima_gp_hard_reset_poll(struct lima_ip *ip) 170 { 171 gp_write(LIMA_GP_PERF_CNT_0_LIMIT, 0xC01A0000); 172 return gp_read(LIMA_GP_PERF_CNT_0_LIMIT) == 0xC01A0000; 173 } 174 175 static int lima_gp_hard_reset(struct lima_ip *ip) 176 { 177 struct lima_device *dev = ip->dev; 178 int ret; 179 180 gp_write(LIMA_GP_PERF_CNT_0_LIMIT, 0xC0FFE000); 181 gp_write(LIMA_GP_INT_MASK, 0); 182 gp_write(LIMA_GP_CMD, LIMA_GP_CMD_RESET); 183 ret = lima_poll_timeout(ip, lima_gp_hard_reset_poll, 10, 100); 184 if (ret) { 185 dev_err(dev->dev, "gp hard reset timeout\n"); 186 return ret; 187 } 188 189 gp_write(LIMA_GP_PERF_CNT_0_LIMIT, 0); 190 gp_write(LIMA_GP_INT_CLEAR, LIMA_GP_IRQ_MASK_ALL); 191 gp_write(LIMA_GP_INT_MASK, LIMA_GP_IRQ_MASK_USED); 192 return 0; 193 } 194 195 static void lima_gp_task_fini(struct lima_sched_pipe *pipe) 196 { 197 lima_gp_soft_reset_async(pipe->processor[0]); 198 } 199 200 static void lima_gp_task_error(struct lima_sched_pipe *pipe) 201 { 202 struct lima_ip *ip = pipe->processor[0]; 203 204 dev_err(ip->dev->dev, "gp task error int_state=%x status=%x\n", 205 gp_read(LIMA_GP_INT_STAT), gp_read(LIMA_GP_STATUS)); 206 207 lima_gp_hard_reset(ip); 208 } 209 210 static void lima_gp_task_mmu_error(struct lima_sched_pipe *pipe) 211 { 212 lima_sched_pipe_task_done(pipe); 213 } 214 215 static void lima_gp_task_mask_irq(struct lima_sched_pipe *pipe) 216 { 217 struct lima_ip *ip = pipe->processor[0]; 218 219 gp_write(LIMA_GP_INT_MASK, 0); 220 } 221 222 static int lima_gp_task_recover(struct lima_sched_pipe *pipe) 223 { 224 struct lima_ip *ip = pipe->processor[0]; 225 struct lima_sched_task *task = pipe->current_task; 226 struct drm_lima_gp_frame *frame = task->frame; 227 u32 *f = frame->frame; 228 size_t fail_size = 229 f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2] - 230 f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2]; 231 232 if (fail_size == task->heap->heap_size) { 233 int ret; 234 235 ret = lima_heap_alloc(task->heap, task->vm); 236 if (ret < 0) 237 return ret; 238 } 239 240 gp_write(LIMA_GP_INT_MASK, LIMA_GP_IRQ_MASK_USED); 241 /* Resume from where we stopped, i.e. new start is old end */ 242 gp_write(LIMA_GP_PLBU_ALLOC_START_ADDR, 243 f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2]); 244 f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2] = 245 f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2] + task->heap->heap_size; 246 gp_write(LIMA_GP_PLBU_ALLOC_END_ADDR, 247 f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2]); 248 gp_write(LIMA_GP_CMD, LIMA_GP_CMD_UPDATE_PLBU_ALLOC); 249 return 0; 250 } 251 252 static void lima_gp_print_version(struct lima_ip *ip) 253 { 254 u32 version, major, minor; 255 char *name; 256 257 version = gp_read(LIMA_GP_VERSION); 258 major = (version >> 8) & 0xFF; 259 minor = version & 0xFF; 260 switch (version >> 16) { 261 case 0xA07: 262 name = "mali200"; 263 break; 264 case 0xC07: 265 name = "mali300"; 266 break; 267 case 0xB07: 268 name = "mali400"; 269 break; 270 case 0xD07: 271 name = "mali450"; 272 break; 273 default: 274 name = "unknown"; 275 break; 276 } 277 dev_info(ip->dev->dev, "%s - %s version major %d minor %d\n", 278 lima_ip_name(ip), name, major, minor); 279 } 280 281 static struct kmem_cache *lima_gp_task_slab; 282 static int lima_gp_task_slab_refcnt; 283 284 static int lima_gp_hw_init(struct lima_ip *ip) 285 { 286 ip->data.async_reset = false; 287 lima_gp_soft_reset_async(ip); 288 return lima_gp_soft_reset_async_wait(ip); 289 } 290 291 int lima_gp_resume(struct lima_ip *ip) 292 { 293 return lima_gp_hw_init(ip); 294 } 295 296 void lima_gp_suspend(struct lima_ip *ip) 297 { 298 299 } 300 301 int lima_gp_init(struct lima_ip *ip) 302 { 303 struct lima_device *dev = ip->dev; 304 int err; 305 306 lima_gp_print_version(ip); 307 308 err = lima_gp_hw_init(ip); 309 if (err) 310 return err; 311 312 err = devm_request_irq(dev->dev, ip->irq, lima_gp_irq_handler, 313 IRQF_SHARED, lima_ip_name(ip), ip); 314 if (err) { 315 dev_err(dev->dev, "gp %s fail to request irq\n", 316 lima_ip_name(ip)); 317 return err; 318 } 319 320 dev->gp_version = gp_read(LIMA_GP_VERSION); 321 322 return 0; 323 } 324 325 void lima_gp_fini(struct lima_ip *ip) 326 { 327 struct lima_device *dev = ip->dev; 328 329 devm_free_irq(dev->dev, ip->irq, ip); 330 } 331 332 int lima_gp_pipe_init(struct lima_device *dev) 333 { 334 int frame_size = sizeof(struct drm_lima_gp_frame); 335 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp; 336 337 if (!lima_gp_task_slab) { 338 lima_gp_task_slab = kmem_cache_create_usercopy( 339 "lima_gp_task", sizeof(struct lima_sched_task) + frame_size, 340 0, SLAB_HWCACHE_ALIGN, sizeof(struct lima_sched_task), 341 frame_size, NULL); 342 if (!lima_gp_task_slab) 343 return -ENOMEM; 344 } 345 lima_gp_task_slab_refcnt++; 346 347 pipe->frame_size = frame_size; 348 pipe->task_slab = lima_gp_task_slab; 349 350 pipe->task_validate = lima_gp_task_validate; 351 pipe->task_run = lima_gp_task_run; 352 pipe->task_fini = lima_gp_task_fini; 353 pipe->task_error = lima_gp_task_error; 354 pipe->task_mmu_error = lima_gp_task_mmu_error; 355 pipe->task_recover = lima_gp_task_recover; 356 pipe->task_mask_irq = lima_gp_task_mask_irq; 357 358 return 0; 359 } 360 361 void lima_gp_pipe_fini(struct lima_device *dev) 362 { 363 if (!--lima_gp_task_slab_refcnt) { 364 kmem_cache_destroy(lima_gp_task_slab); 365 lima_gp_task_slab = NULL; 366 } 367 } 368