1 /* SPDX-License-Identifier: GPL-2.0-only 2 * 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #ifndef __KMB_REGS_H__ 7 #define __KMB_REGS_H__ 8 9 /*************************************************************************** 10 * LCD controller control register defines 11 ***************************************************************************/ 12 #define LCD_CONTROL (0x4 * 0x000) 13 #define LCD_CTRL_PROGRESSIVE (0 << 0) 14 #define LCD_CTRL_INTERLACED BIT(0) 15 #define LCD_CTRL_ENABLE BIT(1) 16 #define LCD_CTRL_VL1_ENABLE BIT(2) 17 #define LCD_CTRL_VL2_ENABLE BIT(3) 18 #define LCD_CTRL_GL1_ENABLE BIT(4) 19 #define LCD_CTRL_GL2_ENABLE BIT(5) 20 #define LCD_CTRL_ALPHA_BLEND_VL1 (0 << 6) 21 #define LCD_CTRL_ALPHA_BLEND_VL2 BIT(6) 22 #define LCD_CTRL_ALPHA_BLEND_GL1 (2 << 6) 23 #define LCD_CTRL_ALPHA_BLEND_GL2 (3 << 6) 24 #define LCD_CTRL_ALPHA_TOP_VL1 (0 << 8) 25 #define LCD_CTRL_ALPHA_TOP_VL2 BIT(8) 26 #define LCD_CTRL_ALPHA_TOP_GL1 (2 << 8) 27 #define LCD_CTRL_ALPHA_TOP_GL2 (3 << 8) 28 #define LCD_CTRL_ALPHA_MIDDLE_VL1 (0 << 10) 29 #define LCD_CTRL_ALPHA_MIDDLE_VL2 BIT(10) 30 #define LCD_CTRL_ALPHA_MIDDLE_GL1 (2 << 10) 31 #define LCD_CTRL_ALPHA_MIDDLE_GL2 (3 << 10) 32 #define LCD_CTRL_ALPHA_BOTTOM_VL1 (0 << 12) 33 #define LCD_CTRL_ALPHA_BOTTOM_VL2 BIT(12) 34 #define LCD_CTRL_ALPHA_BOTTOM_GL1 (2 << 12) 35 #define LCD_CTRL_ALPHA_BOTTOM_GL2 (3 << 12) 36 #define LCD_CTRL_TIM_GEN_ENABLE BIT(14) 37 #define LCD_CTRL_CONTINUOUS (0 << 15) 38 #define LCD_CTRL_ONE_SHOT BIT(15) 39 #define LCD_CTRL_PWM0_EN BIT(16) 40 #define LCD_CTRL_PWM1_EN BIT(17) 41 #define LCD_CTRL_PWM2_EN BIT(18) 42 #define LCD_CTRL_OUTPUT_DISABLED (0 << 19) 43 #define LCD_CTRL_OUTPUT_ENABLED BIT(19) 44 #define LCD_CTRL_BPORCH_ENABLE BIT(21) 45 #define LCD_CTRL_FPORCH_ENABLE BIT(22) 46 #define LCD_CTRL_PIPELINE_DMA BIT(28) 47 #define LCD_CTRL_VHSYNC_IDLE_LVL BIT(31) 48 49 /* interrupts */ 50 #define LCD_INT_STATUS (0x4 * 0x001) 51 #define LCD_INT_EOF BIT(0) 52 #define LCD_INT_LINE_CMP BIT(1) 53 #define LCD_INT_VERT_COMP BIT(2) 54 #define LAYER0_DMA_DONE BIT(3) 55 #define LAYER0_DMA_IDLE BIT(4) 56 #define LAYER0_DMA_FIFO_OVERFLOW BIT(5) 57 #define LAYER0_DMA_FIFO_UNDERFLOW BIT(6) 58 #define LAYER0_DMA_CB_FIFO_OVERFLOW BIT(7) 59 #define LAYER0_DMA_CB_FIFO_UNDERFLOW BIT(8) 60 #define LAYER0_DMA_CR_FIFO_OVERFLOW BIT(9) 61 #define LAYER0_DMA_CR_FIFO_UNDERFLOW BIT(10) 62 #define LAYER1_DMA_DONE BIT(11) 63 #define LAYER1_DMA_IDLE BIT(12) 64 #define LAYER1_DMA_FIFO_OVERFLOW BIT(13) 65 #define LAYER1_DMA_FIFO_UNDERFLOW BIT(14) 66 #define LAYER1_DMA_CB_FIFO_OVERFLOW BIT(15) 67 #define LAYER1_DMA_CB_FIFO_UNDERFLOW BIT(16) 68 #define LAYER1_DMA_CR_FIFO_OVERFLOW BIT(17) 69 #define LAYER1_DMA_CR_FIFO_UNDERFLOW BIT(18) 70 #define LAYER2_DMA_DONE BIT(19) 71 #define LAYER2_DMA_IDLE BIT(20) 72 #define LAYER2_DMA_FIFO_OVERFLOW BIT(21) 73 #define LAYER2_DMA_FIFO_UNDERFLOW BIT(22) 74 #define LAYER3_DMA_DONE BIT(23) 75 #define LAYER3_DMA_IDLE BIT(24) 76 #define LAYER3_DMA_FIFO_OVERFLOW BIT(25) 77 #define LAYER3_DMA_FIFO_UNDERFLOW BIT(26) 78 #define LCD_INT_LAYER (0x07fffff8) 79 #define LCD_INT_ENABLE (0x4 * 0x002) 80 #define LCD_INT_CLEAR (0x4 * 0x003) 81 #define LCD_LINE_COUNT (0x4 * 0x004) 82 #define LCD_LINE_COMPARE (0x4 * 0x005) 83 #define LCD_VSTATUS (0x4 * 0x006) 84 85 /*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal 86 * interval interrupt 87 */ 88 /* BITS 13 and 14 */ 89 #define LCD_VSTATUS_COMPARE (0x4 * 0x007) 90 #define LCD_VSTATUS_VERTICAL_STATUS_MASK (3 << 13) 91 #define LCD_VSTATUS_COMPARE_VSYNC (0 << 13) 92 #define LCD_VSTATUS_COMPARE_BACKPORCH BIT(13) 93 #define LCD_VSTATUS_COMPARE_ACTIVE (2 << 13) 94 #define LCD_VSTATUS_COMPARE_FRONT_PORCH (3 << 13) 95 96 #define LCD_SCREEN_WIDTH (0x4 * 0x008) 97 #define LCD_SCREEN_HEIGHT (0x4 * 0x009) 98 #define LCD_FIELD_INT_CFG (0x4 * 0x00a) 99 #define LCD_FIFO_FLUSH (0x4 * 0x00b) 100 #define LCD_BG_COLOUR_LS (0x4 * 0x00c) 101 #define LCD_BG_COLOUR_MS (0x4 * 0x00d) 102 #define LCD_RAM_CFG (0x4 * 0x00e) 103 104 /**************************************************************************** 105 * LCD controller Layer config register 106 ***************************************************************************/ 107 #define LCD_LAYER0_CFG (0x4 * 0x100) 108 #define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400 * (N))) 109 #define LCD_LAYER_SCALE_H BIT(1) 110 #define LCD_LAYER_SCALE_V BIT(2) 111 #define LCD_LAYER_SCALE_H_V (LCD_LAYER_SCALE_H | \ 112 LCD_LAYER_SCALE_V) 113 #define LCD_LAYER_CSC_EN BIT(3) 114 #define LCD_LAYER_ALPHA_STATIC BIT(4) 115 #define LCD_LAYER_ALPHA_EMBED BIT(5) 116 #define LCD_LAYER_ALPHA_COMBI (LCD_LAYER_ALPHA_STATIC | \ 117 LCD_LAYER_ALPHA_EMBED) 118 /* RGB multiplied with alpha */ 119 #define LCD_LAYER_ALPHA_PREMULT BIT(6) 120 #define LCD_LAYER_INVERT_COL BIT(7) 121 #define LCD_LAYER_TRANSPARENT_EN BIT(8) 122 #define LCD_LAYER_FORMAT_YCBCR444PLAN (0 << 9) 123 #define LCD_LAYER_FORMAT_YCBCR422PLAN BIT(9) 124 #define LCD_LAYER_FORMAT_YCBCR420PLAN (2 << 9) 125 #define LCD_LAYER_FORMAT_RGB888PLAN (3 << 9) 126 #define LCD_LAYER_FORMAT_YCBCR444LIN (4 << 9) 127 #define LCD_LAYER_FORMAT_YCBCR422LIN (5 << 9) 128 #define LCD_LAYER_FORMAT_RGB888 (6 << 9) 129 #define LCD_LAYER_FORMAT_RGBA8888 (7 << 9) 130 #define LCD_LAYER_FORMAT_RGBX8888 (8 << 9) 131 #define LCD_LAYER_FORMAT_RGB565 (9 << 9) 132 #define LCD_LAYER_FORMAT_RGBA1555 (0xa << 9) 133 #define LCD_LAYER_FORMAT_XRGB1555 (0xb << 9) 134 #define LCD_LAYER_FORMAT_RGB444 (0xc << 9) 135 #define LCD_LAYER_FORMAT_RGBA4444 (0xd << 9) 136 #define LCD_LAYER_FORMAT_RGBX4444 (0xe << 9) 137 #define LCD_LAYER_FORMAT_RGB332 (0xf << 9) 138 #define LCD_LAYER_FORMAT_RGBA3328 (0x10 << 9) 139 #define LCD_LAYER_FORMAT_RGBX3328 (0x11 << 9) 140 #define LCD_LAYER_FORMAT_CLUT (0x12 << 9) 141 #define LCD_LAYER_FORMAT_NV12 (0x1c << 9) 142 #define LCD_LAYER_PLANAR_STORAGE BIT(14) 143 #define LCD_LAYER_8BPP (0 << 15) 144 #define LCD_LAYER_16BPP BIT(15) 145 #define LCD_LAYER_24BPP (2 << 15) 146 #define LCD_LAYER_32BPP (3 << 15) 147 #define LCD_LAYER_Y_ORDER BIT(17) 148 #define LCD_LAYER_CRCB_ORDER BIT(18) 149 #define LCD_LAYER_BGR_ORDER BIT(19) 150 #define LCD_LAYER_LUT_2ENT (0 << 20) 151 #define LCD_LAYER_LUT_4ENT BIT(20) 152 #define LCD_LAYER_LUT_16ENT (2 << 20) 153 #define LCD_LAYER_NO_FLIP (0 << 22) 154 #define LCD_LAYER_FLIP_V BIT(22) 155 #define LCD_LAYER_FLIP_H (2 << 22) 156 #define LCD_LAYER_ROT_R90 (3 << 22) 157 #define LCD_LAYER_ROT_L90 (4 << 22) 158 #define LCD_LAYER_ROT_180 (5 << 22) 159 #define LCD_LAYER_FIFO_00 (0 << 25) 160 #define LCD_LAYER_FIFO_25 BIT(25) 161 #define LCD_LAYER_FIFO_50 (2 << 25) 162 #define LCD_LAYER_FIFO_100 (3 << 25) 163 #define LCD_LAYER_INTERLEAVE_DIS (0 << 27) 164 #define LCD_LAYER_INTERLEAVE_V BIT(27) 165 #define LCD_LAYER_INTERLEAVE_H (2 << 27) 166 #define LCD_LAYER_INTERLEAVE_CH (3 << 27) 167 #define LCD_LAYER_INTERLEAVE_V_SUB (4 << 27) 168 #define LCD_LAYER_INTERLEAVE_H_SUB (5 << 27) 169 #define LCD_LAYER_INTERLEAVE_CH_SUB (6 << 27) 170 #define LCD_LAYER_INTER_POS_EVEN (0 << 30) 171 #define LCD_LAYER_INTER_POS_ODD BIT(30) 172 173 #define LCD_LAYER0_COL_START (0x4 * 0x101) 174 #define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400 * (N))) 175 #define LCD_LAYER0_ROW_START (0x4 * 0x102) 176 #define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400 * (N))) 177 #define LCD_LAYER0_WIDTH (0x4 * 0x103) 178 #define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400 * (N))) 179 #define LCD_LAYER0_HEIGHT (0x4 * 0x104) 180 #define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400 * (N))) 181 #define LCD_LAYER0_SCALE_CFG (0x4 * 0x105) 182 #define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400 * (N))) 183 #define LCD_LAYER0_ALPHA (0x4 * 0x106) 184 #define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400 * (N))) 185 #define LCD_LAYER0_INV_COLOUR_LS (0x4 * 0x107) 186 #define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + \ 187 (0x400 * (N))) 188 #define LCD_LAYER0_INV_COLOUR_MS (0x4 * 0x108) 189 #define LCD_LAYERn_INV_COLOUR_MS(N) (LCD_LAYER0_INV_COLOUR_MS + \ 190 (0x400 * (N))) 191 #define LCD_LAYER0_TRANS_COLOUR_LS (0x4 * 0x109) 192 #define LCD_LAYERn_TRANS_COLOUR_LS(N) (LCD_LAYER0_TRANS_COLOUR_LS + \ 193 (0x400 * (N))) 194 #define LCD_LAYER0_TRANS_COLOUR_MS (0x4 * 0x10a) 195 #define LCD_LAYERn_TRANS_COLOUR_MS(N) (LCD_LAYER0_TRANS_COLOUR_MS + \ 196 (0x400 * (N))) 197 #define LCD_LAYER0_CSC_COEFF11 (0x4 * 0x10b) 198 #define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400 * (N))) 199 #define LCD_LAYER0_CSC_COEFF12 (0x4 * 0x10c) 200 #define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400 * (N))) 201 #define LCD_LAYER0_CSC_COEFF13 (0x4 * 0x10d) 202 #define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400 * (N))) 203 #define LCD_LAYER0_CSC_COEFF21 (0x4 * 0x10e) 204 #define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400 * (N))) 205 #define LCD_LAYER0_CSC_COEFF22 (0x4 * 0x10f) 206 #define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400 * (N))) 207 #define LCD_LAYER0_CSC_COEFF23 (0x4 * 0x110) 208 #define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400 * (N))) 209 #define LCD_LAYER0_CSC_COEFF31 (0x4 * 0x111) 210 #define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400 * (N))) 211 #define LCD_LAYER0_CSC_COEFF32 (0x4 * 0x112) 212 #define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400 * (N))) 213 #define LCD_LAYER0_CSC_COEFF33 (0x4 * 0x113) 214 #define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400 * (N))) 215 #define LCD_LAYER0_CSC_OFF1 (0x4 * 0x114) 216 #define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400 * (N))) 217 #define LCD_LAYER0_CSC_OFF2 (0x4 * 0x115) 218 #define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400 * (N))) 219 #define LCD_LAYER0_CSC_OFF3 (0x4 * 0x116) 220 #define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400 * (N))) 221 222 /* LCD controller Layer DMA config register */ 223 #define LCD_LAYER0_DMA_CFG (0x4 * 0x117) 224 #define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + \ 225 (0x400 * (N))) 226 #define LCD_DMA_LAYER_ENABLE BIT(0) 227 #define LCD_DMA_LAYER_STATUS BIT(1) 228 #define LCD_DMA_LAYER_AUTO_UPDATE BIT(2) 229 #define LCD_DMA_LAYER_CONT_UPDATE BIT(3) 230 #define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (LCD_DMA_LAYER_AUTO_UPDATE \ 231 | LCD_DMA_LAYER_CONT_UPDATE) 232 #define LCD_DMA_LAYER_FIFO_ADR_MODE BIT(4) 233 #define LCD_DMA_LAYER_AXI_BURST_1 BIT(5) 234 #define LCD_DMA_LAYER_AXI_BURST_2 (2 << 5) 235 #define LCD_DMA_LAYER_AXI_BURST_3 (3 << 5) 236 #define LCD_DMA_LAYER_AXI_BURST_4 (4 << 5) 237 #define LCD_DMA_LAYER_AXI_BURST_5 (5 << 5) 238 #define LCD_DMA_LAYER_AXI_BURST_6 (6 << 5) 239 #define LCD_DMA_LAYER_AXI_BURST_7 (7 << 5) 240 #define LCD_DMA_LAYER_AXI_BURST_8 (8 << 5) 241 #define LCD_DMA_LAYER_AXI_BURST_9 (9 << 5) 242 #define LCD_DMA_LAYER_AXI_BURST_10 (0xa << 5) 243 #define LCD_DMA_LAYER_AXI_BURST_11 (0xb << 5) 244 #define LCD_DMA_LAYER_AXI_BURST_12 (0xc << 5) 245 #define LCD_DMA_LAYER_AXI_BURST_13 (0xd << 5) 246 #define LCD_DMA_LAYER_AXI_BURST_14 (0xe << 5) 247 #define LCD_DMA_LAYER_AXI_BURST_15 (0xf << 5) 248 #define LCD_DMA_LAYER_AXI_BURST_16 (0x10 << 5) 249 #define LCD_DMA_LAYER_VSTRIDE_EN BIT(10) 250 251 #define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) 252 #define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR \ 253 + (0x400 * (N))) 254 #define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119) 255 #define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW \ 256 + (0x400 * (N))) 257 #define LCD_LAYER0_DMA_LEN (0x4 * 0x11a) 258 #define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + \ 259 (0x400 * (N))) 260 #define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b) 261 #define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + \ 262 (0x400 * (N))) 263 #define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c) 264 #define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + \ 265 (0x400 * (N))) 266 #define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d) 267 #define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + \ 268 (0x400 * (N))) 269 #define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e) 270 #define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE +\ 271 (0x400 * (N))) 272 #define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f) 273 #define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + \ 274 (0x400 * (N))) 275 #define LCD_LAYER0_CFG2 (0x4 * 0x120) 276 #define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400 * (N))) 277 #define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) 278 #define LCD_LAYERn_DMA_START_CB_ADR(N) (LCD_LAYER0_DMA_START_CB_ADR + \ 279 (0x20 * (N))) 280 #define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) 281 #define LCD_LAYERn_DMA_START_CB_SHADOW(N) (LCD_LAYER0_DMA_START_CB_SHADOW\ 282 + (0x20 * (N))) 283 #define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) 284 #define LCD_LAYERn_DMA_CB_LINE_WIDTH(N) (LCD_LAYER0_DMA_CB_LINE_WIDTH +\ 285 (0x20 * (N))) 286 #define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) 287 #define LCD_LAYERn_DMA_CB_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CB_LINE_VSTRIDE\ 288 + (0x20 * (N))) 289 #define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) 290 #define LCD_LAYERn_DMA_START_CR_ADR(N) (LCD_LAYER0_DMA_START_CR_ADR + \ 291 (0x20 * (N))) 292 #define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) 293 #define LCD_LAYERn_DMA_START_CR_SHADOW(N) \ 294 (LCD_LAYER0_DMA_START_CR_SHADOW\ 295 + (0x20 * (N))) 296 #define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) 297 #define LCD_LAYERn_DMA_CR_LINE_WIDTH(N) (LCD_LAYER0_DMA_CR_LINE_WIDTH +\ 298 (0x20 * (N))) 299 #define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) 300 #define LCD_LAYERn_DMA_CR_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CR_LINE_VSTRIDE\ 301 + (0x20 * (N))) 302 #define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) 303 #define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) 304 #define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) 305 #define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b) 306 #define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c) 307 #define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d) 308 #define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e) 309 #define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f) 310 311 /**************************************************************************** 312 * LCD controller output format register defines 313 ***************************************************************************/ 314 #define LCD_OUT_FORMAT_CFG (0x4 * 0x800) 315 #define LCD_OUTF_FORMAT_RGB121212 (0x00) 316 #define LCD_OUTF_FORMAT_RGB101010 (0x01) 317 #define LCD_OUTF_FORMAT_RGB888 (0x02) 318 #define LCD_OUTF_FORMAT_RGB666 (0x03) 319 #define LCD_OUTF_FORMAT_RGB565 (0x04) 320 #define LCD_OUTF_FORMAT_RGB444 (0x05) 321 #define LCD_OUTF_FORMAT_MRGB121212 (0x10) 322 #define LCD_OUTF_FORMAT_MRGB101010 (0x11) 323 #define LCD_OUTF_FORMAT_MRGB888 (0x12) 324 #define LCD_OUTF_FORMAT_MRGB666 (0x13) 325 #define LCD_OUTF_FORMAT_MRGB565 (0x14) 326 #define LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08) 327 #define LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09) 328 #define LCD_OUTF_FORMAT_YCBCR420_8B (0x0A) 329 #define LCD_OUTF_FORMAT_YCBCR420_10B (0x0B) 330 #define LCD_OUTF_FORMAT_YCBCR420_12B (0x0C) 331 #define LCD_OUTF_FORMAT_YCBCR422_8B (0x0D) 332 #define LCD_OUTF_FORMAT_YCBCR422_10B (0x0E) 333 #define LCD_OUTF_FORMAT_YCBCR444 (0x0F) 334 #define LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18) 335 #define LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19) 336 #define LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A) 337 #define LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B) 338 #define LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C) 339 #define LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D) 340 #define LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E) 341 #define LCD_OUTF_FORMAT_MYCBCR444 (0x1F) 342 #define LCD_OUTF_BGR_ORDER BIT(5) 343 #define LCD_OUTF_Y_ORDER BIT(6) 344 #define LCD_OUTF_CRCB_ORDER BIT(7) 345 #define LCD_OUTF_SYNC_MODE BIT(11) 346 #define LCD_OUTF_RGB_CONV_MODE BIT(14) 347 #define LCD_OUTF_MIPI_RGB_MODE BIT(18) 348 349 #define LCD_HSYNC_WIDTH (0x4 * 0x801) 350 #define LCD_H_BACKPORCH (0x4 * 0x802) 351 #define LCD_H_ACTIVEWIDTH (0x4 * 0x803) 352 #define LCD_H_FRONTPORCH (0x4 * 0x804) 353 #define LCD_VSYNC_WIDTH (0x4 * 0x805) 354 #define LCD_V_BACKPORCH (0x4 * 0x806) 355 #define LCD_V_ACTIVEHEIGHT (0x4 * 0x807) 356 #define LCD_V_FRONTPORCH (0x4 * 0x808) 357 #define LCD_VSYNC_START (0x4 * 0x809) 358 #define LCD_VSYNC_END (0x4 * 0x80a) 359 #define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b) 360 #define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c) 361 #define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d) 362 #define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e) 363 #define LCD_VSYNC_START_EVEN (0x4 * 0x80f) 364 #define LCD_VSYNC_END_EVEN (0x4 * 0x810) 365 #define LCD_TIMING_GEN_TRIG (0x4 * 0x811) 366 #define LCD_PWM0_CTRL (0x4 * 0x812) 367 #define LCD_PWM0_RPT_LEADIN (0x4 * 0x813) 368 #define LCD_PWM0_HIGH_LOW (0x4 * 0x814) 369 #define LCD_PWM1_CTRL (0x4 * 0x815) 370 #define LCD_PWM1_RPT_LEADIN (0x4 * 0x816) 371 #define LCD_PWM1_HIGH_LOW (0x4 * 0x817) 372 #define LCD_PWM2_CTRL (0x4 * 0x818) 373 #define LCD_PWM2_RPT_LEADIN (0x4 * 0x819) 374 #define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) 375 #define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) 376 #define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) 377 #define LCD_DMA_STATE_ACTIVE BIT(3) 378 #define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) 379 #define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) 380 #define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) 381 #define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05) 382 #define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06) 383 #define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07) 384 #define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08) 385 #define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09) 386 #define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a) 387 #define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b) 388 #define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c) 389 #define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d) 390 #define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) 391 #define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f) 392 393 /*************************************************************************** 394 * MIPI controller control register defines 395 *************************************************************************/ 396 #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) 397 #define HS_OFFSET(M) (((M) + 1) * 0x400) 398 399 #define MIPI_TX_HS_CTRL (0x0) 400 #define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) 401 #define HS_CTRL_EN BIT(0) 402 /* 1:CSI 0:DSI */ 403 #define HS_CTRL_CSIDSIN BIT(2) 404 /* 1:LCD, 0:DMA */ 405 #define TX_SOURCE BIT(3) 406 #define ACTIVE_LANES(n) ((n) << 4) 407 #define LCD_VC(ch) ((ch) << 8) 408 #define DSI_EOTP_EN BIT(11) 409 #define DSI_CMD_HFP_EN BIT(12) 410 #define CRC_EN BIT(14) 411 #define HSEXIT_CNT(n) ((n) << 16) 412 #define HSCLKIDLE_CNT BIT(24) 413 #define MIPI_TX_HS_SYNC_CFG (0x8) 414 #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ 415 + HS_OFFSET(M)) 416 #define LINE_SYNC_PKT_ENABLE BIT(0) 417 #define FRAME_COUNTER_ACTIVE BIT(1) 418 #define LINE_COUNTER_ACTIVE BIT(2) 419 #define DSI_V_BLANKING BIT(4) 420 #define DSI_HSA_BLANKING BIT(5) 421 #define DSI_HBP_BLANKING BIT(6) 422 #define DSI_HFP_BLANKING BIT(7) 423 #define DSI_SYNC_PULSE_EVENTN BIT(8) 424 #define DSI_LPM_FIRST_VSA_LINE BIT(9) 425 #define DSI_LPM_LAST_VFP_LINE BIT(10) 426 #define WAIT_ALL_SECT BIT(11) 427 #define WAIT_TRIG_POS BIT(15) 428 #define ALWAYS_USE_HACT(f) ((f) << 19) 429 #define FRAME_GEN_EN(f) ((f) << 23) 430 #define HACT_WAIT_STOP(f) ((f) << 28) 431 #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) 432 #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ 433 HS_OFFSET(M) + (0x2C * (N)) \ 434 + (8 * (O))) 435 #define MIPI_TX_SECT_WC_MASK (0xffff) 436 #define MIPI_TX_SECT_VC_MASK (3) 437 #define MIPI_TX_SECT_VC_SHIFT (22) 438 #define MIPI_TX_SECT_DT_MASK (0x3f) 439 #define MIPI_TX_SECT_DT_SHIFT (16) 440 #define MIPI_TX_SECT_DM_MASK (3) 441 #define MIPI_TX_SECT_DM_SHIFT (24) 442 #define MIPI_TX_SECT_DMA_PACKED BIT(26) 443 #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60) 444 #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64) 445 #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ 446 (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 \ 447 + HS_OFFSET(M) + (0x2C * (N))) 448 #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) 449 #define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ 450 (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \ 451 + (0x2C * (N)) + (8 * (O))) 452 453 #define MIPI_TX_HS_FG0_NUM_LINES (0x68) 454 #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \ 455 (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \ 456 + (0x2C * (N))) 457 #define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104) 458 #define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \ 459 (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \ 460 + (0x4 * (N))) 461 #define MIPI_TX_HS_V_BACKPORCHES0 (0x16c) 462 #define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \ 463 (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \ 464 + (0x4 * (N))) 465 #define MIPI_TX_HS_V_FRONTPORCHES0 (0x174) 466 #define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \ 467 (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \ 468 + (0x4 * (N))) 469 #define MIPI_TX_HS_V_ACTIVE0 (0x17c) 470 #define MIPI_TXm_HS_V_ACTIVEn(M, N) \ 471 (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \ 472 + (0x4 * (N))) 473 #define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c) 474 #define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \ 475 (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \ 476 + (0x4 * (N))) 477 #define MIPI_TX_HS_H_BACKPORCH0 (0x11c) 478 #define MIPI_TXm_HS_H_BACKPORCHn(M, N) \ 479 (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \ 480 + (0x4 * (N))) 481 #define MIPI_TX_HS_H_FRONTPORCH0 (0x12c) 482 #define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \ 483 (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \ 484 + (0x4 * (N))) 485 #define MIPI_TX_HS_H_ACTIVE0 (0x184) 486 #define MIPI_TXm_HS_H_ACTIVEn(M, N) \ 487 (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \ 488 + (0x4 * (N))) 489 #define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c) 490 #define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \ 491 (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \ 492 + (0x4 * (N))) 493 #define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c) 494 #define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \ 495 (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \ 496 + (0x4 * (N))) 497 #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) 498 #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \ 499 (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \ 500 + (0x4 * (N))) 501 502 #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) 503 #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \ 504 (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M)) 505 506 #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198) 507 #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c) 508 #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ 509 (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \ 510 + (0x4 * (N))) 511 #define SET_MC_FIFO_CHAN_ALLOC(dev, ctrl, vc, sz) \ 512 kmb_write_bits_mipi(dev, \ 513 MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \ 514 (vc) / 2), ((vc) % 2) * 16, 16, sz) 515 #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0) 516 #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4) 517 #define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ 518 (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \ 519 + (0x4 * (N))) 520 #define SET_MC_FIFO_RTHRESHOLD(dev, ctrl, vc, th) \ 521 kmb_write_bits_mipi(dev, MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, \ 522 (vc) / 2), ((vc) % 2) * 16, 16, th) 523 #define MIPI_TX_HS_DMA_CFG (0x1a8) 524 #define MIPI_TX_HS_DMA_START_ADR_CHAN0 (0x1ac) 525 #define MIPI_TX_HS_DMA_LEN_CHAN0 (0x1b4) 526 527 /* MIPI IRQ */ 528 #define MIPI_CTRL_IRQ_STATUS0 (0x00) 529 #define MIPI_DPHY_ERR_IRQ 1 530 #define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */ 531 #define MIPI_HS_IRQ 13 532 /* bits 13-22 */ 533 #define MIPI_HS_IRQ_MASK 0x7FE000 534 #define MIPI_LP_EVENT_IRQ 25 535 #define MIPI_GET_IRQ_STAT0(dev) kmb_read_mipi(dev, \ 536 MIPI_CTRL_IRQ_STATUS0) 537 #define MIPI_CTRL_IRQ_STATUS1 (0x04) 538 #define MIPI_HS_RX_EVENT_IRQ 0 539 #define MIPI_GET_IRQ_STAT1(dev) kmb_read_mipi(dev, \ 540 MIPI_CTRL_IRQ_STATUS1) 541 #define MIPI_CTRL_IRQ_ENABLE0 (0x08) 542 #define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) kmb_set_bit_mipi(dev, \ 543 MIPI_CTRL_IRQ_ENABLE0, \ 544 (M) + (N)) 545 #define MIPI_GET_IRQ_ENABLED0(dev) kmb_read_mipi(dev, \ 546 MIPI_CTRL_IRQ_ENABLE0) 547 #define MIPI_CTRL_IRQ_ENABLE1 (0x0c) 548 #define MIPI_GET_IRQ_ENABLED1(dev) kmb_read_mipi(dev, \ 549 MIPI_CTRL_IRQ_ENABLE1) 550 #define MIPI_CTRL_IRQ_CLEAR0 (0x010) 551 #define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) \ 552 kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR0, (M) + (N)) 553 #define MIPI_CTRL_IRQ_CLEAR1 (0x014) 554 #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \ 555 kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, (M) + (N)) 556 #define MIPI_CTRL_DIG_LOOPBACK (0x018) 557 #define MIPI_TX_HS_IRQ_STATUS (0x01c) 558 #define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \ 559 HS_OFFSET(M)) 560 #define GET_MIPI_TX_HS_IRQ_STATUS(dev, M) kmb_read_mipi(dev, \ 561 MIPI_TX_HS_IRQ_STATUSm(M)) 562 #define MIPI_TX_HS_IRQ_LINE_COMPARE BIT(1) 563 #define MIPI_TX_HS_IRQ_FRAME_DONE_0 BIT(2) 564 #define MIPI_TX_HS_IRQ_FRAME_DONE_1 BIT(3) 565 #define MIPI_TX_HS_IRQ_FRAME_DONE_2 BIT(4) 566 #define MIPI_TX_HS_IRQ_FRAME_DONE_3 BIT(5) 567 #define MIPI_TX_HS_IRQ_DMA_DONE_0 BIT(6) 568 #define MIPI_TX_HS_IRQ_DMA_IDLE_0 BIT(7) 569 #define MIPI_TX_HS_IRQ_DMA_DONE_1 BIT(8) 570 #define MIPI_TX_HS_IRQ_DMA_IDLE_1 BIT(9) 571 #define MIPI_TX_HS_IRQ_DMA_DONE_2 BIT(10) 572 #define MIPI_TX_HS_IRQ_DMA_IDLE_2 BIT(11) 573 #define MIPI_TX_HS_IRQ_DMA_DONE_3 BIT(12) 574 #define MIPI_TX_HS_IRQ_DMA_IDLE_3 BIT(13) 575 #define MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW BIT(14) 576 #define MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW BIT(15) 577 #define MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY BIT(16) 578 #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL BIT(17) 579 #define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR BIT(18) 580 #define MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR BIT(20) 581 #define MIPI_TX_HS_IRQ_FRAME_DONE \ 582 (MIPI_TX_HS_IRQ_FRAME_DONE_0 | \ 583 MIPI_TX_HS_IRQ_FRAME_DONE_1 | \ 584 MIPI_TX_HS_IRQ_FRAME_DONE_2 | \ 585 MIPI_TX_HS_IRQ_FRAME_DONE_3) 586 587 #define MIPI_TX_HS_IRQ_DMA_DONE \ 588 (MIPI_TX_HS_IRQ_DMA_DONE_0 | \ 589 MIPI_TX_HS_IRQ_DMA_DONE_1 | \ 590 MIPI_TX_HS_IRQ_DMA_DONE_2 | \ 591 MIPI_TX_HS_IRQ_DMA_DONE_3) 592 593 #define MIPI_TX_HS_IRQ_DMA_IDLE \ 594 (MIPI_TX_HS_IRQ_DMA_IDLE_0 | \ 595 MIPI_TX_HS_IRQ_DMA_IDLE_1 | \ 596 MIPI_TX_HS_IRQ_DMA_IDLE_2 | \ 597 MIPI_TX_HS_IRQ_DMA_IDLE_3) 598 599 #define MIPI_TX_HS_IRQ_ERROR \ 600 (MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW | \ 601 MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW | \ 602 MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY | \ 603 MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL | \ 604 MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR | \ 605 MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR) 606 607 #define MIPI_TX_HS_IRQ_ALL \ 608 (MIPI_TX_HS_IRQ_FRAME_DONE | \ 609 MIPI_TX_HS_IRQ_DMA_DONE | \ 610 MIPI_TX_HS_IRQ_DMA_IDLE | \ 611 MIPI_TX_HS_IRQ_LINE_COMPARE | \ 612 MIPI_TX_HS_IRQ_ERROR) 613 614 #define MIPI_TX_HS_IRQ_ENABLE (0x020) 615 #define GET_HS_IRQ_ENABLE(dev, M) kmb_read_mipi(dev, \ 616 MIPI_TX_HS_IRQ_ENABLE \ 617 + HS_OFFSET(M)) 618 #define MIPI_TX_HS_IRQ_CLEAR (0x024) 619 620 /* MIPI Test Pattern Generation */ 621 #define MIPI_TX_HS_TEST_PAT_CTRL (0x230) 622 #define MIPI_TXm_HS_TEST_PAT_CTRL(M) \ 623 (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M)) 624 #define TP_EN_VCm(M) (1 << ((M) * 0x04)) 625 #define TP_SEL_VCm(M, N) \ 626 ((N) << (((M) * 0x04) + 1)) 627 #define TP_STRIPE_WIDTH(M) ((M) << 16) 628 #define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234) 629 #define MIPI_TXm_HS_TEST_PAT_COLOR0(M) \ 630 (MIPI_TX_HS_TEST_PAT_COLOR0 + HS_OFFSET(M)) 631 #define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238) 632 #define MIPI_TXm_HS_TEST_PAT_COLOR1(M) \ 633 (MIPI_TX_HS_TEST_PAT_COLOR1 + HS_OFFSET(M)) 634 635 /* D-PHY regs */ 636 #define DPHY_ENABLE (0x100) 637 #define DPHY_INIT_CTRL0 (0x104) 638 #define SHUTDOWNZ 0 639 #define RESETZ 12 640 #define DPHY_INIT_CTRL1 (0x108) 641 #define PLL_CLKSEL_0 18 642 #define PLL_SHADOW_CTRL 16 643 #define DPHY_INIT_CTRL2 (0x10c) 644 #define SET_DPHY_INIT_CTRL0(dev, dphy, offset) \ 645 kmb_set_bit_mipi(dev, DPHY_INIT_CTRL0, \ 646 ((dphy) + (offset))) 647 #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ 648 kmb_clr_bit_mipi(dev, DPHY_INIT_CTRL0, \ 649 ((dphy) + (offset))) 650 #define DPHY_INIT_CTRL2 (0x10c) 651 #define DPHY_PLL_OBS0 (0x110) 652 #define DPHY_PLL_OBS1 (0x114) 653 #define DPHY_PLL_OBS2 (0x118) 654 #define DPHY_FREQ_CTRL0_3 (0x11c) 655 #define DPHY_FREQ_CTRL4_7 (0x120) 656 #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ 657 kmb_write_bits_mipi(dev, DPHY_FREQ_CTRL0_3 \ 658 + (((dphy) / 4) * 4), (dphy % 4) * 8, 6, val) 659 660 #define DPHY_FORCE_CTRL0 (0x128) 661 #define DPHY_FORCE_CTRL1 (0x12C) 662 #define MIPI_DPHY_STAT0_3 (0x134) 663 #define MIPI_DPHY_STAT4_7 (0x138) 664 #define GET_STOPSTATE_DATA(dev, dphy) \ 665 (((kmb_read_mipi(dev, MIPI_DPHY_STAT0_3 + \ 666 ((dphy) / 4) * 4)) >> \ 667 (((dphy % 4) * 8) + 4)) & 0x03) 668 669 #define MIPI_DPHY_ERR_STAT6_7 (0x14C) 670 671 #define DPHY_TEST_CTRL0 (0x154) 672 #define SET_DPHY_TEST_CTRL0(dev, dphy) \ 673 kmb_set_bit_mipi(dev, DPHY_TEST_CTRL0, (dphy)) 674 #define CLR_DPHY_TEST_CTRL0(dev, dphy) \ 675 kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL0, \ 676 (dphy)) 677 #define DPHY_TEST_CTRL1 (0x158) 678 #define SET_DPHY_TEST_CTRL1_CLK(dev, dphy) \ 679 kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy)) 680 #define CLR_DPHY_TEST_CTRL1_CLK(dev, dphy) \ 681 kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy)) 682 #define SET_DPHY_TEST_CTRL1_EN(dev, dphy) \ 683 kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, ((dphy) + 12)) 684 #define CLR_DPHY_TEST_CTRL1_EN(dev, dphy) \ 685 kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, ((dphy) + 12)) 686 #define DPHY_TEST_DIN0_3 (0x15c) 687 #define SET_TEST_DIN0_3(dev, dphy, val) \ 688 kmb_write_mipi(dev, DPHY_TEST_DIN0_3 + \ 689 4, ((val) << (((dphy) % 4) * 8))) 690 #define DPHY_TEST_DOUT0_3 (0x168) 691 #define GET_TEST_DOUT0_3(dev, dphy) \ 692 (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3) \ 693 >> (((dphy) % 4) * 8) & 0xff) 694 #define DPHY_TEST_DOUT4_7 (0x16C) 695 #define GET_TEST_DOUT4_7(dev, dphy) \ 696 (kmb_read_mipi(dev, DPHY_TEST_DOUT4_7) \ 697 >> (((dphy) % 4) * 8) & 0xff) 698 #define DPHY_TEST_DOUT8_9 (0x170) 699 #define DPHY_TEST_DIN4_7 (0x160) 700 #define DPHY_TEST_DIN8_9 (0x164) 701 #define DPHY_PLL_LOCK (0x188) 702 #define GET_PLL_LOCK(dev, dphy) \ 703 (kmb_read_mipi(dev, DPHY_PLL_LOCK) \ 704 & (1 << ((dphy) - MIPI_DPHY6))) 705 #define DPHY_CFG_CLK_EN (0x18c) 706 707 #define MSS_MIPI_CIF_CFG (0x00) 708 #define MSS_LCD_MIPI_CFG (0x04) 709 #define MSS_CAM_CLK_CTRL (0x10) 710 #define MSS_LOOPBACK_CFG (0x0C) 711 #define LCD BIT(1) 712 #define MIPI_COMMON BIT(2) 713 #define MIPI_TX0 BIT(9) 714 #define MSS_CAM_RSTN_CTRL (0x14) 715 #define MSS_CAM_RSTN_SET (0x20) 716 #define MSS_CAM_RSTN_CLR (0x24) 717 718 #define MSSCPU_CPR_CLK_EN (0x0) 719 #define MSSCPU_CPR_RST_EN (0x10) 720 #define BIT_MASK_16 (0xffff) 721 /* icam lcd qos */ 722 #define LCD_QOS_PRIORITY (0x8) 723 #define LCD_QOS_MODE (0xC) 724 #define LCD_QOS_BW (0x10) 725 #endif /* __KMB_REGS_H__ */ 726