17f7b96a8SAnitha Chrisanthus /* SPDX-License-Identifier: GPL-2.0-only 27f7b96a8SAnitha Chrisanthus * 37f7b96a8SAnitha Chrisanthus * Copyright © 2018-2020 Intel Corporation 47f7b96a8SAnitha Chrisanthus */ 57f7b96a8SAnitha Chrisanthus 67f7b96a8SAnitha Chrisanthus #ifndef __KMB_PLANE_H__ 77f7b96a8SAnitha Chrisanthus #define __KMB_PLANE_H__ 87f7b96a8SAnitha Chrisanthus 97f7b96a8SAnitha Chrisanthus #include <drm/drm_fourcc.h> 107f7b96a8SAnitha Chrisanthus #include <drm/drm_plane.h> 117f7b96a8SAnitha Chrisanthus 127f7b96a8SAnitha Chrisanthus #define LCD_INT_VL0_ERR ((LAYER0_DMA_FIFO_UNDERFLOW) | \ 137f7b96a8SAnitha Chrisanthus (LAYER0_DMA_FIFO_OVERFLOW) | \ 147f7b96a8SAnitha Chrisanthus (LAYER0_DMA_CB_FIFO_OVERFLOW) | \ 157f7b96a8SAnitha Chrisanthus (LAYER0_DMA_CB_FIFO_UNDERFLOW) | \ 167f7b96a8SAnitha Chrisanthus (LAYER0_DMA_CR_FIFO_OVERFLOW) | \ 177f7b96a8SAnitha Chrisanthus (LAYER0_DMA_CR_FIFO_UNDERFLOW)) 187f7b96a8SAnitha Chrisanthus 197f7b96a8SAnitha Chrisanthus #define LCD_INT_VL1_ERR ((LAYER1_DMA_FIFO_UNDERFLOW) | \ 207f7b96a8SAnitha Chrisanthus (LAYER1_DMA_FIFO_OVERFLOW) | \ 217f7b96a8SAnitha Chrisanthus (LAYER1_DMA_CB_FIFO_OVERFLOW) | \ 227f7b96a8SAnitha Chrisanthus (LAYER1_DMA_CB_FIFO_UNDERFLOW) | \ 237f7b96a8SAnitha Chrisanthus (LAYER1_DMA_CR_FIFO_OVERFLOW) | \ 247f7b96a8SAnitha Chrisanthus (LAYER1_DMA_CR_FIFO_UNDERFLOW)) 257f7b96a8SAnitha Chrisanthus 267f7b96a8SAnitha Chrisanthus #define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW) 277f7b96a8SAnitha Chrisanthus #define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW) 287f7b96a8SAnitha Chrisanthus #define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR) 297f7b96a8SAnitha Chrisanthus #define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR) 307f7b96a8SAnitha Chrisanthus #define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR) 317f7b96a8SAnitha Chrisanthus #define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) 327f7b96a8SAnitha Chrisanthus #define LCD_INT_DMA_ERR (LCD_INT_VL0_ERR | LCD_INT_VL1_ERR \ 337f7b96a8SAnitha Chrisanthus | LCD_INT_GL0_ERR | LCD_INT_GL1_ERR) 347f7b96a8SAnitha Chrisanthus 357f7b96a8SAnitha Chrisanthus #define POSSIBLE_CRTCS 1 367f7b96a8SAnitha Chrisanthus #define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) 377f7b96a8SAnitha Chrisanthus 38c026565fSEdmund Dea #define POSSIBLE_CRTCS 1 39c026565fSEdmund Dea #define KMB_MAX_PLANES 2 40c026565fSEdmund Dea 417f7b96a8SAnitha Chrisanthus enum layer_id { 427f7b96a8SAnitha Chrisanthus LAYER_0, 437f7b96a8SAnitha Chrisanthus LAYER_1, 447f7b96a8SAnitha Chrisanthus LAYER_2, 457f7b96a8SAnitha Chrisanthus LAYER_3, 467f7b96a8SAnitha Chrisanthus /* KMB_MAX_PLANES */ 477f7b96a8SAnitha Chrisanthus }; 487f7b96a8SAnitha Chrisanthus 497f7b96a8SAnitha Chrisanthus enum sub_plane_id { 507f7b96a8SAnitha Chrisanthus Y_PLANE, 517f7b96a8SAnitha Chrisanthus U_PLANE, 527f7b96a8SAnitha Chrisanthus V_PLANE, 537f7b96a8SAnitha Chrisanthus MAX_SUB_PLANES, 547f7b96a8SAnitha Chrisanthus }; 557f7b96a8SAnitha Chrisanthus 567f7b96a8SAnitha Chrisanthus struct kmb_plane { 577f7b96a8SAnitha Chrisanthus struct drm_plane base_plane; 587f7b96a8SAnitha Chrisanthus unsigned char id; 597f7b96a8SAnitha Chrisanthus }; 607f7b96a8SAnitha Chrisanthus 617f7b96a8SAnitha Chrisanthus struct layer_status { 627f7b96a8SAnitha Chrisanthus bool disable; 637f7b96a8SAnitha Chrisanthus u32 ctrl; 647f7b96a8SAnitha Chrisanthus }; 657f7b96a8SAnitha Chrisanthus 66*982f8ad6SEdmund Dea struct disp_cfg { 67*982f8ad6SEdmund Dea unsigned int width; 68*982f8ad6SEdmund Dea unsigned int height; 69*982f8ad6SEdmund Dea unsigned int format; 70*982f8ad6SEdmund Dea }; 71*982f8ad6SEdmund Dea 727f7b96a8SAnitha Chrisanthus struct kmb_plane *kmb_plane_init(struct drm_device *drm); 737f7b96a8SAnitha Chrisanthus void kmb_plane_destroy(struct drm_plane *plane); 747f7b96a8SAnitha Chrisanthus #endif /* __KMB_PLANE_H__ */ 75