1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic.h> 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_blend.h> 9 #include <drm/drm_crtc.h> 10 #include <drm/drm_crtc_helper.h> 11 #include <drm/drm_fb_cma_helper.h> 12 #include <drm/drm_fb_helper.h> 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_framebuffer.h> 15 #include <drm/drm_gem_cma_helper.h> 16 #include <drm/drm_managed.h> 17 #include <drm/drm_plane_helper.h> 18 19 #include "kmb_drv.h" 20 #include "kmb_plane.h" 21 #include "kmb_regs.h" 22 23 const u32 layer_irqs[] = { 24 LCD_INT_VL0, 25 LCD_INT_VL1, 26 LCD_INT_GL0, 27 LCD_INT_GL1 28 }; 29 30 /* Conversion (yuv->rgb) matrix from myriadx */ 31 static const u32 csc_coef_lcd[] = { 32 1024, 0, 1436, 33 1024, -352, -731, 34 1024, 1814, 0, 35 -179, 125, -226 36 }; 37 38 /* Graphics layer (layers 2 & 3) formats, only packed formats are supported */ 39 static const u32 kmb_formats_g[] = { 40 DRM_FORMAT_RGB332, 41 DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, 42 DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, 43 DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, 44 DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, 45 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, 46 DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, 47 DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 48 DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, 49 }; 50 51 /* Video layer ( 0 & 1) formats, packed and planar formats are supported */ 52 static const u32 kmb_formats_v[] = { 53 /* packed formats */ 54 DRM_FORMAT_RGB332, 55 DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, 56 DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, 57 DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, 58 DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, 59 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, 60 DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, 61 DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 62 DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, 63 /*planar formats */ 64 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, 65 DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, 66 DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, 67 DRM_FORMAT_NV12, DRM_FORMAT_NV21, 68 }; 69 70 static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) 71 { 72 struct kmb_drm_private *kmb; 73 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 74 int i; 75 int plane_id = kmb_plane->id; 76 struct disp_cfg init_disp_cfg; 77 78 kmb = to_kmb(plane->dev); 79 init_disp_cfg = kmb->init_disp_cfg[plane_id]; 80 /* Due to HW limitations, changing pixel format after initial 81 * plane configuration is not supported. 82 */ 83 if (init_disp_cfg.format && init_disp_cfg.format != format) { 84 drm_dbg(&kmb->drm, "Cannot change format after initial plane configuration"); 85 return -EINVAL; 86 } 87 for (i = 0; i < plane->format_count; i++) { 88 if (plane->format_types[i] == format) 89 return 0; 90 } 91 return -EINVAL; 92 } 93 94 static int kmb_plane_atomic_check(struct drm_plane *plane, 95 struct drm_atomic_state *state) 96 { 97 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 98 plane); 99 struct kmb_drm_private *kmb; 100 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 101 int plane_id = kmb_plane->id; 102 struct disp_cfg init_disp_cfg; 103 struct drm_framebuffer *fb; 104 int ret; 105 struct drm_crtc_state *crtc_state; 106 bool can_position; 107 108 kmb = to_kmb(plane->dev); 109 init_disp_cfg = kmb->init_disp_cfg[plane_id]; 110 fb = new_plane_state->fb; 111 if (!fb || !new_plane_state->crtc) 112 return 0; 113 114 ret = check_pixel_format(plane, fb->format->format); 115 if (ret) 116 return ret; 117 118 if (new_plane_state->crtc_w > KMB_FB_MAX_WIDTH || 119 new_plane_state->crtc_h > KMB_FB_MAX_HEIGHT || 120 new_plane_state->crtc_w < KMB_FB_MIN_WIDTH || 121 new_plane_state->crtc_h < KMB_FB_MIN_HEIGHT) 122 return -EINVAL; 123 124 /* Due to HW limitations, changing plane height or width after 125 * initial plane configuration is not supported. 126 */ 127 if ((init_disp_cfg.width && init_disp_cfg.height) && 128 (init_disp_cfg.width != fb->width || 129 init_disp_cfg.height != fb->height)) { 130 drm_dbg(&kmb->drm, "Cannot change plane height or width after initial configuration"); 131 return -EINVAL; 132 } 133 can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY); 134 crtc_state = 135 drm_atomic_get_existing_crtc_state(state, 136 new_plane_state->crtc); 137 return drm_atomic_helper_check_plane_state(new_plane_state, 138 crtc_state, 139 DRM_PLANE_HELPER_NO_SCALING, 140 DRM_PLANE_HELPER_NO_SCALING, 141 can_position, true); 142 } 143 144 static void kmb_plane_atomic_disable(struct drm_plane *plane, 145 struct drm_atomic_state *state) 146 { 147 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 148 int plane_id = kmb_plane->id; 149 struct kmb_drm_private *kmb; 150 151 kmb = to_kmb(plane->dev); 152 153 if (WARN_ON(plane_id >= KMB_MAX_PLANES)) 154 return; 155 156 switch (plane_id) { 157 case LAYER_0: 158 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE; 159 break; 160 case LAYER_1: 161 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE; 162 break; 163 } 164 165 kmb->plane_status[plane_id].disable = true; 166 } 167 168 static unsigned int get_pixel_format(u32 format) 169 { 170 unsigned int val = 0; 171 172 switch (format) { 173 /* planar formats */ 174 case DRM_FORMAT_YUV444: 175 val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE; 176 break; 177 case DRM_FORMAT_YVU444: 178 val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE 179 | LCD_LAYER_CRCB_ORDER; 180 break; 181 case DRM_FORMAT_YUV422: 182 val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE; 183 break; 184 case DRM_FORMAT_YVU422: 185 val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE 186 | LCD_LAYER_CRCB_ORDER; 187 break; 188 case DRM_FORMAT_YUV420: 189 val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE; 190 break; 191 case DRM_FORMAT_YVU420: 192 val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE 193 | LCD_LAYER_CRCB_ORDER; 194 break; 195 case DRM_FORMAT_NV12: 196 val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE; 197 break; 198 case DRM_FORMAT_NV21: 199 val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE 200 | LCD_LAYER_CRCB_ORDER; 201 break; 202 /* packed formats */ 203 /* looks hw requires B & G to be swapped when RGB */ 204 case DRM_FORMAT_RGB332: 205 val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER; 206 break; 207 case DRM_FORMAT_XBGR4444: 208 val = LCD_LAYER_FORMAT_RGBX4444; 209 break; 210 case DRM_FORMAT_ARGB4444: 211 val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; 212 break; 213 case DRM_FORMAT_ABGR4444: 214 val = LCD_LAYER_FORMAT_RGBA4444; 215 break; 216 case DRM_FORMAT_XRGB1555: 217 val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; 218 break; 219 case DRM_FORMAT_XBGR1555: 220 val = LCD_LAYER_FORMAT_XRGB1555; 221 break; 222 case DRM_FORMAT_ARGB1555: 223 val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; 224 break; 225 case DRM_FORMAT_ABGR1555: 226 val = LCD_LAYER_FORMAT_RGBA1555; 227 break; 228 case DRM_FORMAT_RGB565: 229 val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; 230 break; 231 case DRM_FORMAT_BGR565: 232 val = LCD_LAYER_FORMAT_RGB565; 233 break; 234 case DRM_FORMAT_RGB888: 235 val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; 236 break; 237 case DRM_FORMAT_BGR888: 238 val = LCD_LAYER_FORMAT_RGB888; 239 break; 240 case DRM_FORMAT_XRGB8888: 241 val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; 242 break; 243 case DRM_FORMAT_XBGR8888: 244 val = LCD_LAYER_FORMAT_RGBX8888; 245 break; 246 case DRM_FORMAT_ARGB8888: 247 val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; 248 break; 249 case DRM_FORMAT_ABGR8888: 250 val = LCD_LAYER_FORMAT_RGBA8888; 251 break; 252 } 253 DRM_INFO_ONCE("%s : %d format=0x%x val=0x%x\n", 254 __func__, __LINE__, format, val); 255 return val; 256 } 257 258 static unsigned int get_bits_per_pixel(const struct drm_format_info *format) 259 { 260 u32 bpp = 0; 261 unsigned int val = 0; 262 263 if (format->num_planes > 1) { 264 val = LCD_LAYER_8BPP; 265 return val; 266 } 267 268 bpp += 8 * format->cpp[0]; 269 270 switch (bpp) { 271 case 8: 272 val = LCD_LAYER_8BPP; 273 break; 274 case 16: 275 val = LCD_LAYER_16BPP; 276 break; 277 case 24: 278 val = LCD_LAYER_24BPP; 279 break; 280 case 32: 281 val = LCD_LAYER_32BPP; 282 break; 283 } 284 285 DRM_DEBUG("bpp=%d val=0x%x\n", bpp, val); 286 return val; 287 } 288 289 static void config_csc(struct kmb_drm_private *kmb, int plane_id) 290 { 291 /* YUV to RGB conversion using the fixed matrix csc_coef_lcd */ 292 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]); 293 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]); 294 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]); 295 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]); 296 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]); 297 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]); 298 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]); 299 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]); 300 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]); 301 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]); 302 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]); 303 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]); 304 } 305 306 static void kmb_plane_set_alpha(struct kmb_drm_private *kmb, 307 const struct drm_plane_state *state, 308 unsigned char plane_id, 309 unsigned int *val) 310 { 311 u16 plane_alpha = state->alpha; 312 u16 pixel_blend_mode = state->pixel_blend_mode; 313 int has_alpha = state->fb->format->has_alpha; 314 315 if (plane_alpha != DRM_BLEND_ALPHA_OPAQUE) 316 *val |= LCD_LAYER_ALPHA_STATIC; 317 318 if (has_alpha) { 319 switch (pixel_blend_mode) { 320 case DRM_MODE_BLEND_PIXEL_NONE: 321 break; 322 case DRM_MODE_BLEND_PREMULTI: 323 *val |= LCD_LAYER_ALPHA_EMBED | LCD_LAYER_ALPHA_PREMULT; 324 break; 325 case DRM_MODE_BLEND_COVERAGE: 326 *val |= LCD_LAYER_ALPHA_EMBED; 327 break; 328 default: 329 DRM_DEBUG("Missing pixel blend mode case (%s == %ld)\n", 330 __stringify(pixel_blend_mode), 331 (long)pixel_blend_mode); 332 break; 333 } 334 } 335 336 if (plane_alpha == DRM_BLEND_ALPHA_OPAQUE && !has_alpha) { 337 *val &= LCD_LAYER_ALPHA_DISABLED; 338 return; 339 } 340 341 kmb_write_lcd(kmb, LCD_LAYERn_ALPHA(plane_id), plane_alpha); 342 } 343 344 static void kmb_plane_atomic_update(struct drm_plane *plane, 345 struct drm_atomic_state *state) 346 { 347 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 348 plane); 349 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 350 plane); 351 struct drm_framebuffer *fb; 352 struct kmb_drm_private *kmb; 353 unsigned int width; 354 unsigned int height; 355 unsigned int dma_len; 356 struct kmb_plane *kmb_plane; 357 unsigned int dma_cfg; 358 unsigned int ctrl = 0, val = 0, out_format = 0; 359 unsigned int src_w, src_h, crtc_x, crtc_y; 360 unsigned char plane_id; 361 int num_planes; 362 static dma_addr_t addr[MAX_SUB_PLANES]; 363 struct disp_cfg *init_disp_cfg; 364 365 if (!plane || !new_plane_state || !old_plane_state) 366 return; 367 368 fb = new_plane_state->fb; 369 if (!fb) 370 return; 371 372 num_planes = fb->format->num_planes; 373 kmb_plane = to_kmb_plane(plane); 374 375 kmb = to_kmb(plane->dev); 376 plane_id = kmb_plane->id; 377 378 spin_lock_irq(&kmb->irq_lock); 379 if (kmb->kmb_under_flow || kmb->kmb_flush_done) { 380 spin_unlock_irq(&kmb->irq_lock); 381 drm_dbg(&kmb->drm, "plane_update:underflow!!!! returning"); 382 return; 383 } 384 spin_unlock_irq(&kmb->irq_lock); 385 386 init_disp_cfg = &kmb->init_disp_cfg[plane_id]; 387 src_w = new_plane_state->src_w >> 16; 388 src_h = new_plane_state->src_h >> 16; 389 crtc_x = new_plane_state->crtc_x; 390 crtc_y = new_plane_state->crtc_y; 391 392 drm_dbg(&kmb->drm, 393 "src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x\n", 394 src_w, src_h, fb->format->format, fb->flags); 395 396 width = fb->width; 397 height = fb->height; 398 dma_len = (width * height * fb->format->cpp[0]); 399 drm_dbg(&kmb->drm, "dma_len=%d ", dma_len); 400 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN(plane_id), dma_len); 401 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); 402 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), 403 fb->pitches[0]); 404 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), 405 (width * fb->format->cpp[0])); 406 407 addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, new_plane_state, 0); 408 kmb_write_lcd(kmb, LCD_LAYERn_DMA_START_ADDR(plane_id), 409 addr[Y_PLANE] + fb->offsets[0]); 410 val = get_pixel_format(fb->format->format); 411 val |= get_bits_per_pixel(fb->format); 412 /* Program Cb/Cr for planar formats */ 413 if (num_planes > 1) { 414 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), 415 width * fb->format->cpp[0]); 416 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), 417 (width * fb->format->cpp[0])); 418 419 addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, new_plane_state, 420 U_PLANE); 421 /* check if Cb/Cr is swapped*/ 422 if (num_planes == 3 && (val & LCD_LAYER_CRCB_ORDER)) 423 kmb_write_lcd(kmb, 424 LCD_LAYERn_DMA_START_CR_ADR(plane_id), 425 addr[U_PLANE]); 426 else 427 kmb_write_lcd(kmb, 428 LCD_LAYERn_DMA_START_CB_ADR(plane_id), 429 addr[U_PLANE]); 430 431 if (num_planes == 3) { 432 kmb_write_lcd(kmb, 433 LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), 434 ((width) * fb->format->cpp[0])); 435 436 kmb_write_lcd(kmb, 437 LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), 438 ((width) * fb->format->cpp[0])); 439 440 addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, 441 new_plane_state, 442 V_PLANE); 443 444 /* check if Cb/Cr is swapped*/ 445 if (val & LCD_LAYER_CRCB_ORDER) 446 kmb_write_lcd(kmb, 447 LCD_LAYERn_DMA_START_CB_ADR(plane_id), 448 addr[V_PLANE]); 449 else 450 kmb_write_lcd(kmb, 451 LCD_LAYERn_DMA_START_CR_ADR(plane_id), 452 addr[V_PLANE]); 453 } 454 } 455 456 kmb_write_lcd(kmb, LCD_LAYERn_WIDTH(plane_id), src_w - 1); 457 kmb_write_lcd(kmb, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); 458 kmb_write_lcd(kmb, LCD_LAYERn_COL_START(plane_id), crtc_x); 459 kmb_write_lcd(kmb, LCD_LAYERn_ROW_START(plane_id), crtc_y); 460 461 val |= LCD_LAYER_FIFO_100; 462 463 if (val & LCD_LAYER_PLANAR_STORAGE) { 464 val |= LCD_LAYER_CSC_EN; 465 466 /* Enable CSC if input is planar and output is RGB */ 467 config_csc(kmb, plane_id); 468 } 469 470 kmb_plane_set_alpha(kmb, plane->state, plane_id, &val); 471 472 kmb_write_lcd(kmb, LCD_LAYERn_CFG(plane_id), val); 473 474 /* Configure LCD_CONTROL */ 475 ctrl = kmb_read_lcd(kmb, LCD_CONTROL); 476 477 /* Set layer blending config */ 478 ctrl &= ~LCD_CTRL_ALPHA_ALL; 479 ctrl |= LCD_CTRL_ALPHA_BOTTOM_VL1 | 480 LCD_CTRL_ALPHA_BLEND_VL2; 481 482 ctrl &= ~LCD_CTRL_ALPHA_BLEND_BKGND_DISABLE; 483 484 switch (plane_id) { 485 case LAYER_0: 486 ctrl |= LCD_CTRL_VL1_ENABLE; 487 break; 488 case LAYER_1: 489 ctrl |= LCD_CTRL_VL2_ENABLE; 490 break; 491 case LAYER_2: 492 ctrl |= LCD_CTRL_GL1_ENABLE; 493 break; 494 case LAYER_3: 495 ctrl |= LCD_CTRL_GL2_ENABLE; 496 break; 497 } 498 499 ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE 500 | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; 501 502 /* LCD is connected to MIPI on kmb 503 * Therefore this bit is required for DSI Tx 504 */ 505 ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; 506 507 kmb_write_lcd(kmb, LCD_CONTROL, ctrl); 508 509 /* Enable pipeline AXI read transactions for the DMA 510 * after setting graphics layers. This must be done 511 * in a separate write cycle. 512 */ 513 kmb_set_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA); 514 515 /* FIXME no doc on how to set output format, these values are taken 516 * from the Myriadx tests 517 */ 518 out_format |= LCD_OUTF_FORMAT_RGB888; 519 520 /* Leave RGB order,conversion mode and clip mode to default */ 521 /* do not interleave RGB channels for mipi Tx compatibility */ 522 out_format |= LCD_OUTF_MIPI_RGB_MODE; 523 kmb_write_lcd(kmb, LCD_OUT_FORMAT_CFG, out_format); 524 525 dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | 526 LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; 527 528 /* Enable DMA */ 529 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); 530 531 /* Save initial display config */ 532 if (!init_disp_cfg->width || 533 !init_disp_cfg->height || 534 !init_disp_cfg->format) { 535 init_disp_cfg->width = width; 536 init_disp_cfg->height = height; 537 init_disp_cfg->format = fb->format->format; 538 } 539 540 drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg, 541 kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id))); 542 543 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF | 544 LCD_INT_DMA_ERR); 545 kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, LCD_INT_EOF | 546 LCD_INT_DMA_ERR); 547 } 548 549 static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { 550 .atomic_check = kmb_plane_atomic_check, 551 .atomic_update = kmb_plane_atomic_update, 552 .atomic_disable = kmb_plane_atomic_disable 553 }; 554 555 void kmb_plane_destroy(struct drm_plane *plane) 556 { 557 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 558 559 drm_plane_cleanup(plane); 560 kfree(kmb_plane); 561 } 562 563 static const struct drm_plane_funcs kmb_plane_funcs = { 564 .update_plane = drm_atomic_helper_update_plane, 565 .disable_plane = drm_atomic_helper_disable_plane, 566 .destroy = kmb_plane_destroy, 567 .reset = drm_atomic_helper_plane_reset, 568 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 569 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 570 }; 571 572 struct kmb_plane *kmb_plane_init(struct drm_device *drm) 573 { 574 struct kmb_drm_private *kmb = to_kmb(drm); 575 struct kmb_plane *plane = NULL; 576 struct kmb_plane *primary = NULL; 577 int i = 0; 578 int ret = 0; 579 enum drm_plane_type plane_type; 580 const u32 *plane_formats; 581 int num_plane_formats; 582 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 583 BIT(DRM_MODE_BLEND_PREMULTI) | 584 BIT(DRM_MODE_BLEND_COVERAGE); 585 586 for (i = 0; i < KMB_MAX_PLANES; i++) { 587 plane = drmm_kzalloc(drm, sizeof(*plane), GFP_KERNEL); 588 589 if (!plane) { 590 drm_err(drm, "Failed to allocate plane\n"); 591 return ERR_PTR(-ENOMEM); 592 } 593 594 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 595 DRM_PLANE_TYPE_OVERLAY; 596 if (i < 2) { 597 plane_formats = kmb_formats_v; 598 num_plane_formats = ARRAY_SIZE(kmb_formats_v); 599 } else { 600 plane_formats = kmb_formats_g; 601 num_plane_formats = ARRAY_SIZE(kmb_formats_g); 602 } 603 604 ret = drm_universal_plane_init(drm, &plane->base_plane, 605 POSSIBLE_CRTCS, &kmb_plane_funcs, 606 plane_formats, num_plane_formats, 607 NULL, plane_type, "plane %d", i); 608 if (ret < 0) { 609 drm_err(drm, "drm_universal_plane_init failed (ret=%d)", 610 ret); 611 goto cleanup; 612 } 613 drm_dbg(drm, "%s : %d i=%d type=%d", 614 __func__, __LINE__, 615 i, plane_type); 616 drm_plane_create_alpha_property(&plane->base_plane); 617 618 drm_plane_create_blend_mode_property(&plane->base_plane, 619 blend_caps); 620 621 drm_plane_create_zpos_immutable_property(&plane->base_plane, i); 622 623 drm_plane_helper_add(&plane->base_plane, 624 &kmb_plane_helper_funcs); 625 626 if (plane_type == DRM_PLANE_TYPE_PRIMARY) { 627 primary = plane; 628 kmb->plane = plane; 629 } 630 drm_dbg(drm, "%s : %d primary=%p\n", __func__, __LINE__, 631 &primary->base_plane); 632 plane->id = i; 633 } 634 635 /* Disable pipeline AXI read transactions for the DMA 636 * prior to setting graphics layers 637 */ 638 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA); 639 640 return primary; 641 cleanup: 642 drmm_kfree(drm, plane); 643 return ERR_PTR(ret); 644 } 645