1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic.h> 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_crtc.h> 9 #include <drm/drm_crtc_helper.h> 10 #include <drm/drm_fb_cma_helper.h> 11 #include <drm/drm_fb_helper.h> 12 #include <drm/drm_fourcc.h> 13 #include <drm/drm_gem_cma_helper.h> 14 #include <drm/drm_managed.h> 15 #include <drm/drm_plane_helper.h> 16 17 #include "kmb_drv.h" 18 #include "kmb_plane.h" 19 #include "kmb_regs.h" 20 21 const u32 layer_irqs[] = { 22 LCD_INT_VL0, 23 LCD_INT_VL1, 24 LCD_INT_GL0, 25 LCD_INT_GL1 26 }; 27 28 /* Conversion (yuv->rgb) matrix from myriadx */ 29 static const u32 csc_coef_lcd[] = { 30 1024, 0, 1436, 31 1024, -352, -731, 32 1024, 1814, 0, 33 -179, 125, -226 34 }; 35 36 /* Graphics layer (layers 2 & 3) formats, only packed formats are supported */ 37 static const u32 kmb_formats_g[] = { 38 DRM_FORMAT_RGB332, 39 DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, 40 DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, 41 DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, 42 DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, 43 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, 44 DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, 45 DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 46 DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, 47 }; 48 49 /* Video layer ( 0 & 1) formats, packed and planar formats are supported */ 50 static const u32 kmb_formats_v[] = { 51 /* packed formats */ 52 DRM_FORMAT_RGB332, 53 DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, 54 DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, 55 DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, 56 DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, 57 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, 58 DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, 59 DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, 61 /*planar formats */ 62 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, 63 DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, 64 DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, 65 DRM_FORMAT_NV12, DRM_FORMAT_NV21, 66 }; 67 68 static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) 69 { 70 int i; 71 72 for (i = 0; i < plane->format_count; i++) { 73 if (plane->format_types[i] == format) 74 return 0; 75 } 76 return -EINVAL; 77 } 78 79 static int kmb_plane_atomic_check(struct drm_plane *plane, 80 struct drm_plane_state *state) 81 { 82 struct drm_framebuffer *fb; 83 int ret; 84 struct drm_crtc_state *crtc_state; 85 bool can_position; 86 87 fb = state->fb; 88 if (!fb || !state->crtc) 89 return 0; 90 91 ret = check_pixel_format(plane, fb->format->format); 92 if (ret) 93 return ret; 94 95 if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT) 96 return -EINVAL; 97 if (state->crtc_w < KMB_MIN_WIDTH || state->crtc_h < KMB_MIN_HEIGHT) 98 return -EINVAL; 99 can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY); 100 crtc_state = 101 drm_atomic_get_existing_crtc_state(state->state, state->crtc); 102 return drm_atomic_helper_check_plane_state(state, crtc_state, 103 DRM_PLANE_HELPER_NO_SCALING, 104 DRM_PLANE_HELPER_NO_SCALING, 105 can_position, true); 106 } 107 108 static void kmb_plane_atomic_disable(struct drm_plane *plane, 109 struct drm_plane_state *state) 110 { 111 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 112 int plane_id = kmb_plane->id; 113 struct kmb_drm_private *kmb; 114 115 kmb = to_kmb(plane->dev); 116 117 switch (plane_id) { 118 case LAYER_0: 119 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE; 120 break; 121 case LAYER_1: 122 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE; 123 break; 124 case LAYER_2: 125 kmb->plane_status[plane_id].ctrl = LCD_CTRL_GL1_ENABLE; 126 break; 127 case LAYER_3: 128 kmb->plane_status[plane_id].ctrl = LCD_CTRL_GL2_ENABLE; 129 break; 130 } 131 132 kmb->plane_status[plane_id].disable = true; 133 } 134 135 static unsigned int get_pixel_format(u32 format) 136 { 137 unsigned int val = 0; 138 139 switch (format) { 140 /* planar formats */ 141 case DRM_FORMAT_YUV444: 142 val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE; 143 break; 144 case DRM_FORMAT_YVU444: 145 val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE 146 | LCD_LAYER_CRCB_ORDER; 147 break; 148 case DRM_FORMAT_YUV422: 149 val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE; 150 break; 151 case DRM_FORMAT_YVU422: 152 val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE 153 | LCD_LAYER_CRCB_ORDER; 154 break; 155 case DRM_FORMAT_YUV420: 156 val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE; 157 break; 158 case DRM_FORMAT_YVU420: 159 val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE 160 | LCD_LAYER_CRCB_ORDER; 161 break; 162 case DRM_FORMAT_NV12: 163 val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE; 164 break; 165 case DRM_FORMAT_NV21: 166 val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE 167 | LCD_LAYER_CRCB_ORDER; 168 break; 169 /* packed formats */ 170 /* looks hw requires B & G to be swapped when RGB */ 171 case DRM_FORMAT_RGB332: 172 val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER; 173 break; 174 case DRM_FORMAT_XBGR4444: 175 val = LCD_LAYER_FORMAT_RGBX4444; 176 break; 177 case DRM_FORMAT_ARGB4444: 178 val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; 179 break; 180 case DRM_FORMAT_ABGR4444: 181 val = LCD_LAYER_FORMAT_RGBA4444; 182 break; 183 case DRM_FORMAT_XRGB1555: 184 val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; 185 break; 186 case DRM_FORMAT_XBGR1555: 187 val = LCD_LAYER_FORMAT_XRGB1555; 188 break; 189 case DRM_FORMAT_ARGB1555: 190 val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; 191 break; 192 case DRM_FORMAT_ABGR1555: 193 val = LCD_LAYER_FORMAT_RGBA1555; 194 break; 195 case DRM_FORMAT_RGB565: 196 val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; 197 break; 198 case DRM_FORMAT_BGR565: 199 val = LCD_LAYER_FORMAT_RGB565; 200 break; 201 case DRM_FORMAT_RGB888: 202 val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; 203 break; 204 case DRM_FORMAT_BGR888: 205 val = LCD_LAYER_FORMAT_RGB888; 206 break; 207 case DRM_FORMAT_XRGB8888: 208 val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; 209 break; 210 case DRM_FORMAT_XBGR8888: 211 val = LCD_LAYER_FORMAT_RGBX8888; 212 break; 213 case DRM_FORMAT_ARGB8888: 214 val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; 215 break; 216 case DRM_FORMAT_ABGR8888: 217 val = LCD_LAYER_FORMAT_RGBA8888; 218 break; 219 } 220 DRM_INFO_ONCE("%s : %d format=0x%x val=0x%x\n", 221 __func__, __LINE__, format, val); 222 return val; 223 } 224 225 static unsigned int get_bits_per_pixel(const struct drm_format_info *format) 226 { 227 u32 bpp = 0; 228 unsigned int val = 0; 229 230 if (format->num_planes > 1) { 231 val = LCD_LAYER_8BPP; 232 return val; 233 } 234 235 bpp += 8 * format->cpp[0]; 236 237 switch (bpp) { 238 case 8: 239 val = LCD_LAYER_8BPP; 240 break; 241 case 16: 242 val = LCD_LAYER_16BPP; 243 break; 244 case 24: 245 val = LCD_LAYER_24BPP; 246 break; 247 case 32: 248 val = LCD_LAYER_32BPP; 249 break; 250 } 251 252 DRM_DEBUG("bpp=%d val=0x%x\n", bpp, val); 253 return val; 254 } 255 256 static void config_csc(struct kmb_drm_private *kmb, int plane_id) 257 { 258 /* YUV to RGB conversion using the fixed matrix csc_coef_lcd */ 259 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]); 260 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]); 261 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]); 262 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]); 263 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]); 264 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]); 265 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]); 266 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]); 267 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]); 268 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]); 269 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]); 270 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]); 271 } 272 273 static void kmb_plane_atomic_update(struct drm_plane *plane, 274 struct drm_plane_state *state) 275 { 276 struct drm_framebuffer *fb; 277 struct kmb_drm_private *kmb; 278 unsigned int width; 279 unsigned int height; 280 unsigned int dma_len; 281 struct kmb_plane *kmb_plane; 282 unsigned int dma_cfg; 283 unsigned int ctrl = 0, val = 0, out_format = 0; 284 unsigned int src_w, src_h, crtc_x, crtc_y; 285 unsigned char plane_id; 286 int num_planes; 287 static dma_addr_t addr[MAX_SUB_PLANES]; 288 289 if (!plane || !plane->state || !state) 290 return; 291 292 fb = plane->state->fb; 293 if (!fb) 294 return; 295 num_planes = fb->format->num_planes; 296 kmb_plane = to_kmb_plane(plane); 297 plane_id = kmb_plane->id; 298 299 kmb = to_kmb(plane->dev); 300 301 spin_lock_irq(&kmb->irq_lock); 302 if (kmb->kmb_under_flow || kmb->kmb_flush_done) { 303 spin_unlock_irq(&kmb->irq_lock); 304 drm_dbg(&kmb->drm, "plane_update:underflow!!!! returning"); 305 return; 306 } 307 spin_unlock_irq(&kmb->irq_lock); 308 309 src_w = (plane->state->src_w >> 16); 310 src_h = plane->state->src_h >> 16; 311 crtc_x = plane->state->crtc_x; 312 crtc_y = plane->state->crtc_y; 313 314 drm_dbg(&kmb->drm, 315 "src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x\n", 316 src_w, src_h, fb->format->format, fb->flags); 317 318 width = fb->width; 319 height = fb->height; 320 dma_len = (width * height * fb->format->cpp[0]); 321 drm_dbg(&kmb->drm, "dma_len=%d ", dma_len); 322 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN(plane_id), dma_len); 323 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); 324 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), 325 fb->pitches[0]); 326 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), 327 (width * fb->format->cpp[0])); 328 329 addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); 330 kmb_write_lcd(kmb, LCD_LAYERn_DMA_START_ADDR(plane_id), 331 addr[Y_PLANE] + fb->offsets[0]); 332 val = get_pixel_format(fb->format->format); 333 val |= get_bits_per_pixel(fb->format); 334 /* Program Cb/Cr for planar formats */ 335 if (num_planes > 1) { 336 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), 337 width * fb->format->cpp[0]); 338 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), 339 (width * fb->format->cpp[0])); 340 341 addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 342 U_PLANE); 343 /* check if Cb/Cr is swapped*/ 344 if (num_planes == 3 && (val & LCD_LAYER_CRCB_ORDER)) 345 kmb_write_lcd(kmb, 346 LCD_LAYERn_DMA_START_CR_ADR(plane_id), 347 addr[U_PLANE]); 348 else 349 kmb_write_lcd(kmb, 350 LCD_LAYERn_DMA_START_CB_ADR(plane_id), 351 addr[U_PLANE]); 352 353 if (num_planes == 3) { 354 kmb_write_lcd(kmb, 355 LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), 356 ((width) * fb->format->cpp[0])); 357 358 kmb_write_lcd(kmb, 359 LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), 360 ((width) * fb->format->cpp[0])); 361 362 addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, 363 plane->state, 364 V_PLANE); 365 366 /* check if Cb/Cr is swapped*/ 367 if (val & LCD_LAYER_CRCB_ORDER) 368 kmb_write_lcd(kmb, 369 LCD_LAYERn_DMA_START_CB_ADR(plane_id), 370 addr[V_PLANE]); 371 else 372 kmb_write_lcd(kmb, 373 LCD_LAYERn_DMA_START_CR_ADR(plane_id), 374 addr[V_PLANE]); 375 } 376 } 377 378 kmb_write_lcd(kmb, LCD_LAYERn_WIDTH(plane_id), src_w - 1); 379 kmb_write_lcd(kmb, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); 380 kmb_write_lcd(kmb, LCD_LAYERn_COL_START(plane_id), crtc_x); 381 kmb_write_lcd(kmb, LCD_LAYERn_ROW_START(plane_id), crtc_y); 382 383 val |= LCD_LAYER_FIFO_100; 384 385 if (val & LCD_LAYER_PLANAR_STORAGE) { 386 val |= LCD_LAYER_CSC_EN; 387 388 /* Enable CSC if input is planar and output is RGB */ 389 config_csc(kmb, plane_id); 390 } 391 392 kmb_write_lcd(kmb, LCD_LAYERn_CFG(plane_id), val); 393 394 switch (plane_id) { 395 case LAYER_0: 396 ctrl = LCD_CTRL_VL1_ENABLE; 397 break; 398 case LAYER_1: 399 ctrl = LCD_CTRL_VL2_ENABLE; 400 break; 401 case LAYER_2: 402 ctrl = LCD_CTRL_GL1_ENABLE; 403 break; 404 case LAYER_3: 405 ctrl = LCD_CTRL_GL2_ENABLE; 406 break; 407 } 408 409 ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE 410 | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; 411 412 /* LCD is connected to MIPI on kmb 413 * Therefore this bit is required for DSI Tx 414 */ 415 ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; 416 417 kmb_set_bitmask_lcd(kmb, LCD_CONTROL, ctrl); 418 419 /* FIXME no doc on how to set output format,these values are 420 * taken from the Myriadx tests 421 */ 422 out_format |= LCD_OUTF_FORMAT_RGB888; 423 424 /* Leave RGB order,conversion mode and clip mode to default */ 425 /* do not interleave RGB channels for mipi Tx compatibility */ 426 out_format |= LCD_OUTF_MIPI_RGB_MODE; 427 kmb_write_lcd(kmb, LCD_OUT_FORMAT_CFG, out_format); 428 429 dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | 430 LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; 431 432 /* Enable DMA */ 433 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); 434 drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg, 435 kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id))); 436 437 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF | 438 LCD_INT_DMA_ERR); 439 kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, LCD_INT_EOF | 440 LCD_INT_DMA_ERR); 441 } 442 443 static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { 444 .atomic_check = kmb_plane_atomic_check, 445 .atomic_update = kmb_plane_atomic_update, 446 .atomic_disable = kmb_plane_atomic_disable 447 }; 448 449 void kmb_plane_destroy(struct drm_plane *plane) 450 { 451 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 452 453 drm_plane_cleanup(plane); 454 kfree(kmb_plane); 455 } 456 457 static const struct drm_plane_funcs kmb_plane_funcs = { 458 .update_plane = drm_atomic_helper_update_plane, 459 .disable_plane = drm_atomic_helper_disable_plane, 460 .destroy = kmb_plane_destroy, 461 .reset = drm_atomic_helper_plane_reset, 462 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 463 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 464 }; 465 466 struct kmb_plane *kmb_plane_init(struct drm_device *drm) 467 { 468 struct kmb_drm_private *kmb = to_kmb(drm); 469 struct kmb_plane *plane = NULL; 470 struct kmb_plane *primary = NULL; 471 int i = 0; 472 int ret = 0; 473 enum drm_plane_type plane_type; 474 const u32 *plane_formats; 475 int num_plane_formats; 476 477 for (i = 0; i < KMB_MAX_PLANES; i++) { 478 plane = drmm_kzalloc(drm, sizeof(*plane), GFP_KERNEL); 479 480 if (!plane) { 481 drm_err(drm, "Failed to allocate plane\n"); 482 return ERR_PTR(-ENOMEM); 483 } 484 485 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 486 DRM_PLANE_TYPE_OVERLAY; 487 if (i < 2) { 488 plane_formats = kmb_formats_v; 489 num_plane_formats = ARRAY_SIZE(kmb_formats_v); 490 } else { 491 plane_formats = kmb_formats_g; 492 num_plane_formats = ARRAY_SIZE(kmb_formats_g); 493 } 494 495 ret = drm_universal_plane_init(drm, &plane->base_plane, 496 POSSIBLE_CRTCS, &kmb_plane_funcs, 497 plane_formats, num_plane_formats, 498 NULL, plane_type, "plane %d", i); 499 if (ret < 0) { 500 drm_err(drm, "drm_universal_plane_init failed (ret=%d)", 501 ret); 502 goto cleanup; 503 } 504 drm_dbg(drm, "%s : %d i=%d type=%d", 505 __func__, __LINE__, 506 i, plane_type); 507 drm_plane_helper_add(&plane->base_plane, 508 &kmb_plane_helper_funcs); 509 if (plane_type == DRM_PLANE_TYPE_PRIMARY) { 510 primary = plane; 511 kmb->plane = plane; 512 } 513 drm_dbg(drm, "%s : %d primary=%p\n", __func__, __LINE__, 514 &primary->base_plane); 515 plane->id = i; 516 } 517 518 return primary; 519 cleanup: 520 drmm_kfree(drm, plane); 521 return ERR_PTR(ret); 522 } 523