1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2018-2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic.h> 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_blend.h> 9 #include <drm/drm_crtc.h> 10 #include <drm/drm_crtc_helper.h> 11 #include <drm/drm_fb_cma_helper.h> 12 #include <drm/drm_fb_helper.h> 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_framebuffer.h> 15 #include <drm/drm_gem_cma_helper.h> 16 #include <drm/drm_managed.h> 17 18 #include "kmb_drv.h" 19 #include "kmb_plane.h" 20 #include "kmb_regs.h" 21 22 const u32 layer_irqs[] = { 23 LCD_INT_VL0, 24 LCD_INT_VL1, 25 LCD_INT_GL0, 26 LCD_INT_GL1 27 }; 28 29 /* Conversion (yuv->rgb) matrix from myriadx */ 30 static const u32 csc_coef_lcd[] = { 31 1024, 0, 1436, 32 1024, -352, -731, 33 1024, 1814, 0, 34 -179, 125, -226 35 }; 36 37 /* Graphics layer (layers 2 & 3) formats, only packed formats are supported */ 38 static const u32 kmb_formats_g[] = { 39 DRM_FORMAT_RGB332, 40 DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, 41 DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, 42 DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, 43 DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, 44 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, 45 DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, 46 DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 47 DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, 48 }; 49 50 /* Video layer ( 0 & 1) formats, packed and planar formats are supported */ 51 static const u32 kmb_formats_v[] = { 52 /* packed formats */ 53 DRM_FORMAT_RGB332, 54 DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, 55 DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, 56 DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, 57 DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, 58 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, 59 DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, 60 DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 61 DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, 62 /*planar formats */ 63 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, 64 DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, 65 DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, 66 DRM_FORMAT_NV12, DRM_FORMAT_NV21, 67 }; 68 69 static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) 70 { 71 struct kmb_drm_private *kmb; 72 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 73 int i; 74 int plane_id = kmb_plane->id; 75 struct disp_cfg init_disp_cfg; 76 77 kmb = to_kmb(plane->dev); 78 init_disp_cfg = kmb->init_disp_cfg[plane_id]; 79 /* Due to HW limitations, changing pixel format after initial 80 * plane configuration is not supported. 81 */ 82 if (init_disp_cfg.format && init_disp_cfg.format != format) { 83 drm_dbg(&kmb->drm, "Cannot change format after initial plane configuration"); 84 return -EINVAL; 85 } 86 for (i = 0; i < plane->format_count; i++) { 87 if (plane->format_types[i] == format) 88 return 0; 89 } 90 return -EINVAL; 91 } 92 93 static int kmb_plane_atomic_check(struct drm_plane *plane, 94 struct drm_atomic_state *state) 95 { 96 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 97 plane); 98 struct kmb_drm_private *kmb; 99 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 100 int plane_id = kmb_plane->id; 101 struct disp_cfg init_disp_cfg; 102 struct drm_framebuffer *fb; 103 int ret; 104 struct drm_crtc_state *crtc_state; 105 bool can_position; 106 107 kmb = to_kmb(plane->dev); 108 init_disp_cfg = kmb->init_disp_cfg[plane_id]; 109 fb = new_plane_state->fb; 110 if (!fb || !new_plane_state->crtc) 111 return 0; 112 113 ret = check_pixel_format(plane, fb->format->format); 114 if (ret) 115 return ret; 116 117 if (new_plane_state->crtc_w > KMB_FB_MAX_WIDTH || 118 new_plane_state->crtc_h > KMB_FB_MAX_HEIGHT || 119 new_plane_state->crtc_w < KMB_FB_MIN_WIDTH || 120 new_plane_state->crtc_h < KMB_FB_MIN_HEIGHT) 121 return -EINVAL; 122 123 /* Due to HW limitations, changing plane height or width after 124 * initial plane configuration is not supported. 125 */ 126 if ((init_disp_cfg.width && init_disp_cfg.height) && 127 (init_disp_cfg.width != fb->width || 128 init_disp_cfg.height != fb->height)) { 129 drm_dbg(&kmb->drm, "Cannot change plane height or width after initial configuration"); 130 return -EINVAL; 131 } 132 can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY); 133 crtc_state = 134 drm_atomic_get_existing_crtc_state(state, 135 new_plane_state->crtc); 136 return drm_atomic_helper_check_plane_state(new_plane_state, 137 crtc_state, 138 DRM_PLANE_NO_SCALING, 139 DRM_PLANE_NO_SCALING, 140 can_position, true); 141 } 142 143 static void kmb_plane_atomic_disable(struct drm_plane *plane, 144 struct drm_atomic_state *state) 145 { 146 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 147 int plane_id = kmb_plane->id; 148 struct kmb_drm_private *kmb; 149 150 kmb = to_kmb(plane->dev); 151 152 if (WARN_ON(plane_id >= KMB_MAX_PLANES)) 153 return; 154 155 switch (plane_id) { 156 case LAYER_0: 157 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE; 158 break; 159 case LAYER_1: 160 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE; 161 break; 162 } 163 164 kmb->plane_status[plane_id].disable = true; 165 } 166 167 static unsigned int get_pixel_format(u32 format) 168 { 169 unsigned int val = 0; 170 171 switch (format) { 172 /* planar formats */ 173 case DRM_FORMAT_YUV444: 174 val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE; 175 break; 176 case DRM_FORMAT_YVU444: 177 val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE 178 | LCD_LAYER_CRCB_ORDER; 179 break; 180 case DRM_FORMAT_YUV422: 181 val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE; 182 break; 183 case DRM_FORMAT_YVU422: 184 val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE 185 | LCD_LAYER_CRCB_ORDER; 186 break; 187 case DRM_FORMAT_YUV420: 188 val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE; 189 break; 190 case DRM_FORMAT_YVU420: 191 val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE 192 | LCD_LAYER_CRCB_ORDER; 193 break; 194 case DRM_FORMAT_NV12: 195 val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE; 196 break; 197 case DRM_FORMAT_NV21: 198 val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE 199 | LCD_LAYER_CRCB_ORDER; 200 break; 201 /* packed formats */ 202 /* looks hw requires B & G to be swapped when RGB */ 203 case DRM_FORMAT_RGB332: 204 val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER; 205 break; 206 case DRM_FORMAT_XBGR4444: 207 val = LCD_LAYER_FORMAT_RGBX4444; 208 break; 209 case DRM_FORMAT_ARGB4444: 210 val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; 211 break; 212 case DRM_FORMAT_ABGR4444: 213 val = LCD_LAYER_FORMAT_RGBA4444; 214 break; 215 case DRM_FORMAT_XRGB1555: 216 val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; 217 break; 218 case DRM_FORMAT_XBGR1555: 219 val = LCD_LAYER_FORMAT_XRGB1555; 220 break; 221 case DRM_FORMAT_ARGB1555: 222 val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; 223 break; 224 case DRM_FORMAT_ABGR1555: 225 val = LCD_LAYER_FORMAT_RGBA1555; 226 break; 227 case DRM_FORMAT_RGB565: 228 val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; 229 break; 230 case DRM_FORMAT_BGR565: 231 val = LCD_LAYER_FORMAT_RGB565; 232 break; 233 case DRM_FORMAT_RGB888: 234 val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; 235 break; 236 case DRM_FORMAT_BGR888: 237 val = LCD_LAYER_FORMAT_RGB888; 238 break; 239 case DRM_FORMAT_XRGB8888: 240 val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; 241 break; 242 case DRM_FORMAT_XBGR8888: 243 val = LCD_LAYER_FORMAT_RGBX8888; 244 break; 245 case DRM_FORMAT_ARGB8888: 246 val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; 247 break; 248 case DRM_FORMAT_ABGR8888: 249 val = LCD_LAYER_FORMAT_RGBA8888; 250 break; 251 } 252 DRM_INFO_ONCE("%s : %d format=0x%x val=0x%x\n", 253 __func__, __LINE__, format, val); 254 return val; 255 } 256 257 static unsigned int get_bits_per_pixel(const struct drm_format_info *format) 258 { 259 u32 bpp = 0; 260 unsigned int val = 0; 261 262 if (format->num_planes > 1) { 263 val = LCD_LAYER_8BPP; 264 return val; 265 } 266 267 bpp += 8 * format->cpp[0]; 268 269 switch (bpp) { 270 case 8: 271 val = LCD_LAYER_8BPP; 272 break; 273 case 16: 274 val = LCD_LAYER_16BPP; 275 break; 276 case 24: 277 val = LCD_LAYER_24BPP; 278 break; 279 case 32: 280 val = LCD_LAYER_32BPP; 281 break; 282 } 283 284 DRM_DEBUG("bpp=%d val=0x%x\n", bpp, val); 285 return val; 286 } 287 288 static void config_csc(struct kmb_drm_private *kmb, int plane_id) 289 { 290 /* YUV to RGB conversion using the fixed matrix csc_coef_lcd */ 291 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]); 292 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]); 293 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]); 294 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]); 295 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]); 296 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]); 297 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]); 298 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]); 299 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]); 300 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]); 301 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]); 302 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]); 303 } 304 305 static void kmb_plane_set_alpha(struct kmb_drm_private *kmb, 306 const struct drm_plane_state *state, 307 unsigned char plane_id, 308 unsigned int *val) 309 { 310 u16 plane_alpha = state->alpha; 311 u16 pixel_blend_mode = state->pixel_blend_mode; 312 int has_alpha = state->fb->format->has_alpha; 313 314 if (plane_alpha != DRM_BLEND_ALPHA_OPAQUE) 315 *val |= LCD_LAYER_ALPHA_STATIC; 316 317 if (has_alpha) { 318 switch (pixel_blend_mode) { 319 case DRM_MODE_BLEND_PIXEL_NONE: 320 break; 321 case DRM_MODE_BLEND_PREMULTI: 322 *val |= LCD_LAYER_ALPHA_EMBED | LCD_LAYER_ALPHA_PREMULT; 323 break; 324 case DRM_MODE_BLEND_COVERAGE: 325 *val |= LCD_LAYER_ALPHA_EMBED; 326 break; 327 default: 328 DRM_DEBUG("Missing pixel blend mode case (%s == %ld)\n", 329 __stringify(pixel_blend_mode), 330 (long)pixel_blend_mode); 331 break; 332 } 333 } 334 335 if (plane_alpha == DRM_BLEND_ALPHA_OPAQUE && !has_alpha) { 336 *val &= LCD_LAYER_ALPHA_DISABLED; 337 return; 338 } 339 340 kmb_write_lcd(kmb, LCD_LAYERn_ALPHA(plane_id), plane_alpha); 341 } 342 343 static void kmb_plane_atomic_update(struct drm_plane *plane, 344 struct drm_atomic_state *state) 345 { 346 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 347 plane); 348 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 349 plane); 350 struct drm_framebuffer *fb; 351 struct kmb_drm_private *kmb; 352 unsigned int width; 353 unsigned int height; 354 unsigned int dma_len; 355 struct kmb_plane *kmb_plane; 356 unsigned int dma_cfg; 357 unsigned int ctrl = 0, val = 0, out_format = 0; 358 unsigned int src_w, src_h, crtc_x, crtc_y; 359 unsigned char plane_id; 360 int num_planes; 361 static dma_addr_t addr[MAX_SUB_PLANES]; 362 struct disp_cfg *init_disp_cfg; 363 364 if (!plane || !new_plane_state || !old_plane_state) 365 return; 366 367 fb = new_plane_state->fb; 368 if (!fb) 369 return; 370 371 num_planes = fb->format->num_planes; 372 kmb_plane = to_kmb_plane(plane); 373 374 kmb = to_kmb(plane->dev); 375 plane_id = kmb_plane->id; 376 377 spin_lock_irq(&kmb->irq_lock); 378 if (kmb->kmb_under_flow || kmb->kmb_flush_done) { 379 spin_unlock_irq(&kmb->irq_lock); 380 drm_dbg(&kmb->drm, "plane_update:underflow!!!! returning"); 381 return; 382 } 383 spin_unlock_irq(&kmb->irq_lock); 384 385 init_disp_cfg = &kmb->init_disp_cfg[plane_id]; 386 src_w = new_plane_state->src_w >> 16; 387 src_h = new_plane_state->src_h >> 16; 388 crtc_x = new_plane_state->crtc_x; 389 crtc_y = new_plane_state->crtc_y; 390 391 drm_dbg(&kmb->drm, 392 "src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x\n", 393 src_w, src_h, fb->format->format, fb->flags); 394 395 width = fb->width; 396 height = fb->height; 397 dma_len = (width * height * fb->format->cpp[0]); 398 drm_dbg(&kmb->drm, "dma_len=%d ", dma_len); 399 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN(plane_id), dma_len); 400 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); 401 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), 402 fb->pitches[0]); 403 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), 404 (width * fb->format->cpp[0])); 405 406 addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, new_plane_state, 0); 407 kmb_write_lcd(kmb, LCD_LAYERn_DMA_START_ADDR(plane_id), 408 addr[Y_PLANE] + fb->offsets[0]); 409 val = get_pixel_format(fb->format->format); 410 val |= get_bits_per_pixel(fb->format); 411 /* Program Cb/Cr for planar formats */ 412 if (num_planes > 1) { 413 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), 414 width * fb->format->cpp[0]); 415 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), 416 (width * fb->format->cpp[0])); 417 418 addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, new_plane_state, 419 U_PLANE); 420 /* check if Cb/Cr is swapped*/ 421 if (num_planes == 3 && (val & LCD_LAYER_CRCB_ORDER)) 422 kmb_write_lcd(kmb, 423 LCD_LAYERn_DMA_START_CR_ADR(plane_id), 424 addr[U_PLANE]); 425 else 426 kmb_write_lcd(kmb, 427 LCD_LAYERn_DMA_START_CB_ADR(plane_id), 428 addr[U_PLANE]); 429 430 if (num_planes == 3) { 431 kmb_write_lcd(kmb, 432 LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), 433 ((width) * fb->format->cpp[0])); 434 435 kmb_write_lcd(kmb, 436 LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), 437 ((width) * fb->format->cpp[0])); 438 439 addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, 440 new_plane_state, 441 V_PLANE); 442 443 /* check if Cb/Cr is swapped*/ 444 if (val & LCD_LAYER_CRCB_ORDER) 445 kmb_write_lcd(kmb, 446 LCD_LAYERn_DMA_START_CB_ADR(plane_id), 447 addr[V_PLANE]); 448 else 449 kmb_write_lcd(kmb, 450 LCD_LAYERn_DMA_START_CR_ADR(plane_id), 451 addr[V_PLANE]); 452 } 453 } 454 455 kmb_write_lcd(kmb, LCD_LAYERn_WIDTH(plane_id), src_w - 1); 456 kmb_write_lcd(kmb, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); 457 kmb_write_lcd(kmb, LCD_LAYERn_COL_START(plane_id), crtc_x); 458 kmb_write_lcd(kmb, LCD_LAYERn_ROW_START(plane_id), crtc_y); 459 460 val |= LCD_LAYER_FIFO_100; 461 462 if (val & LCD_LAYER_PLANAR_STORAGE) { 463 val |= LCD_LAYER_CSC_EN; 464 465 /* Enable CSC if input is planar and output is RGB */ 466 config_csc(kmb, plane_id); 467 } 468 469 kmb_plane_set_alpha(kmb, plane->state, plane_id, &val); 470 471 kmb_write_lcd(kmb, LCD_LAYERn_CFG(plane_id), val); 472 473 /* Configure LCD_CONTROL */ 474 ctrl = kmb_read_lcd(kmb, LCD_CONTROL); 475 476 /* Set layer blending config */ 477 ctrl &= ~LCD_CTRL_ALPHA_ALL; 478 ctrl |= LCD_CTRL_ALPHA_BOTTOM_VL1 | 479 LCD_CTRL_ALPHA_BLEND_VL2; 480 481 ctrl &= ~LCD_CTRL_ALPHA_BLEND_BKGND_DISABLE; 482 483 switch (plane_id) { 484 case LAYER_0: 485 ctrl |= LCD_CTRL_VL1_ENABLE; 486 break; 487 case LAYER_1: 488 ctrl |= LCD_CTRL_VL2_ENABLE; 489 break; 490 case LAYER_2: 491 ctrl |= LCD_CTRL_GL1_ENABLE; 492 break; 493 case LAYER_3: 494 ctrl |= LCD_CTRL_GL2_ENABLE; 495 break; 496 } 497 498 ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE 499 | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; 500 501 /* LCD is connected to MIPI on kmb 502 * Therefore this bit is required for DSI Tx 503 */ 504 ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; 505 506 kmb_write_lcd(kmb, LCD_CONTROL, ctrl); 507 508 /* Enable pipeline AXI read transactions for the DMA 509 * after setting graphics layers. This must be done 510 * in a separate write cycle. 511 */ 512 kmb_set_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA); 513 514 /* FIXME no doc on how to set output format, these values are taken 515 * from the Myriadx tests 516 */ 517 out_format |= LCD_OUTF_FORMAT_RGB888; 518 519 /* Leave RGB order,conversion mode and clip mode to default */ 520 /* do not interleave RGB channels for mipi Tx compatibility */ 521 out_format |= LCD_OUTF_MIPI_RGB_MODE; 522 kmb_write_lcd(kmb, LCD_OUT_FORMAT_CFG, out_format); 523 524 dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | 525 LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; 526 527 /* Enable DMA */ 528 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); 529 530 /* Save initial display config */ 531 if (!init_disp_cfg->width || 532 !init_disp_cfg->height || 533 !init_disp_cfg->format) { 534 init_disp_cfg->width = width; 535 init_disp_cfg->height = height; 536 init_disp_cfg->format = fb->format->format; 537 } 538 539 drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg, 540 kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id))); 541 542 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF | 543 LCD_INT_DMA_ERR); 544 kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, LCD_INT_EOF | 545 LCD_INT_DMA_ERR); 546 } 547 548 static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { 549 .atomic_check = kmb_plane_atomic_check, 550 .atomic_update = kmb_plane_atomic_update, 551 .atomic_disable = kmb_plane_atomic_disable 552 }; 553 554 void kmb_plane_destroy(struct drm_plane *plane) 555 { 556 struct kmb_plane *kmb_plane = to_kmb_plane(plane); 557 558 drm_plane_cleanup(plane); 559 kfree(kmb_plane); 560 } 561 562 static const struct drm_plane_funcs kmb_plane_funcs = { 563 .update_plane = drm_atomic_helper_update_plane, 564 .disable_plane = drm_atomic_helper_disable_plane, 565 .destroy = kmb_plane_destroy, 566 .reset = drm_atomic_helper_plane_reset, 567 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 568 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 569 }; 570 571 struct kmb_plane *kmb_plane_init(struct drm_device *drm) 572 { 573 struct kmb_drm_private *kmb = to_kmb(drm); 574 struct kmb_plane *plane = NULL; 575 struct kmb_plane *primary = NULL; 576 int i = 0; 577 int ret = 0; 578 enum drm_plane_type plane_type; 579 const u32 *plane_formats; 580 int num_plane_formats; 581 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 582 BIT(DRM_MODE_BLEND_PREMULTI) | 583 BIT(DRM_MODE_BLEND_COVERAGE); 584 585 for (i = 0; i < KMB_MAX_PLANES; i++) { 586 plane = drmm_kzalloc(drm, sizeof(*plane), GFP_KERNEL); 587 588 if (!plane) { 589 drm_err(drm, "Failed to allocate plane\n"); 590 return ERR_PTR(-ENOMEM); 591 } 592 593 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : 594 DRM_PLANE_TYPE_OVERLAY; 595 if (i < 2) { 596 plane_formats = kmb_formats_v; 597 num_plane_formats = ARRAY_SIZE(kmb_formats_v); 598 } else { 599 plane_formats = kmb_formats_g; 600 num_plane_formats = ARRAY_SIZE(kmb_formats_g); 601 } 602 603 ret = drm_universal_plane_init(drm, &plane->base_plane, 604 POSSIBLE_CRTCS, &kmb_plane_funcs, 605 plane_formats, num_plane_formats, 606 NULL, plane_type, "plane %d", i); 607 if (ret < 0) { 608 drm_err(drm, "drm_universal_plane_init failed (ret=%d)", 609 ret); 610 goto cleanup; 611 } 612 drm_dbg(drm, "%s : %d i=%d type=%d", 613 __func__, __LINE__, 614 i, plane_type); 615 drm_plane_create_alpha_property(&plane->base_plane); 616 617 drm_plane_create_blend_mode_property(&plane->base_plane, 618 blend_caps); 619 620 drm_plane_create_zpos_immutable_property(&plane->base_plane, i); 621 622 drm_plane_helper_add(&plane->base_plane, 623 &kmb_plane_helper_funcs); 624 625 if (plane_type == DRM_PLANE_TYPE_PRIMARY) { 626 primary = plane; 627 kmb->plane = plane; 628 } 629 drm_dbg(drm, "%s : %d primary=%p\n", __func__, __LINE__, 630 &primary->base_plane); 631 plane->id = i; 632 } 633 634 /* Disable pipeline AXI read transactions for the DMA 635 * prior to setting graphics layers 636 */ 637 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA); 638 639 return primary; 640 cleanup: 641 drmm_kfree(drm, plane); 642 return ERR_PTR(ret); 643 } 644