1*98521f4dSAnitha Chrisanthus /* SPDX-License-Identifier: GPL-2.0-only 2*98521f4dSAnitha Chrisanthus * 3*98521f4dSAnitha Chrisanthus * Copyright © 2019-2020 Intel Corporation 4*98521f4dSAnitha Chrisanthus */ 5*98521f4dSAnitha Chrisanthus 6*98521f4dSAnitha Chrisanthus #ifndef __KMB_DSI_H__ 7*98521f4dSAnitha Chrisanthus #define __KMB_DSI_H__ 8*98521f4dSAnitha Chrisanthus 9*98521f4dSAnitha Chrisanthus #include <drm/drm_encoder.h> 10*98521f4dSAnitha Chrisanthus #include <drm/drm_mipi_dsi.h> 11*98521f4dSAnitha Chrisanthus 12*98521f4dSAnitha Chrisanthus /* MIPI TX CFG */ 13*98521f4dSAnitha Chrisanthus #define MIPI_TX_LANE_DATA_RATE_MBPS 891 14*98521f4dSAnitha Chrisanthus #define MIPI_TX_REF_CLK_KHZ 24000 15*98521f4dSAnitha Chrisanthus #define MIPI_TX_CFG_CLK_KHZ 24000 16*98521f4dSAnitha Chrisanthus #define MIPI_TX_BPP 24 17*98521f4dSAnitha Chrisanthus 18*98521f4dSAnitha Chrisanthus /* DPHY Tx test codes*/ 19*98521f4dSAnitha Chrisanthus #define TEST_CODE_FSM_CONTROL 0x03 20*98521f4dSAnitha Chrisanthus #define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C 21*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E 22*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F 23*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_VCO_CTRL 0x12 24*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_GMP_CTRL 0x13 25*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14 26*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_LOCK_FILTER 0x15 27*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_UNLOCK_FILTER 0x16 28*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_INPUT_DIVIDER 0x17 29*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18 30*98521f4dSAnitha Chrisanthus #define PLL_FEEDBACK_DIVIDER_HIGH BIT(7) 31*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 32*98521f4dSAnitha Chrisanthus #define PLL_N_OVR_EN BIT(4) 33*98521f4dSAnitha Chrisanthus #define PLL_M_OVR_EN BIT(5) 34*98521f4dSAnitha Chrisanthus #define TEST_CODE_VOD_LEVEL 0x24 35*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C 36*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_LOCK_DETECTOR 0x1D 37*98521f4dSAnitha Chrisanthus #define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 38*98521f4dSAnitha Chrisanthus #define TEST_CODE_PLL_ANALOG_PROG 0x1F 39*98521f4dSAnitha Chrisanthus #define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 40*98521f4dSAnitha Chrisanthus #define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 41*98521f4dSAnitha Chrisanthus #define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 42*98521f4dSAnitha Chrisanthus 43*98521f4dSAnitha Chrisanthus /* DPHY params */ 44*98521f4dSAnitha Chrisanthus #define PLL_N_MIN 0 45*98521f4dSAnitha Chrisanthus #define PLL_N_MAX 15 46*98521f4dSAnitha Chrisanthus #define PLL_M_MIN 62 47*98521f4dSAnitha Chrisanthus #define PLL_M_MAX 623 48*98521f4dSAnitha Chrisanthus #define PLL_FVCO_MAX 1250 49*98521f4dSAnitha Chrisanthus 50*98521f4dSAnitha Chrisanthus #define TIMEOUT 600 51*98521f4dSAnitha Chrisanthus 52*98521f4dSAnitha Chrisanthus #define MIPI_TX_FRAME_GEN 4 53*98521f4dSAnitha Chrisanthus #define MIPI_TX_FRAME_GEN_SECTIONS 4 54*98521f4dSAnitha Chrisanthus #define MIPI_CTRL_VIRTUAL_CHANNELS 4 55*98521f4dSAnitha Chrisanthus #define MIPI_D_LANES_PER_DPHY 2 56*98521f4dSAnitha Chrisanthus #define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 57*98521f4dSAnitha Chrisanthus #define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511 58*98521f4dSAnitha Chrisanthus /* 2 Data Lanes per D-PHY */ 59*98521f4dSAnitha Chrisanthus #define MIPI_DPHY_D_LANES 2 60*98521f4dSAnitha Chrisanthus #define MIPI_DPHY_DEFAULT_BIT_RATES 63 61*98521f4dSAnitha Chrisanthus 62*98521f4dSAnitha Chrisanthus #define KMB_MIPI_DEFAULT_CLK 24000000 63*98521f4dSAnitha Chrisanthus #define KMB_MIPI_DEFAULT_CFG_CLK 24000000 64*98521f4dSAnitha Chrisanthus 65*98521f4dSAnitha Chrisanthus #define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base) 66*98521f4dSAnitha Chrisanthus 67*98521f4dSAnitha Chrisanthus struct kmb_dsi { 68*98521f4dSAnitha Chrisanthus struct drm_encoder base; 69*98521f4dSAnitha Chrisanthus struct device *dev; 70*98521f4dSAnitha Chrisanthus struct platform_device *pdev; 71*98521f4dSAnitha Chrisanthus struct mipi_dsi_host *host; 72*98521f4dSAnitha Chrisanthus struct mipi_dsi_device *device; 73*98521f4dSAnitha Chrisanthus struct drm_bridge *adv_bridge; 74*98521f4dSAnitha Chrisanthus void __iomem *mipi_mmio; 75*98521f4dSAnitha Chrisanthus struct clk *clk_mipi; 76*98521f4dSAnitha Chrisanthus struct clk *clk_mipi_ecfg; 77*98521f4dSAnitha Chrisanthus struct clk *clk_mipi_cfg; 78*98521f4dSAnitha Chrisanthus int sys_clk_mhz; 79*98521f4dSAnitha Chrisanthus }; 80*98521f4dSAnitha Chrisanthus 81*98521f4dSAnitha Chrisanthus /* DPHY Tx test codes */ 82*98521f4dSAnitha Chrisanthus 83*98521f4dSAnitha Chrisanthus enum mipi_ctrl_num { 84*98521f4dSAnitha Chrisanthus MIPI_CTRL0 = 0, 85*98521f4dSAnitha Chrisanthus MIPI_CTRL1, 86*98521f4dSAnitha Chrisanthus MIPI_CTRL2, 87*98521f4dSAnitha Chrisanthus MIPI_CTRL3, 88*98521f4dSAnitha Chrisanthus MIPI_CTRL4, 89*98521f4dSAnitha Chrisanthus MIPI_CTRL5, 90*98521f4dSAnitha Chrisanthus MIPI_CTRL6, 91*98521f4dSAnitha Chrisanthus MIPI_CTRL7, 92*98521f4dSAnitha Chrisanthus MIPI_CTRL8, 93*98521f4dSAnitha Chrisanthus MIPI_CTRL9, 94*98521f4dSAnitha Chrisanthus MIPI_CTRL_NA 95*98521f4dSAnitha Chrisanthus }; 96*98521f4dSAnitha Chrisanthus 97*98521f4dSAnitha Chrisanthus enum mipi_dphy_num { 98*98521f4dSAnitha Chrisanthus MIPI_DPHY0 = 0, 99*98521f4dSAnitha Chrisanthus MIPI_DPHY1, 100*98521f4dSAnitha Chrisanthus MIPI_DPHY2, 101*98521f4dSAnitha Chrisanthus MIPI_DPHY3, 102*98521f4dSAnitha Chrisanthus MIPI_DPHY4, 103*98521f4dSAnitha Chrisanthus MIPI_DPHY5, 104*98521f4dSAnitha Chrisanthus MIPI_DPHY6, 105*98521f4dSAnitha Chrisanthus MIPI_DPHY7, 106*98521f4dSAnitha Chrisanthus MIPI_DPHY8, 107*98521f4dSAnitha Chrisanthus MIPI_DPHY9, 108*98521f4dSAnitha Chrisanthus MIPI_DPHY_NA 109*98521f4dSAnitha Chrisanthus }; 110*98521f4dSAnitha Chrisanthus 111*98521f4dSAnitha Chrisanthus enum mipi_dir { 112*98521f4dSAnitha Chrisanthus MIPI_RX, 113*98521f4dSAnitha Chrisanthus MIPI_TX 114*98521f4dSAnitha Chrisanthus }; 115*98521f4dSAnitha Chrisanthus 116*98521f4dSAnitha Chrisanthus enum mipi_ctrl_type { 117*98521f4dSAnitha Chrisanthus MIPI_DSI, 118*98521f4dSAnitha Chrisanthus MIPI_CSI 119*98521f4dSAnitha Chrisanthus }; 120*98521f4dSAnitha Chrisanthus 121*98521f4dSAnitha Chrisanthus enum mipi_data_if { 122*98521f4dSAnitha Chrisanthus MIPI_IF_DMA, 123*98521f4dSAnitha Chrisanthus MIPI_IF_PARALLEL 124*98521f4dSAnitha Chrisanthus }; 125*98521f4dSAnitha Chrisanthus 126*98521f4dSAnitha Chrisanthus enum mipi_data_mode { 127*98521f4dSAnitha Chrisanthus MIPI_DATA_MODE0, 128*98521f4dSAnitha Chrisanthus MIPI_DATA_MODE1, 129*98521f4dSAnitha Chrisanthus MIPI_DATA_MODE2, 130*98521f4dSAnitha Chrisanthus MIPI_DATA_MODE3 131*98521f4dSAnitha Chrisanthus }; 132*98521f4dSAnitha Chrisanthus 133*98521f4dSAnitha Chrisanthus enum mipi_dsi_video_mode { 134*98521f4dSAnitha Chrisanthus DSI_VIDEO_MODE_NO_BURST_PULSE, 135*98521f4dSAnitha Chrisanthus DSI_VIDEO_MODE_NO_BURST_EVENT, 136*98521f4dSAnitha Chrisanthus DSI_VIDEO_MODE_BURST 137*98521f4dSAnitha Chrisanthus }; 138*98521f4dSAnitha Chrisanthus 139*98521f4dSAnitha Chrisanthus enum mipi_dsi_blanking_mode { 140*98521f4dSAnitha Chrisanthus TRANSITION_TO_LOW_POWER, 141*98521f4dSAnitha Chrisanthus SEND_BLANK_PACKET 142*98521f4dSAnitha Chrisanthus }; 143*98521f4dSAnitha Chrisanthus 144*98521f4dSAnitha Chrisanthus enum mipi_dsi_eotp { 145*98521f4dSAnitha Chrisanthus DSI_EOTP_DISABLED, 146*98521f4dSAnitha Chrisanthus DSI_EOTP_ENABLES 147*98521f4dSAnitha Chrisanthus }; 148*98521f4dSAnitha Chrisanthus 149*98521f4dSAnitha Chrisanthus enum mipi_dsi_data_type { 150*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_00 = 0x00, 151*98521f4dSAnitha Chrisanthus DSI_SP_DT_VSYNC_START = 0x01, 152*98521f4dSAnitha Chrisanthus DSI_SP_DT_COLOR_MODE_OFF = 0x02, 153*98521f4dSAnitha Chrisanthus DSI_SP_DT_GENERIC_SHORT_WR = 0x03, 154*98521f4dSAnitha Chrisanthus DSI_SP_DT_GENERIC_RD = 0x04, 155*98521f4dSAnitha Chrisanthus DSI_SP_DT_DCS_SHORT_WR = 0x05, 156*98521f4dSAnitha Chrisanthus DSI_SP_DT_DCS_RD = 0x06, 157*98521f4dSAnitha Chrisanthus DSI_SP_DT_EOTP = 0x08, 158*98521f4dSAnitha Chrisanthus DSI_LP_DT_NULL = 0x09, 159*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_0A = 0x0a, 160*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_0B = 0x0b, 161*98521f4dSAnitha Chrisanthus DSI_LP_DT_LPPS_YCBCR422_20B = 0x0c, 162*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_RGB101010_30B = 0x0d, 163*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_RGB565_16B = 0x0e, 164*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_0F = 0x0f, 165*98521f4dSAnitha Chrisanthus 166*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_10 = 0x10, 167*98521f4dSAnitha Chrisanthus DSI_SP_DT_VSYNC_END = 0x11, 168*98521f4dSAnitha Chrisanthus DSI_SP_DT_COLOR_MODE_ON = 0x12, 169*98521f4dSAnitha Chrisanthus DSI_SP_DT_GENERIC_SHORT_WR_1PAR = 0x13, 170*98521f4dSAnitha Chrisanthus DSI_SP_DT_GENERIC_RD_1PAR = 0x14, 171*98521f4dSAnitha Chrisanthus DSI_SP_DT_DCS_SHORT_WR_1PAR = 0x15, 172*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_16 = 0x16, 173*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_17 = 0x17, 174*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_18 = 0x18, 175*98521f4dSAnitha Chrisanthus DSI_LP_DT_BLANK = 0x19, 176*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_1A = 0x1a, 177*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_1B = 0x1b, 178*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_YCBCR422_24B = 0x1c, 179*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_RGB121212_36B = 0x1d, 180*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_RGB666_18B = 0x1e, 181*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_1F = 0x1f, 182*98521f4dSAnitha Chrisanthus 183*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_20 = 0x20, 184*98521f4dSAnitha Chrisanthus DSI_SP_DT_HSYNC_START = 0x21, 185*98521f4dSAnitha Chrisanthus DSI_SP_DT_SHUT_DOWN_PERIPH_CMD = 0x22, 186*98521f4dSAnitha Chrisanthus DSI_SP_DT_GENERIC_SHORT_WR_2PAR = 0x23, 187*98521f4dSAnitha Chrisanthus DSI_SP_DT_GENERIC_RD_2PAR = 0x24, 188*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_25 = 0x25, 189*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_26 = 0x26, 190*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_27 = 0x27, 191*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_28 = 0x28, 192*98521f4dSAnitha Chrisanthus DSI_LP_DT_GENERIC_LONG_WR = 0x29, 193*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_2A = 0x2a, 194*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_2B = 0x2b, 195*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_YCBCR422_16B = 0x2c, 196*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_2D = 0x2d, 197*98521f4dSAnitha Chrisanthus DSI_LP_DT_LPPS_RGB666_18B = 0x2e, 198*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_2F = 0x2f, 199*98521f4dSAnitha Chrisanthus 200*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_30 = 0x30, 201*98521f4dSAnitha Chrisanthus DSI_SP_DT_HSYNC_END = 0x31, 202*98521f4dSAnitha Chrisanthus DSI_SP_DT_TURN_ON_PERIPH_CMD = 0x32, 203*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_33 = 0x33, 204*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_34 = 0x34, 205*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_35 = 0x35, 206*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_36 = 0x36, 207*98521f4dSAnitha Chrisanthus DSI_SP_DT_SET_MAX_RETURN_PKT_SIZE = 0x37, 208*98521f4dSAnitha Chrisanthus DSI_SP_DT_RESERVED_38 = 0x38, 209*98521f4dSAnitha Chrisanthus DSI_LP_DT_DSC_LONG_WR = 0x39, 210*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_3A = 0x3a, 211*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_3B = 0x3b, 212*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_3C = 0x3c, 213*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_YCBCR420_12B = 0x3d, 214*98521f4dSAnitha Chrisanthus DSI_LP_DT_PPS_RGB888_24B = 0x3e, 215*98521f4dSAnitha Chrisanthus DSI_LP_DT_RESERVED_3F = 0x3f 216*98521f4dSAnitha Chrisanthus }; 217*98521f4dSAnitha Chrisanthus 218*98521f4dSAnitha Chrisanthus enum mipi_tx_hs_tp_sel { 219*98521f4dSAnitha Chrisanthus MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0 = 0, 220*98521f4dSAnitha Chrisanthus MIPI_TX_HS_TP_WHOLE_FRAME_COLOR1, 221*98521f4dSAnitha Chrisanthus MIPI_TX_HS_TP_V_STRIPES, 222*98521f4dSAnitha Chrisanthus MIPI_TX_HS_TP_H_STRIPES, 223*98521f4dSAnitha Chrisanthus }; 224*98521f4dSAnitha Chrisanthus 225*98521f4dSAnitha Chrisanthus enum dphy_mode { 226*98521f4dSAnitha Chrisanthus MIPI_DPHY_SLAVE = 0, 227*98521f4dSAnitha Chrisanthus MIPI_DPHY_MASTER 228*98521f4dSAnitha Chrisanthus }; 229*98521f4dSAnitha Chrisanthus 230*98521f4dSAnitha Chrisanthus enum dphy_tx_fsm { 231*98521f4dSAnitha Chrisanthus DPHY_TX_POWERDWN = 0, 232*98521f4dSAnitha Chrisanthus DPHY_TX_BGPON, 233*98521f4dSAnitha Chrisanthus DPHY_TX_TERMCAL, 234*98521f4dSAnitha Chrisanthus DPHY_TX_TERMCALUP, 235*98521f4dSAnitha Chrisanthus DPHY_TX_OFFSETCAL, 236*98521f4dSAnitha Chrisanthus DPHY_TX_LOCK, 237*98521f4dSAnitha Chrisanthus DPHY_TX_SRCAL, 238*98521f4dSAnitha Chrisanthus DPHY_TX_IDLE, 239*98521f4dSAnitha Chrisanthus DPHY_TX_ULP, 240*98521f4dSAnitha Chrisanthus DPHY_TX_LANESTART, 241*98521f4dSAnitha Chrisanthus DPHY_TX_CLKALIGN, 242*98521f4dSAnitha Chrisanthus DPHY_TX_DDLTUNNING, 243*98521f4dSAnitha Chrisanthus DPHY_TX_ULP_FORCE_PLL, 244*98521f4dSAnitha Chrisanthus DPHY_TX_LOCK_LOSS 245*98521f4dSAnitha Chrisanthus }; 246*98521f4dSAnitha Chrisanthus 247*98521f4dSAnitha Chrisanthus struct mipi_data_type_params { 248*98521f4dSAnitha Chrisanthus u8 size_constraint_pixels; 249*98521f4dSAnitha Chrisanthus u8 size_constraint_bytes; 250*98521f4dSAnitha Chrisanthus u8 pixels_per_pclk; 251*98521f4dSAnitha Chrisanthus u8 bits_per_pclk; 252*98521f4dSAnitha Chrisanthus }; 253*98521f4dSAnitha Chrisanthus 254*98521f4dSAnitha Chrisanthus struct mipi_tx_dsi_cfg { 255*98521f4dSAnitha Chrisanthus u8 hfp_blank_en; /* Horizontal front porch blanking enable */ 256*98521f4dSAnitha Chrisanthus u8 eotp_en; /* End of transmission packet enable */ 257*98521f4dSAnitha Chrisanthus /* Last vertical front porch blanking mode */ 258*98521f4dSAnitha Chrisanthus u8 lpm_last_vfp_line; 259*98521f4dSAnitha Chrisanthus /* First vertical sync active blanking mode */ 260*98521f4dSAnitha Chrisanthus u8 lpm_first_vsa_line; 261*98521f4dSAnitha Chrisanthus u8 sync_pulse_eventn; /* Sync type */ 262*98521f4dSAnitha Chrisanthus u8 hfp_blanking; /* Horizontal front porch blanking mode */ 263*98521f4dSAnitha Chrisanthus u8 hbp_blanking; /* Horizontal back porch blanking mode */ 264*98521f4dSAnitha Chrisanthus u8 hsa_blanking; /* Horizontal sync active blanking mode */ 265*98521f4dSAnitha Chrisanthus u8 v_blanking; /* Vertical timing blanking mode */ 266*98521f4dSAnitha Chrisanthus }; 267*98521f4dSAnitha Chrisanthus 268*98521f4dSAnitha Chrisanthus struct mipi_tx_frame_section_cfg { 269*98521f4dSAnitha Chrisanthus u32 dma_v_stride; 270*98521f4dSAnitha Chrisanthus u16 dma_v_scale_cfg; 271*98521f4dSAnitha Chrisanthus u16 width_pixels; 272*98521f4dSAnitha Chrisanthus u16 height_lines; 273*98521f4dSAnitha Chrisanthus u8 dma_packed; 274*98521f4dSAnitha Chrisanthus u8 bpp; 275*98521f4dSAnitha Chrisanthus u8 bpp_unpacked; 276*98521f4dSAnitha Chrisanthus u8 dma_h_stride; 277*98521f4dSAnitha Chrisanthus u8 data_type; 278*98521f4dSAnitha Chrisanthus u8 data_mode; 279*98521f4dSAnitha Chrisanthus u8 dma_flip_rotate_sel; 280*98521f4dSAnitha Chrisanthus }; 281*98521f4dSAnitha Chrisanthus 282*98521f4dSAnitha Chrisanthus struct mipi_tx_frame_timing_cfg { 283*98521f4dSAnitha Chrisanthus u32 bpp; 284*98521f4dSAnitha Chrisanthus u32 lane_rate_mbps; 285*98521f4dSAnitha Chrisanthus u32 hsync_width; 286*98521f4dSAnitha Chrisanthus u32 h_backporch; 287*98521f4dSAnitha Chrisanthus u32 h_frontporch; 288*98521f4dSAnitha Chrisanthus u32 h_active; 289*98521f4dSAnitha Chrisanthus u16 vsync_width; 290*98521f4dSAnitha Chrisanthus u16 v_backporch; 291*98521f4dSAnitha Chrisanthus u16 v_frontporch; 292*98521f4dSAnitha Chrisanthus u16 v_active; 293*98521f4dSAnitha Chrisanthus u8 active_lanes; 294*98521f4dSAnitha Chrisanthus }; 295*98521f4dSAnitha Chrisanthus 296*98521f4dSAnitha Chrisanthus struct mipi_tx_frame_sect_phcfg { 297*98521f4dSAnitha Chrisanthus u32 wc; 298*98521f4dSAnitha Chrisanthus enum mipi_data_mode data_mode; 299*98521f4dSAnitha Chrisanthus enum mipi_dsi_data_type data_type; 300*98521f4dSAnitha Chrisanthus u8 vchannel; 301*98521f4dSAnitha Chrisanthus u8 dma_packed; 302*98521f4dSAnitha Chrisanthus }; 303*98521f4dSAnitha Chrisanthus 304*98521f4dSAnitha Chrisanthus struct mipi_tx_frame_cfg { 305*98521f4dSAnitha Chrisanthus struct mipi_tx_frame_section_cfg *sections[MIPI_TX_FRAME_GEN_SECTIONS]; 306*98521f4dSAnitha Chrisanthus u32 hsync_width; /* in pixels */ 307*98521f4dSAnitha Chrisanthus u32 h_backporch; /* in pixels */ 308*98521f4dSAnitha Chrisanthus u32 h_frontporch; /* in pixels */ 309*98521f4dSAnitha Chrisanthus u16 vsync_width; /* in lines */ 310*98521f4dSAnitha Chrisanthus u16 v_backporch; /* in lines */ 311*98521f4dSAnitha Chrisanthus u16 v_frontporch; /* in lines */ 312*98521f4dSAnitha Chrisanthus }; 313*98521f4dSAnitha Chrisanthus 314*98521f4dSAnitha Chrisanthus struct mipi_tx_ctrl_cfg { 315*98521f4dSAnitha Chrisanthus struct mipi_tx_frame_cfg *frames[MIPI_TX_FRAME_GEN]; 316*98521f4dSAnitha Chrisanthus const struct mipi_tx_dsi_cfg *tx_dsi_cfg; 317*98521f4dSAnitha Chrisanthus u8 line_sync_pkt_en; 318*98521f4dSAnitha Chrisanthus u8 line_counter_active; 319*98521f4dSAnitha Chrisanthus u8 frame_counter_active; 320*98521f4dSAnitha Chrisanthus u8 tx_hsclkkidle_cnt; 321*98521f4dSAnitha Chrisanthus u8 tx_hsexit_cnt; 322*98521f4dSAnitha Chrisanthus u8 tx_crc_en; 323*98521f4dSAnitha Chrisanthus u8 tx_hact_wait_stop; 324*98521f4dSAnitha Chrisanthus u8 tx_always_use_hact; 325*98521f4dSAnitha Chrisanthus u8 tx_wait_trig; 326*98521f4dSAnitha Chrisanthus u8 tx_wait_all_sect; 327*98521f4dSAnitha Chrisanthus }; 328*98521f4dSAnitha Chrisanthus 329*98521f4dSAnitha Chrisanthus /* configuration structure for MIPI control */ 330*98521f4dSAnitha Chrisanthus struct mipi_ctrl_cfg { 331*98521f4dSAnitha Chrisanthus u8 active_lanes; /* # active lanes per controller 2/4 */ 332*98521f4dSAnitha Chrisanthus u32 lane_rate_mbps; /* MBPS */ 333*98521f4dSAnitha Chrisanthus u32 ref_clk_khz; 334*98521f4dSAnitha Chrisanthus u32 cfg_clk_khz; 335*98521f4dSAnitha Chrisanthus struct mipi_tx_ctrl_cfg tx_ctrl_cfg; 336*98521f4dSAnitha Chrisanthus }; 337*98521f4dSAnitha Chrisanthus 338*98521f4dSAnitha Chrisanthus static inline void kmb_write_mipi(struct kmb_dsi *kmb_dsi, 339*98521f4dSAnitha Chrisanthus unsigned int reg, u32 value) 340*98521f4dSAnitha Chrisanthus { 341*98521f4dSAnitha Chrisanthus writel(value, (kmb_dsi->mipi_mmio + reg)); 342*98521f4dSAnitha Chrisanthus } 343*98521f4dSAnitha Chrisanthus 344*98521f4dSAnitha Chrisanthus static inline u32 kmb_read_mipi(struct kmb_dsi *kmb_dsi, unsigned int reg) 345*98521f4dSAnitha Chrisanthus { 346*98521f4dSAnitha Chrisanthus return readl(kmb_dsi->mipi_mmio + reg); 347*98521f4dSAnitha Chrisanthus } 348*98521f4dSAnitha Chrisanthus 349*98521f4dSAnitha Chrisanthus static inline void kmb_write_bits_mipi(struct kmb_dsi *kmb_dsi, 350*98521f4dSAnitha Chrisanthus unsigned int reg, u32 offset, 351*98521f4dSAnitha Chrisanthus u32 num_bits, u32 value) 352*98521f4dSAnitha Chrisanthus { 353*98521f4dSAnitha Chrisanthus u32 reg_val = kmb_read_mipi(kmb_dsi, reg); 354*98521f4dSAnitha Chrisanthus u32 mask = (1 << num_bits) - 1; 355*98521f4dSAnitha Chrisanthus 356*98521f4dSAnitha Chrisanthus value &= mask; 357*98521f4dSAnitha Chrisanthus mask <<= offset; 358*98521f4dSAnitha Chrisanthus reg_val &= (~mask); 359*98521f4dSAnitha Chrisanthus reg_val |= (value << offset); 360*98521f4dSAnitha Chrisanthus kmb_write_mipi(kmb_dsi, reg, reg_val); 361*98521f4dSAnitha Chrisanthus } 362*98521f4dSAnitha Chrisanthus 363*98521f4dSAnitha Chrisanthus static inline void kmb_set_bit_mipi(struct kmb_dsi *kmb_dsi, 364*98521f4dSAnitha Chrisanthus unsigned int reg, u32 offset) 365*98521f4dSAnitha Chrisanthus { 366*98521f4dSAnitha Chrisanthus u32 reg_val = kmb_read_mipi(kmb_dsi, reg); 367*98521f4dSAnitha Chrisanthus 368*98521f4dSAnitha Chrisanthus kmb_write_mipi(kmb_dsi, reg, reg_val | (1 << offset)); 369*98521f4dSAnitha Chrisanthus } 370*98521f4dSAnitha Chrisanthus 371*98521f4dSAnitha Chrisanthus static inline void kmb_clr_bit_mipi(struct kmb_dsi *kmb_dsi, 372*98521f4dSAnitha Chrisanthus unsigned int reg, u32 offset) 373*98521f4dSAnitha Chrisanthus { 374*98521f4dSAnitha Chrisanthus u32 reg_val = kmb_read_mipi(kmb_dsi, reg); 375*98521f4dSAnitha Chrisanthus 376*98521f4dSAnitha Chrisanthus kmb_write_mipi(kmb_dsi, reg, reg_val & (~(1 << offset))); 377*98521f4dSAnitha Chrisanthus } 378*98521f4dSAnitha Chrisanthus 379*98521f4dSAnitha Chrisanthus int kmb_dsi_host_bridge_init(struct device *dev); 380*98521f4dSAnitha Chrisanthus struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev); 381*98521f4dSAnitha Chrisanthus void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi); 382*98521f4dSAnitha Chrisanthus int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode, 383*98521f4dSAnitha Chrisanthus int sys_clk_mhz); 384*98521f4dSAnitha Chrisanthus int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi); 385*98521f4dSAnitha Chrisanthus int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi); 386*98521f4dSAnitha Chrisanthus int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi); 387*98521f4dSAnitha Chrisanthus #endif /* __KMB_DSI_H__ */ 388