1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/bitfield.h> 10 #include <linux/component.h> 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/regmap.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_bridge_connector.h> 26 #include <drm/drm_color_mgmt.h> 27 #include <drm/drm_crtc.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_damage_helper.h> 30 #include <drm/drm_drv.h> 31 #include <drm/drm_encoder.h> 32 #include <drm/drm_gem_cma_helper.h> 33 #include <drm/drm_fb_cma_helper.h> 34 #include <drm/drm_fb_helper.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_gem_atomic_helper.h> 37 #include <drm/drm_gem_framebuffer_helper.h> 38 #include <drm/drm_managed.h> 39 #include <drm/drm_of.h> 40 #include <drm/drm_panel.h> 41 #include <drm/drm_plane.h> 42 #include <drm/drm_plane_helper.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_vblank.h> 45 46 #define HWDESC_PALETTE 2 47 48 struct ingenic_dma_hwdesc { 49 u32 next; 50 u32 addr; 51 u32 id; 52 u32 cmd; 53 /* extended hw descriptor for jz4780 */ 54 u32 offsize; 55 u32 pagewidth; 56 u32 cpos; 57 u32 dessize; 58 } __aligned(16); 59 60 struct ingenic_dma_hwdescs { 61 struct ingenic_dma_hwdesc hwdesc[3]; 62 u16 palette[256] __aligned(16); 63 }; 64 65 struct jz_soc_info { 66 bool needs_dev_clk; 67 bool has_osd; 68 bool map_noncoherent; 69 bool use_extended_hwdesc; 70 unsigned int max_width, max_height; 71 const u32 *formats_f0, *formats_f1; 72 unsigned int num_formats_f0, num_formats_f1; 73 }; 74 75 struct ingenic_drm_private_state { 76 struct drm_private_state base; 77 bool use_palette; 78 }; 79 80 struct ingenic_drm { 81 struct drm_device drm; 82 /* 83 * f1 (aka. foreground1) is our primary plane, on top of which 84 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 85 * hardware and cannot be changed. 86 */ 87 struct drm_plane f0, f1, *ipu_plane; 88 struct drm_crtc crtc; 89 90 struct device *dev; 91 struct regmap *map; 92 struct clk *lcd_clk, *pix_clk; 93 const struct jz_soc_info *soc_info; 94 95 struct ingenic_dma_hwdescs *dma_hwdescs; 96 dma_addr_t dma_hwdescs_phys; 97 98 bool panel_is_sharp; 99 bool no_vblank; 100 101 /* 102 * clk_mutex is used to synchronize the pixel clock rate update with 103 * the VBLANK. When the pixel clock's parent clock needs to be updated, 104 * clock_nb's notifier function will lock the mutex, then wait until the 105 * next VBLANK. At that point, the parent clock's rate can be updated, 106 * and the mutex is then unlocked. If an atomic commit happens in the 107 * meantime, it will lock on the mutex, effectively waiting until the 108 * clock update process finishes. Finally, the pixel clock's rate will 109 * be recomputed when the mutex has been released, in the pending atomic 110 * commit, or a future one. 111 */ 112 struct mutex clk_mutex; 113 bool update_clk_rate; 114 struct notifier_block clock_nb; 115 116 struct drm_private_obj private_obj; 117 }; 118 119 struct ingenic_drm_bridge { 120 struct drm_encoder encoder; 121 struct drm_bridge bridge, *next_bridge; 122 123 struct drm_bus_cfg bus_cfg; 124 }; 125 126 static inline struct ingenic_drm_bridge * 127 to_ingenic_drm_bridge(struct drm_encoder *encoder) 128 { 129 return container_of(encoder, struct ingenic_drm_bridge, encoder); 130 } 131 132 static inline struct ingenic_drm_private_state * 133 to_ingenic_drm_priv_state(struct drm_private_state *state) 134 { 135 return container_of(state, struct ingenic_drm_private_state, base); 136 } 137 138 static struct ingenic_drm_private_state * 139 ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 140 { 141 struct drm_private_state *priv_state; 142 143 priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj); 144 if (IS_ERR(priv_state)) 145 return ERR_CAST(priv_state); 146 147 return to_ingenic_drm_priv_state(priv_state); 148 } 149 150 static struct ingenic_drm_private_state * 151 ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 152 { 153 struct drm_private_state *priv_state; 154 155 priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj); 156 if (!priv_state) 157 return NULL; 158 159 return to_ingenic_drm_priv_state(priv_state); 160 } 161 162 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case JZ_REG_LCD_IID: 166 case JZ_REG_LCD_SA0: 167 case JZ_REG_LCD_FID0: 168 case JZ_REG_LCD_CMD0: 169 case JZ_REG_LCD_SA1: 170 case JZ_REG_LCD_FID1: 171 case JZ_REG_LCD_CMD1: 172 return false; 173 default: 174 return true; 175 } 176 } 177 178 static const struct regmap_config ingenic_drm_regmap_config = { 179 .reg_bits = 32, 180 .val_bits = 32, 181 .reg_stride = 4, 182 183 .writeable_reg = ingenic_drm_writeable_reg, 184 }; 185 186 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 187 { 188 return container_of(drm, struct ingenic_drm, drm); 189 } 190 191 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 192 { 193 return container_of(crtc, struct ingenic_drm, crtc); 194 } 195 196 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 197 { 198 return container_of(nb, struct ingenic_drm, clock_nb); 199 } 200 201 static inline dma_addr_t dma_hwdesc_addr(const struct ingenic_drm *priv, 202 unsigned int idx) 203 { 204 u32 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc[idx]); 205 206 return priv->dma_hwdescs_phys + offset; 207 } 208 209 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 210 unsigned long action, 211 void *data) 212 { 213 struct ingenic_drm *priv = drm_nb_get_priv(nb); 214 215 switch (action) { 216 case PRE_RATE_CHANGE: 217 mutex_lock(&priv->clk_mutex); 218 priv->update_clk_rate = true; 219 drm_crtc_wait_one_vblank(&priv->crtc); 220 return NOTIFY_OK; 221 default: 222 mutex_unlock(&priv->clk_mutex); 223 return NOTIFY_OK; 224 } 225 } 226 227 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 228 struct drm_atomic_state *state) 229 { 230 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 231 struct ingenic_drm_private_state *priv_state; 232 unsigned int next_id; 233 234 priv_state = ingenic_drm_get_priv_state(priv, state); 235 if (WARN_ON(IS_ERR(priv_state))) 236 return; 237 238 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 239 240 /* Set addresses of our DMA descriptor chains */ 241 next_id = priv_state->use_palette ? HWDESC_PALETTE : 0; 242 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id)); 243 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); 244 245 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 246 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 247 JZ_LCD_CTRL_ENABLE); 248 249 drm_crtc_vblank_on(crtc); 250 } 251 252 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 253 struct drm_atomic_state *state) 254 { 255 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 256 unsigned int var; 257 258 drm_crtc_vblank_off(crtc); 259 260 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 261 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 262 263 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 264 var & JZ_LCD_STATE_DISABLED, 265 1000, 0); 266 } 267 268 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 269 struct drm_display_mode *mode) 270 { 271 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 272 273 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start; 274 vds = mode->crtc_vtotal - mode->crtc_vsync_start; 275 vde = vds + mode->crtc_vdisplay; 276 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay; 277 278 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start; 279 hds = mode->crtc_htotal - mode->crtc_hsync_start; 280 hde = hds + mode->crtc_hdisplay; 281 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay; 282 283 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 284 0 << JZ_LCD_VSYNC_VPS_OFFSET | 285 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 286 287 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 288 0 << JZ_LCD_HSYNC_HPS_OFFSET | 289 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 290 291 regmap_write(priv->map, JZ_REG_LCD_VAT, 292 ht << JZ_LCD_VAT_HT_OFFSET | 293 vt << JZ_LCD_VAT_VT_OFFSET); 294 295 regmap_write(priv->map, JZ_REG_LCD_DAH, 296 hds << JZ_LCD_DAH_HDS_OFFSET | 297 hde << JZ_LCD_DAH_HDE_OFFSET); 298 regmap_write(priv->map, JZ_REG_LCD_DAV, 299 vds << JZ_LCD_DAV_VDS_OFFSET | 300 vde << JZ_LCD_DAV_VDE_OFFSET); 301 302 if (priv->panel_is_sharp) { 303 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 304 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 305 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 306 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 307 } 308 309 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 310 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 311 312 /* 313 * IPU restart - specify how much time the LCDC will wait before 314 * transferring a new frame from the IPU. The value is the one 315 * suggested in the programming manual. 316 */ 317 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 318 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 319 } 320 321 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 322 struct drm_atomic_state *state) 323 { 324 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 325 crtc); 326 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 327 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 328 329 if (crtc_state->gamma_lut && 330 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 331 dev_dbg(priv->dev, "Invalid palette size\n"); 332 return -EINVAL; 333 } 334 335 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 336 f1_state = drm_atomic_get_plane_state(crtc_state->state, 337 &priv->f1); 338 if (IS_ERR(f1_state)) 339 return PTR_ERR(f1_state); 340 341 f0_state = drm_atomic_get_plane_state(crtc_state->state, 342 &priv->f0); 343 if (IS_ERR(f0_state)) 344 return PTR_ERR(f0_state); 345 346 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 347 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 348 priv->ipu_plane); 349 if (IS_ERR(ipu_state)) 350 return PTR_ERR(ipu_state); 351 352 /* IPU and F1 planes cannot be enabled at the same time. */ 353 if (f1_state->fb && ipu_state->fb) { 354 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 355 return -EINVAL; 356 } 357 } 358 359 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 360 priv->no_vblank = !f1_state->fb && !f0_state->fb && 361 !(ipu_state && ipu_state->fb); 362 } 363 364 return 0; 365 } 366 367 static enum drm_mode_status 368 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 369 { 370 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 371 long rate; 372 373 if (mode->hdisplay > priv->soc_info->max_width) 374 return MODE_BAD_HVALUE; 375 if (mode->vdisplay > priv->soc_info->max_height) 376 return MODE_BAD_VVALUE; 377 378 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 379 if (rate < 0) 380 return MODE_CLOCK_RANGE; 381 382 return MODE_OK; 383 } 384 385 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 386 struct drm_atomic_state *state) 387 { 388 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 389 crtc); 390 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 391 u32 ctrl = 0; 392 393 if (priv->soc_info->has_osd && 394 drm_atomic_crtc_needs_modeset(crtc_state)) { 395 /* 396 * If IPU plane is enabled, enable IPU as source for the F1 397 * plane; otherwise use regular DMA. 398 */ 399 if (priv->ipu_plane && priv->ipu_plane->state->fb) 400 ctrl |= JZ_LCD_OSDCTRL_IPU; 401 402 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 403 JZ_LCD_OSDCTRL_IPU, ctrl); 404 } 405 } 406 407 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 408 struct drm_atomic_state *state) 409 { 410 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 411 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 412 crtc); 413 struct drm_pending_vblank_event *event = crtc_state->event; 414 415 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 416 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode); 417 priv->update_clk_rate = true; 418 } 419 420 if (priv->update_clk_rate) { 421 mutex_lock(&priv->clk_mutex); 422 clk_set_rate(priv->pix_clk, 423 crtc_state->adjusted_mode.crtc_clock * 1000); 424 priv->update_clk_rate = false; 425 mutex_unlock(&priv->clk_mutex); 426 } 427 428 if (event) { 429 crtc_state->event = NULL; 430 431 spin_lock_irq(&crtc->dev->event_lock); 432 if (drm_crtc_vblank_get(crtc) == 0) 433 drm_crtc_arm_vblank_event(crtc, event); 434 else 435 drm_crtc_send_vblank_event(crtc, event); 436 spin_unlock_irq(&crtc->dev->event_lock); 437 } 438 } 439 440 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 441 struct drm_atomic_state *state) 442 { 443 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 444 plane); 445 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 446 plane); 447 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 448 struct ingenic_drm_private_state *priv_state; 449 struct drm_crtc_state *crtc_state; 450 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 451 int ret; 452 453 if (!crtc) 454 return 0; 455 456 if (plane == &priv->f0) 457 return -EINVAL; 458 459 crtc_state = drm_atomic_get_existing_crtc_state(state, 460 crtc); 461 if (WARN_ON(!crtc_state)) 462 return -EINVAL; 463 464 priv_state = ingenic_drm_get_priv_state(priv, state); 465 if (IS_ERR(priv_state)) 466 return PTR_ERR(priv_state); 467 468 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 469 DRM_PLANE_HELPER_NO_SCALING, 470 DRM_PLANE_HELPER_NO_SCALING, 471 priv->soc_info->has_osd, 472 true); 473 if (ret) 474 return ret; 475 476 /* 477 * If OSD is not available, check that the width/height match. 478 * Note that state->src_* are in 16.16 fixed-point format. 479 */ 480 if (!priv->soc_info->has_osd && 481 (new_plane_state->src_x != 0 || 482 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w || 483 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) 484 return -EINVAL; 485 486 priv_state->use_palette = new_plane_state->fb && 487 new_plane_state->fb->format->format == DRM_FORMAT_C8; 488 489 /* 490 * Require full modeset if enabling or disabling a plane, or changing 491 * its position, size or depth. 492 */ 493 if (priv->soc_info->has_osd && 494 (!old_plane_state->fb || !new_plane_state->fb || 495 old_plane_state->crtc_x != new_plane_state->crtc_x || 496 old_plane_state->crtc_y != new_plane_state->crtc_y || 497 old_plane_state->crtc_w != new_plane_state->crtc_w || 498 old_plane_state->crtc_h != new_plane_state->crtc_h || 499 old_plane_state->fb->format->format != new_plane_state->fb->format->format)) 500 crtc_state->mode_changed = true; 501 502 if (priv->soc_info->map_noncoherent) 503 drm_atomic_helper_check_plane_damage(state, new_plane_state); 504 505 return 0; 506 } 507 508 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 509 struct drm_plane *plane) 510 { 511 unsigned int en_bit; 512 513 if (priv->soc_info->has_osd) { 514 if (plane != &priv->f0) 515 en_bit = JZ_LCD_OSDC_F1EN; 516 else 517 en_bit = JZ_LCD_OSDC_F0EN; 518 519 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 520 } 521 } 522 523 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 524 { 525 struct ingenic_drm *priv = dev_get_drvdata(dev); 526 unsigned int en_bit; 527 528 if (priv->soc_info->has_osd) { 529 if (plane != &priv->f0) 530 en_bit = JZ_LCD_OSDC_F1EN; 531 else 532 en_bit = JZ_LCD_OSDC_F0EN; 533 534 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 535 } 536 } 537 538 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 539 struct drm_atomic_state *state) 540 { 541 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 542 543 ingenic_drm_plane_disable(priv->dev, plane); 544 } 545 546 void ingenic_drm_plane_config(struct device *dev, 547 struct drm_plane *plane, u32 fourcc) 548 { 549 struct ingenic_drm *priv = dev_get_drvdata(dev); 550 struct drm_plane_state *state = plane->state; 551 unsigned int xy_reg, size_reg; 552 unsigned int ctrl = 0; 553 554 ingenic_drm_plane_enable(priv, plane); 555 556 if (priv->soc_info->has_osd && plane != &priv->f0) { 557 switch (fourcc) { 558 case DRM_FORMAT_XRGB1555: 559 ctrl |= JZ_LCD_OSDCTRL_RGB555; 560 fallthrough; 561 case DRM_FORMAT_RGB565: 562 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 563 break; 564 case DRM_FORMAT_RGB888: 565 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 566 break; 567 case DRM_FORMAT_XRGB8888: 568 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 569 break; 570 case DRM_FORMAT_XRGB2101010: 571 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 572 break; 573 } 574 575 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 576 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 577 } else { 578 switch (fourcc) { 579 case DRM_FORMAT_C8: 580 ctrl |= JZ_LCD_CTRL_BPP_8; 581 break; 582 case DRM_FORMAT_XRGB1555: 583 ctrl |= JZ_LCD_CTRL_RGB555; 584 fallthrough; 585 case DRM_FORMAT_RGB565: 586 ctrl |= JZ_LCD_CTRL_BPP_15_16; 587 break; 588 case DRM_FORMAT_RGB888: 589 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 590 break; 591 case DRM_FORMAT_XRGB8888: 592 ctrl |= JZ_LCD_CTRL_BPP_18_24; 593 break; 594 case DRM_FORMAT_XRGB2101010: 595 ctrl |= JZ_LCD_CTRL_BPP_30; 596 break; 597 } 598 599 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 600 JZ_LCD_CTRL_BPP_MASK, ctrl); 601 } 602 603 if (priv->soc_info->has_osd) { 604 if (plane != &priv->f0) { 605 xy_reg = JZ_REG_LCD_XYP1; 606 size_reg = JZ_REG_LCD_SIZE1; 607 } else { 608 xy_reg = JZ_REG_LCD_XYP0; 609 size_reg = JZ_REG_LCD_SIZE0; 610 } 611 612 regmap_write(priv->map, xy_reg, 613 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 614 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 615 regmap_write(priv->map, size_reg, 616 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 617 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 618 } 619 } 620 621 bool ingenic_drm_map_noncoherent(const struct device *dev) 622 { 623 const struct ingenic_drm *priv = dev_get_drvdata(dev); 624 625 return priv->soc_info->map_noncoherent; 626 } 627 628 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 629 const struct drm_color_lut *lut) 630 { 631 unsigned int i; 632 633 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 634 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 635 | drm_color_lut_extract(lut[i].green, 6) << 5 636 | drm_color_lut_extract(lut[i].blue, 5); 637 638 priv->dma_hwdescs->palette[i] = color; 639 } 640 } 641 642 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 643 struct drm_atomic_state *state) 644 { 645 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 646 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); 647 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); 648 unsigned int width, height, cpp, next_id, plane_id; 649 struct ingenic_drm_private_state *priv_state; 650 struct drm_crtc_state *crtc_state; 651 struct ingenic_dma_hwdesc *hwdesc; 652 dma_addr_t addr; 653 u32 fourcc; 654 655 if (newstate && newstate->fb) { 656 if (priv->soc_info->map_noncoherent) 657 drm_fb_cma_sync_non_coherent(&priv->drm, oldstate, newstate); 658 659 crtc_state = newstate->crtc->state; 660 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0); 661 662 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0); 663 width = newstate->src_w >> 16; 664 height = newstate->src_h >> 16; 665 cpp = newstate->fb->format->cpp[0]; 666 667 priv_state = ingenic_drm_get_new_priv_state(priv, state); 668 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id; 669 670 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; 671 hwdesc->addr = addr; 672 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 673 hwdesc->next = dma_hwdesc_addr(priv, next_id); 674 675 if (priv->soc_info->use_extended_hwdesc) { 676 hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE; 677 678 /* Extended 8-byte descriptor */ 679 hwdesc->cpos = 0; 680 hwdesc->offsize = 0; 681 hwdesc->pagewidth = 0; 682 683 switch (newstate->fb->format->format) { 684 case DRM_FORMAT_XRGB1555: 685 hwdesc->cpos |= JZ_LCD_CPOS_RGB555; 686 fallthrough; 687 case DRM_FORMAT_RGB565: 688 hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16; 689 break; 690 case DRM_FORMAT_XRGB8888: 691 hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24; 692 break; 693 } 694 hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 << 695 JZ_LCD_CPOS_COEFFICIENT_OFFSET); 696 hwdesc->dessize = 697 (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) | 698 FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height - 1) | 699 FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width - 1); 700 } 701 702 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 703 fourcc = newstate->fb->format->format; 704 705 ingenic_drm_plane_config(priv->dev, plane, fourcc); 706 707 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 708 } 709 710 if (crtc_state->color_mgmt_changed) 711 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 712 } 713 } 714 715 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 716 struct drm_crtc_state *crtc_state, 717 struct drm_connector_state *conn_state) 718 { 719 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 720 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 721 struct ingenic_drm_bridge *bridge = to_ingenic_drm_bridge(encoder); 722 unsigned int cfg, rgbcfg = 0; 723 724 priv->panel_is_sharp = bridge->bus_cfg.flags & DRM_BUS_FLAG_SHARP_SIGNALS; 725 726 if (priv->panel_is_sharp) { 727 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 728 } else { 729 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 730 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 731 } 732 733 if (priv->soc_info->use_extended_hwdesc) 734 cfg |= JZ_LCD_CFG_DESCRIPTOR_8; 735 736 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 737 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 738 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 739 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 740 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_DE_LOW) 741 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 742 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 743 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 744 745 if (!priv->panel_is_sharp) { 746 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) { 747 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 748 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 749 else 750 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 751 } else { 752 switch (bridge->bus_cfg.format) { 753 case MEDIA_BUS_FMT_RGB565_1X16: 754 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 755 break; 756 case MEDIA_BUS_FMT_RGB666_1X18: 757 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 758 break; 759 case MEDIA_BUS_FMT_RGB888_1X24: 760 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 761 break; 762 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 763 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; 764 fallthrough; 765 case MEDIA_BUS_FMT_RGB888_3X8: 766 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 767 break; 768 default: 769 break; 770 } 771 } 772 } 773 774 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 775 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); 776 } 777 778 static int ingenic_drm_bridge_attach(struct drm_bridge *bridge, 779 enum drm_bridge_attach_flags flags) 780 { 781 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder); 782 783 return drm_bridge_attach(bridge->encoder, ib->next_bridge, 784 &ib->bridge, flags); 785 } 786 787 static int ingenic_drm_bridge_atomic_check(struct drm_bridge *bridge, 788 struct drm_bridge_state *bridge_state, 789 struct drm_crtc_state *crtc_state, 790 struct drm_connector_state *conn_state) 791 { 792 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 793 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder); 794 795 ib->bus_cfg = bridge_state->output_bus_cfg; 796 797 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 798 return 0; 799 800 switch (bridge_state->output_bus_cfg.format) { 801 case MEDIA_BUS_FMT_RGB888_3X8: 802 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 803 /* 804 * The LCD controller expects timing values in dot-clock ticks, 805 * which is 3x the timing values in pixels when using a 3x8-bit 806 * display; but it will count the display area size in pixels 807 * either way. Go figure. 808 */ 809 mode->crtc_clock = mode->clock * 3; 810 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2; 811 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2; 812 mode->crtc_hdisplay = mode->hdisplay; 813 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2; 814 return 0; 815 case MEDIA_BUS_FMT_RGB565_1X16: 816 case MEDIA_BUS_FMT_RGB666_1X18: 817 case MEDIA_BUS_FMT_RGB888_1X24: 818 return 0; 819 default: 820 return -EINVAL; 821 } 822 } 823 824 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 825 { 826 struct ingenic_drm *priv = drm_device_get_priv(arg); 827 unsigned int state; 828 829 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 830 831 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 832 JZ_LCD_STATE_EOF_IRQ, 0); 833 834 if (state & JZ_LCD_STATE_EOF_IRQ) 835 drm_crtc_handle_vblank(&priv->crtc); 836 837 return IRQ_HANDLED; 838 } 839 840 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 841 { 842 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 843 844 if (priv->no_vblank) 845 return -EINVAL; 846 847 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 848 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 849 850 return 0; 851 } 852 853 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 854 { 855 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 856 857 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 858 } 859 860 static struct drm_framebuffer * 861 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, 862 const struct drm_mode_fb_cmd2 *mode_cmd) 863 { 864 struct ingenic_drm *priv = drm_device_get_priv(drm); 865 866 if (priv->soc_info->map_noncoherent) 867 return drm_gem_fb_create_with_dirty(drm, file, mode_cmd); 868 869 return drm_gem_fb_create(drm, file, mode_cmd); 870 } 871 872 static struct drm_gem_object * 873 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size) 874 { 875 struct ingenic_drm *priv = drm_device_get_priv(drm); 876 struct drm_gem_cma_object *obj; 877 878 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 879 if (!obj) 880 return ERR_PTR(-ENOMEM); 881 882 obj->map_noncoherent = priv->soc_info->map_noncoherent; 883 884 return &obj->base; 885 } 886 887 static struct drm_private_state * 888 ingenic_drm_duplicate_state(struct drm_private_obj *obj) 889 { 890 struct ingenic_drm_private_state *state = to_ingenic_drm_priv_state(obj->state); 891 892 state = kmemdup(state, sizeof(*state), GFP_KERNEL); 893 if (!state) 894 return NULL; 895 896 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 897 898 return &state->base; 899 } 900 901 static void ingenic_drm_destroy_state(struct drm_private_obj *obj, 902 struct drm_private_state *state) 903 { 904 struct ingenic_drm_private_state *priv_state = to_ingenic_drm_priv_state(state); 905 906 kfree(priv_state); 907 } 908 909 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 910 911 static const struct drm_driver ingenic_drm_driver_data = { 912 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 913 .name = "ingenic-drm", 914 .desc = "DRM module for Ingenic SoCs", 915 .date = "20200716", 916 .major = 1, 917 .minor = 1, 918 .patchlevel = 0, 919 920 .fops = &ingenic_drm_fops, 921 .gem_create_object = ingenic_drm_gem_create_object, 922 DRM_GEM_CMA_DRIVER_OPS, 923 }; 924 925 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 926 .update_plane = drm_atomic_helper_update_plane, 927 .disable_plane = drm_atomic_helper_disable_plane, 928 .reset = drm_atomic_helper_plane_reset, 929 .destroy = drm_plane_cleanup, 930 931 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 932 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 933 }; 934 935 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 936 .set_config = drm_atomic_helper_set_config, 937 .page_flip = drm_atomic_helper_page_flip, 938 .reset = drm_atomic_helper_crtc_reset, 939 .destroy = drm_crtc_cleanup, 940 941 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 942 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 943 944 .enable_vblank = ingenic_drm_enable_vblank, 945 .disable_vblank = ingenic_drm_disable_vblank, 946 }; 947 948 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 949 .atomic_update = ingenic_drm_plane_atomic_update, 950 .atomic_check = ingenic_drm_plane_atomic_check, 951 .atomic_disable = ingenic_drm_plane_atomic_disable, 952 }; 953 954 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 955 .atomic_enable = ingenic_drm_crtc_atomic_enable, 956 .atomic_disable = ingenic_drm_crtc_atomic_disable, 957 .atomic_begin = ingenic_drm_crtc_atomic_begin, 958 .atomic_flush = ingenic_drm_crtc_atomic_flush, 959 .atomic_check = ingenic_drm_crtc_atomic_check, 960 .mode_valid = ingenic_drm_crtc_mode_valid, 961 }; 962 963 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 964 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 965 }; 966 967 static const struct drm_bridge_funcs ingenic_drm_bridge_funcs = { 968 .attach = ingenic_drm_bridge_attach, 969 .atomic_check = ingenic_drm_bridge_atomic_check, 970 .atomic_reset = drm_atomic_helper_bridge_reset, 971 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 972 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 973 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, 974 }; 975 976 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 977 .fb_create = ingenic_drm_gem_fb_create, 978 .output_poll_changed = drm_fb_helper_output_poll_changed, 979 .atomic_check = drm_atomic_helper_check, 980 .atomic_commit = drm_atomic_helper_commit, 981 }; 982 983 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 984 .atomic_commit_tail = drm_atomic_helper_commit_tail, 985 }; 986 987 static const struct drm_private_state_funcs ingenic_drm_private_state_funcs = { 988 .atomic_duplicate_state = ingenic_drm_duplicate_state, 989 .atomic_destroy_state = ingenic_drm_destroy_state, 990 }; 991 992 static void ingenic_drm_unbind_all(void *d) 993 { 994 struct ingenic_drm *priv = d; 995 996 component_unbind_all(priv->dev, &priv->drm); 997 } 998 999 static void __maybe_unused ingenic_drm_release_rmem(void *d) 1000 { 1001 of_reserved_mem_device_release(d); 1002 } 1003 1004 static void ingenic_drm_configure_hwdesc(struct ingenic_drm *priv, 1005 unsigned int hwdesc, 1006 unsigned int next_hwdesc, u32 id) 1007 { 1008 struct ingenic_dma_hwdesc *desc = &priv->dma_hwdescs->hwdesc[hwdesc]; 1009 1010 desc->next = dma_hwdesc_addr(priv, next_hwdesc); 1011 desc->id = id; 1012 } 1013 1014 static void ingenic_drm_configure_hwdesc_palette(struct ingenic_drm *priv) 1015 { 1016 struct ingenic_dma_hwdesc *desc; 1017 1018 ingenic_drm_configure_hwdesc(priv, HWDESC_PALETTE, 0, 0xc0); 1019 1020 desc = &priv->dma_hwdescs->hwdesc[HWDESC_PALETTE]; 1021 desc->addr = priv->dma_hwdescs_phys 1022 + offsetof(struct ingenic_dma_hwdescs, palette); 1023 desc->cmd = JZ_LCD_CMD_ENABLE_PAL 1024 | (sizeof(priv->dma_hwdescs->palette) / 4); 1025 } 1026 1027 static void ingenic_drm_configure_hwdesc_plane(struct ingenic_drm *priv, 1028 unsigned int plane) 1029 { 1030 ingenic_drm_configure_hwdesc(priv, plane, plane, 0xf0 | plane); 1031 } 1032 1033 static void ingenic_drm_atomic_private_obj_fini(struct drm_device *drm, void *private_obj) 1034 { 1035 drm_atomic_private_obj_fini(private_obj); 1036 } 1037 1038 static int ingenic_drm_bind(struct device *dev, bool has_components) 1039 { 1040 struct platform_device *pdev = to_platform_device(dev); 1041 struct ingenic_drm_private_state *private_state; 1042 const struct jz_soc_info *soc_info; 1043 struct ingenic_drm *priv; 1044 struct clk *parent_clk; 1045 struct drm_plane *primary; 1046 struct drm_bridge *bridge; 1047 struct drm_panel *panel; 1048 struct drm_connector *connector; 1049 struct drm_encoder *encoder; 1050 struct ingenic_drm_bridge *ib; 1051 struct drm_device *drm; 1052 void __iomem *base; 1053 struct resource *res; 1054 struct regmap_config regmap_config; 1055 long parent_rate; 1056 unsigned int i, clone_mask = 0; 1057 int ret, irq; 1058 1059 soc_info = of_device_get_match_data(dev); 1060 if (!soc_info) { 1061 dev_err(dev, "Missing platform data\n"); 1062 return -EINVAL; 1063 } 1064 1065 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 1066 ret = of_reserved_mem_device_init(dev); 1067 1068 if (ret && ret != -ENODEV) 1069 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 1070 1071 if (!ret) { 1072 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 1073 if (ret) 1074 return ret; 1075 } 1076 } 1077 1078 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 1079 struct ingenic_drm, drm); 1080 if (IS_ERR(priv)) 1081 return PTR_ERR(priv); 1082 1083 priv->soc_info = soc_info; 1084 priv->dev = dev; 1085 drm = &priv->drm; 1086 1087 platform_set_drvdata(pdev, priv); 1088 1089 ret = drmm_mode_config_init(drm); 1090 if (ret) 1091 return ret; 1092 1093 drm->mode_config.min_width = 0; 1094 drm->mode_config.min_height = 0; 1095 drm->mode_config.max_width = soc_info->max_width; 1096 drm->mode_config.max_height = 4095; 1097 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 1098 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 1099 1100 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1101 if (IS_ERR(base)) { 1102 dev_err(dev, "Failed to get memory resource\n"); 1103 return PTR_ERR(base); 1104 } 1105 1106 regmap_config = ingenic_drm_regmap_config; 1107 regmap_config.max_register = res->end - res->start; 1108 priv->map = devm_regmap_init_mmio(dev, base, 1109 ®map_config); 1110 if (IS_ERR(priv->map)) { 1111 dev_err(dev, "Failed to create regmap\n"); 1112 return PTR_ERR(priv->map); 1113 } 1114 1115 irq = platform_get_irq(pdev, 0); 1116 if (irq < 0) 1117 return irq; 1118 1119 if (soc_info->needs_dev_clk) { 1120 priv->lcd_clk = devm_clk_get(dev, "lcd"); 1121 if (IS_ERR(priv->lcd_clk)) { 1122 dev_err(dev, "Failed to get lcd clock\n"); 1123 return PTR_ERR(priv->lcd_clk); 1124 } 1125 } 1126 1127 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 1128 if (IS_ERR(priv->pix_clk)) { 1129 dev_err(dev, "Failed to get pixel clock\n"); 1130 return PTR_ERR(priv->pix_clk); 1131 } 1132 1133 priv->dma_hwdescs = dmam_alloc_coherent(dev, 1134 sizeof(*priv->dma_hwdescs), 1135 &priv->dma_hwdescs_phys, 1136 GFP_KERNEL); 1137 if (!priv->dma_hwdescs) 1138 return -ENOMEM; 1139 1140 /* Configure DMA hwdesc for foreground0 plane */ 1141 ingenic_drm_configure_hwdesc_plane(priv, 0); 1142 1143 /* Configure DMA hwdesc for foreground1 plane */ 1144 ingenic_drm_configure_hwdesc_plane(priv, 1); 1145 1146 /* Configure DMA hwdesc for palette */ 1147 ingenic_drm_configure_hwdesc_palette(priv); 1148 1149 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0; 1150 1151 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs); 1152 1153 ret = drm_universal_plane_init(drm, primary, 1, 1154 &ingenic_drm_primary_plane_funcs, 1155 priv->soc_info->formats_f1, 1156 priv->soc_info->num_formats_f1, 1157 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1158 if (ret) { 1159 dev_err(dev, "Failed to register plane: %i\n", ret); 1160 return ret; 1161 } 1162 1163 if (soc_info->map_noncoherent) 1164 drm_plane_enable_fb_damage_clips(&priv->f1); 1165 1166 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 1167 1168 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary, 1169 NULL, &ingenic_drm_crtc_funcs, NULL); 1170 if (ret) { 1171 dev_err(dev, "Failed to init CRTC: %i\n", ret); 1172 return ret; 1173 } 1174 1175 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 1176 ARRAY_SIZE(priv->dma_hwdescs->palette)); 1177 1178 if (soc_info->has_osd) { 1179 drm_plane_helper_add(&priv->f0, 1180 &ingenic_drm_plane_helper_funcs); 1181 1182 ret = drm_universal_plane_init(drm, &priv->f0, 1, 1183 &ingenic_drm_primary_plane_funcs, 1184 priv->soc_info->formats_f0, 1185 priv->soc_info->num_formats_f0, 1186 NULL, DRM_PLANE_TYPE_OVERLAY, 1187 NULL); 1188 if (ret) { 1189 dev_err(dev, "Failed to register overlay plane: %i\n", 1190 ret); 1191 return ret; 1192 } 1193 1194 if (soc_info->map_noncoherent) 1195 drm_plane_enable_fb_damage_clips(&priv->f0); 1196 1197 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 1198 ret = component_bind_all(dev, drm); 1199 if (ret) { 1200 if (ret != -EPROBE_DEFER) 1201 dev_err(dev, "Failed to bind components: %i\n", ret); 1202 return ret; 1203 } 1204 1205 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 1206 if (ret) 1207 return ret; 1208 1209 priv->ipu_plane = drm_plane_from_index(drm, 2); 1210 if (!priv->ipu_plane) { 1211 dev_err(dev, "Failed to retrieve IPU plane\n"); 1212 return -EINVAL; 1213 } 1214 } 1215 } 1216 1217 for (i = 0; ; i++) { 1218 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 1219 if (ret) { 1220 if (ret == -ENODEV) 1221 break; /* we're done */ 1222 if (ret != -EPROBE_DEFER) 1223 dev_err(dev, "Failed to get bridge handle\n"); 1224 return ret; 1225 } 1226 1227 if (panel) 1228 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 1229 DRM_MODE_CONNECTOR_DPI); 1230 1231 ib = drmm_encoder_alloc(drm, struct ingenic_drm_bridge, encoder, 1232 NULL, DRM_MODE_ENCODER_DPI, NULL); 1233 if (IS_ERR(ib)) { 1234 ret = PTR_ERR(ib); 1235 dev_err(dev, "Failed to init encoder: %d\n", ret); 1236 return ret; 1237 } 1238 1239 encoder = &ib->encoder; 1240 encoder->possible_crtcs = drm_crtc_mask(&priv->crtc); 1241 1242 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1243 1244 ib->bridge.funcs = &ingenic_drm_bridge_funcs; 1245 ib->next_bridge = bridge; 1246 1247 ret = drm_bridge_attach(encoder, &ib->bridge, NULL, 1248 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1249 if (ret) { 1250 dev_err(dev, "Unable to attach bridge\n"); 1251 return ret; 1252 } 1253 1254 connector = drm_bridge_connector_init(drm, encoder); 1255 if (IS_ERR(connector)) { 1256 dev_err(dev, "Unable to init connector\n"); 1257 return PTR_ERR(connector); 1258 } 1259 1260 drm_connector_attach_encoder(connector, encoder); 1261 } 1262 1263 drm_for_each_encoder(encoder, drm) { 1264 clone_mask |= BIT(drm_encoder_index(encoder)); 1265 } 1266 1267 drm_for_each_encoder(encoder, drm) { 1268 encoder->possible_clones = clone_mask; 1269 } 1270 1271 ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm); 1272 if (ret) { 1273 dev_err(dev, "Unable to install IRQ handler\n"); 1274 return ret; 1275 } 1276 1277 ret = drm_vblank_init(drm, 1); 1278 if (ret) { 1279 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1280 return ret; 1281 } 1282 1283 drm_mode_config_reset(drm); 1284 1285 ret = clk_prepare_enable(priv->pix_clk); 1286 if (ret) { 1287 dev_err(dev, "Unable to start pixel clock\n"); 1288 return ret; 1289 } 1290 1291 if (priv->lcd_clk) { 1292 parent_clk = clk_get_parent(priv->lcd_clk); 1293 parent_rate = clk_get_rate(parent_clk); 1294 1295 /* LCD Device clock must be 3x the pixel clock for STN panels, 1296 * or 1.5x the pixel clock for TFT panels. To avoid having to 1297 * check for the LCD device clock everytime we do a mode change, 1298 * we set the LCD device clock to the highest rate possible. 1299 */ 1300 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1301 if (ret) { 1302 dev_err(dev, "Unable to set LCD clock rate\n"); 1303 goto err_pixclk_disable; 1304 } 1305 1306 ret = clk_prepare_enable(priv->lcd_clk); 1307 if (ret) { 1308 dev_err(dev, "Unable to start lcd clock\n"); 1309 goto err_pixclk_disable; 1310 } 1311 } 1312 1313 /* Enable OSD if available */ 1314 if (soc_info->has_osd) 1315 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); 1316 1317 mutex_init(&priv->clk_mutex); 1318 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1319 1320 parent_clk = clk_get_parent(priv->pix_clk); 1321 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1322 if (ret) { 1323 dev_err(dev, "Unable to register clock notifier\n"); 1324 goto err_devclk_disable; 1325 } 1326 1327 private_state = kzalloc(sizeof(*private_state), GFP_KERNEL); 1328 if (!private_state) { 1329 ret = -ENOMEM; 1330 goto err_clk_notifier_unregister; 1331 } 1332 1333 drm_atomic_private_obj_init(drm, &priv->private_obj, &private_state->base, 1334 &ingenic_drm_private_state_funcs); 1335 1336 ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini, 1337 &priv->private_obj); 1338 if (ret) 1339 goto err_private_state_free; 1340 1341 ret = drm_dev_register(drm, 0); 1342 if (ret) { 1343 dev_err(dev, "Failed to register DRM driver\n"); 1344 goto err_clk_notifier_unregister; 1345 } 1346 1347 drm_fbdev_generic_setup(drm, 32); 1348 1349 return 0; 1350 1351 err_private_state_free: 1352 kfree(private_state); 1353 err_clk_notifier_unregister: 1354 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1355 err_devclk_disable: 1356 if (priv->lcd_clk) 1357 clk_disable_unprepare(priv->lcd_clk); 1358 err_pixclk_disable: 1359 clk_disable_unprepare(priv->pix_clk); 1360 return ret; 1361 } 1362 1363 static int ingenic_drm_bind_with_components(struct device *dev) 1364 { 1365 return ingenic_drm_bind(dev, true); 1366 } 1367 1368 static int compare_of(struct device *dev, void *data) 1369 { 1370 return dev->of_node == data; 1371 } 1372 1373 static void ingenic_drm_unbind(struct device *dev) 1374 { 1375 struct ingenic_drm *priv = dev_get_drvdata(dev); 1376 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1377 1378 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1379 if (priv->lcd_clk) 1380 clk_disable_unprepare(priv->lcd_clk); 1381 clk_disable_unprepare(priv->pix_clk); 1382 1383 drm_dev_unregister(&priv->drm); 1384 drm_atomic_helper_shutdown(&priv->drm); 1385 } 1386 1387 static const struct component_master_ops ingenic_master_ops = { 1388 .bind = ingenic_drm_bind_with_components, 1389 .unbind = ingenic_drm_unbind, 1390 }; 1391 1392 static int ingenic_drm_probe(struct platform_device *pdev) 1393 { 1394 struct device *dev = &pdev->dev; 1395 struct component_match *match = NULL; 1396 struct device_node *np; 1397 1398 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1399 return ingenic_drm_bind(dev, false); 1400 1401 /* IPU is at port address 8 */ 1402 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1403 if (!np) 1404 return ingenic_drm_bind(dev, false); 1405 1406 drm_of_component_match_add(dev, &match, compare_of, np); 1407 of_node_put(np); 1408 1409 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1410 } 1411 1412 static int ingenic_drm_remove(struct platform_device *pdev) 1413 { 1414 struct device *dev = &pdev->dev; 1415 1416 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1417 ingenic_drm_unbind(dev); 1418 else 1419 component_master_del(dev, &ingenic_master_ops); 1420 1421 return 0; 1422 } 1423 1424 static int __maybe_unused ingenic_drm_suspend(struct device *dev) 1425 { 1426 struct ingenic_drm *priv = dev_get_drvdata(dev); 1427 1428 return drm_mode_config_helper_suspend(&priv->drm); 1429 } 1430 1431 static int __maybe_unused ingenic_drm_resume(struct device *dev) 1432 { 1433 struct ingenic_drm *priv = dev_get_drvdata(dev); 1434 1435 return drm_mode_config_helper_resume(&priv->drm); 1436 } 1437 1438 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume); 1439 1440 static const u32 jz4740_formats[] = { 1441 DRM_FORMAT_XRGB1555, 1442 DRM_FORMAT_RGB565, 1443 DRM_FORMAT_XRGB8888, 1444 }; 1445 1446 static const u32 jz4725b_formats_f1[] = { 1447 DRM_FORMAT_XRGB1555, 1448 DRM_FORMAT_RGB565, 1449 DRM_FORMAT_XRGB8888, 1450 }; 1451 1452 static const u32 jz4725b_formats_f0[] = { 1453 DRM_FORMAT_C8, 1454 DRM_FORMAT_XRGB1555, 1455 DRM_FORMAT_RGB565, 1456 DRM_FORMAT_XRGB8888, 1457 }; 1458 1459 static const u32 jz4770_formats_f1[] = { 1460 DRM_FORMAT_XRGB1555, 1461 DRM_FORMAT_RGB565, 1462 DRM_FORMAT_RGB888, 1463 DRM_FORMAT_XRGB8888, 1464 DRM_FORMAT_XRGB2101010, 1465 }; 1466 1467 static const u32 jz4770_formats_f0[] = { 1468 DRM_FORMAT_C8, 1469 DRM_FORMAT_XRGB1555, 1470 DRM_FORMAT_RGB565, 1471 DRM_FORMAT_RGB888, 1472 DRM_FORMAT_XRGB8888, 1473 DRM_FORMAT_XRGB2101010, 1474 }; 1475 1476 static const struct jz_soc_info jz4740_soc_info = { 1477 .needs_dev_clk = true, 1478 .has_osd = false, 1479 .map_noncoherent = false, 1480 .max_width = 800, 1481 .max_height = 600, 1482 .formats_f1 = jz4740_formats, 1483 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1484 /* JZ4740 has only one plane */ 1485 }; 1486 1487 static const struct jz_soc_info jz4725b_soc_info = { 1488 .needs_dev_clk = false, 1489 .has_osd = true, 1490 .map_noncoherent = false, 1491 .max_width = 800, 1492 .max_height = 600, 1493 .formats_f1 = jz4725b_formats_f1, 1494 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1495 .formats_f0 = jz4725b_formats_f0, 1496 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1497 }; 1498 1499 static const struct jz_soc_info jz4770_soc_info = { 1500 .needs_dev_clk = false, 1501 .has_osd = true, 1502 .map_noncoherent = true, 1503 .max_width = 1280, 1504 .max_height = 720, 1505 .formats_f1 = jz4770_formats_f1, 1506 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1507 .formats_f0 = jz4770_formats_f0, 1508 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1509 }; 1510 1511 static const struct jz_soc_info jz4780_soc_info = { 1512 .needs_dev_clk = true, 1513 .has_osd = true, 1514 .use_extended_hwdesc = true, 1515 .max_width = 4096, 1516 .max_height = 2048, 1517 .formats_f1 = jz4770_formats_f1, 1518 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1519 .formats_f0 = jz4770_formats_f0, 1520 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1521 }; 1522 1523 static const struct of_device_id ingenic_drm_of_match[] = { 1524 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1525 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1526 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1527 { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info }, 1528 { /* sentinel */ }, 1529 }; 1530 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1531 1532 static struct platform_driver ingenic_drm_driver = { 1533 .driver = { 1534 .name = "ingenic-drm", 1535 .pm = pm_ptr(&ingenic_drm_pm_ops), 1536 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1537 }, 1538 .probe = ingenic_drm_probe, 1539 .remove = ingenic_drm_remove, 1540 }; 1541 1542 static int ingenic_drm_init(void) 1543 { 1544 int err; 1545 1546 if (drm_firmware_drivers_only()) 1547 return -ENODEV; 1548 1549 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1550 err = platform_driver_register(ingenic_ipu_driver_ptr); 1551 if (err) 1552 return err; 1553 } 1554 1555 return platform_driver_register(&ingenic_drm_driver); 1556 } 1557 module_init(ingenic_drm_init); 1558 1559 static void ingenic_drm_exit(void) 1560 { 1561 platform_driver_unregister(&ingenic_drm_driver); 1562 1563 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1564 platform_driver_unregister(ingenic_ipu_driver_ptr); 1565 } 1566 module_exit(ingenic_drm_exit); 1567 1568 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1569 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1570 MODULE_LICENSE("GPL v2"); 1571