1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/component.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of_device.h> 16 #include <linux/of_reserved_mem.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/regmap.h> 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_color_mgmt.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_drv.h> 29 #include <drm/drm_encoder.h> 30 #include <drm/drm_gem_cma_helper.h> 31 #include <drm/drm_fb_cma_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/drm_fourcc.h> 34 #include <drm/drm_gem_atomic_helper.h> 35 #include <drm/drm_gem_framebuffer_helper.h> 36 #include <drm/drm_managed.h> 37 #include <drm/drm_of.h> 38 #include <drm/drm_panel.h> 39 #include <drm/drm_plane.h> 40 #include <drm/drm_plane_helper.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/drm_vblank.h> 43 44 struct ingenic_dma_hwdesc { 45 u32 next; 46 u32 addr; 47 u32 id; 48 u32 cmd; 49 } __aligned(16); 50 51 struct ingenic_dma_hwdescs { 52 struct ingenic_dma_hwdesc hwdesc_f0; 53 struct ingenic_dma_hwdesc hwdesc_f1; 54 struct ingenic_dma_hwdesc hwdesc_pal; 55 u16 palette[256] __aligned(16); 56 }; 57 58 struct jz_soc_info { 59 bool needs_dev_clk; 60 bool has_osd; 61 bool map_noncoherent; 62 unsigned int max_width, max_height; 63 const u32 *formats_f0, *formats_f1; 64 unsigned int num_formats_f0, num_formats_f1; 65 }; 66 67 struct ingenic_drm { 68 struct drm_device drm; 69 /* 70 * f1 (aka. foreground1) is our primary plane, on top of which 71 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 72 * hardware and cannot be changed. 73 */ 74 struct drm_plane f0, f1, *ipu_plane; 75 struct drm_crtc crtc; 76 77 struct device *dev; 78 struct regmap *map; 79 struct clk *lcd_clk, *pix_clk; 80 const struct jz_soc_info *soc_info; 81 82 struct ingenic_dma_hwdescs *dma_hwdescs; 83 dma_addr_t dma_hwdescs_phys; 84 85 bool panel_is_sharp; 86 bool no_vblank; 87 88 /* 89 * clk_mutex is used to synchronize the pixel clock rate update with 90 * the VBLANK. When the pixel clock's parent clock needs to be updated, 91 * clock_nb's notifier function will lock the mutex, then wait until the 92 * next VBLANK. At that point, the parent clock's rate can be updated, 93 * and the mutex is then unlocked. If an atomic commit happens in the 94 * meantime, it will lock on the mutex, effectively waiting until the 95 * clock update process finishes. Finally, the pixel clock's rate will 96 * be recomputed when the mutex has been released, in the pending atomic 97 * commit, or a future one. 98 */ 99 struct mutex clk_mutex; 100 bool update_clk_rate; 101 struct notifier_block clock_nb; 102 }; 103 104 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 105 { 106 switch (reg) { 107 case JZ_REG_LCD_IID: 108 case JZ_REG_LCD_SA0: 109 case JZ_REG_LCD_FID0: 110 case JZ_REG_LCD_CMD0: 111 case JZ_REG_LCD_SA1: 112 case JZ_REG_LCD_FID1: 113 case JZ_REG_LCD_CMD1: 114 return false; 115 default: 116 return true; 117 } 118 } 119 120 static const struct regmap_config ingenic_drm_regmap_config = { 121 .reg_bits = 32, 122 .val_bits = 32, 123 .reg_stride = 4, 124 125 .max_register = JZ_REG_LCD_SIZE1, 126 .writeable_reg = ingenic_drm_writeable_reg, 127 }; 128 129 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 130 { 131 return container_of(drm, struct ingenic_drm, drm); 132 } 133 134 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 135 { 136 return container_of(crtc, struct ingenic_drm, crtc); 137 } 138 139 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 140 { 141 return container_of(nb, struct ingenic_drm, clock_nb); 142 } 143 144 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 145 unsigned long action, 146 void *data) 147 { 148 struct ingenic_drm *priv = drm_nb_get_priv(nb); 149 150 switch (action) { 151 case PRE_RATE_CHANGE: 152 mutex_lock(&priv->clk_mutex); 153 priv->update_clk_rate = true; 154 drm_crtc_wait_one_vblank(&priv->crtc); 155 return NOTIFY_OK; 156 default: 157 mutex_unlock(&priv->clk_mutex); 158 return NOTIFY_OK; 159 } 160 } 161 162 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 163 struct drm_atomic_state *state) 164 { 165 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 166 167 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 168 169 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 170 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 171 JZ_LCD_CTRL_ENABLE); 172 173 drm_crtc_vblank_on(crtc); 174 } 175 176 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 177 struct drm_atomic_state *state) 178 { 179 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 180 unsigned int var; 181 182 drm_crtc_vblank_off(crtc); 183 184 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 185 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 186 187 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 188 var & JZ_LCD_STATE_DISABLED, 189 1000, 0); 190 } 191 192 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 193 struct drm_display_mode *mode) 194 { 195 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 196 197 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start; 198 vds = mode->crtc_vtotal - mode->crtc_vsync_start; 199 vde = vds + mode->crtc_vdisplay; 200 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay; 201 202 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start; 203 hds = mode->crtc_htotal - mode->crtc_hsync_start; 204 hde = hds + mode->crtc_hdisplay; 205 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay; 206 207 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 208 0 << JZ_LCD_VSYNC_VPS_OFFSET | 209 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 210 211 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 212 0 << JZ_LCD_HSYNC_HPS_OFFSET | 213 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 214 215 regmap_write(priv->map, JZ_REG_LCD_VAT, 216 ht << JZ_LCD_VAT_HT_OFFSET | 217 vt << JZ_LCD_VAT_VT_OFFSET); 218 219 regmap_write(priv->map, JZ_REG_LCD_DAH, 220 hds << JZ_LCD_DAH_HDS_OFFSET | 221 hde << JZ_LCD_DAH_HDE_OFFSET); 222 regmap_write(priv->map, JZ_REG_LCD_DAV, 223 vds << JZ_LCD_DAV_VDS_OFFSET | 224 vde << JZ_LCD_DAV_VDE_OFFSET); 225 226 if (priv->panel_is_sharp) { 227 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 228 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 229 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 230 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 231 } 232 233 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 234 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 235 236 /* 237 * IPU restart - specify how much time the LCDC will wait before 238 * transferring a new frame from the IPU. The value is the one 239 * suggested in the programming manual. 240 */ 241 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 242 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 243 } 244 245 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 246 struct drm_atomic_state *state) 247 { 248 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 249 crtc); 250 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 251 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 252 253 if (crtc_state->gamma_lut && 254 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 255 dev_dbg(priv->dev, "Invalid palette size\n"); 256 return -EINVAL; 257 } 258 259 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 260 f1_state = drm_atomic_get_plane_state(crtc_state->state, 261 &priv->f1); 262 if (IS_ERR(f1_state)) 263 return PTR_ERR(f1_state); 264 265 f0_state = drm_atomic_get_plane_state(crtc_state->state, 266 &priv->f0); 267 if (IS_ERR(f0_state)) 268 return PTR_ERR(f0_state); 269 270 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 271 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 272 priv->ipu_plane); 273 if (IS_ERR(ipu_state)) 274 return PTR_ERR(ipu_state); 275 276 /* IPU and F1 planes cannot be enabled at the same time. */ 277 if (f1_state->fb && ipu_state->fb) { 278 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 279 return -EINVAL; 280 } 281 } 282 283 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 284 priv->no_vblank = !f1_state->fb && !f0_state->fb && 285 !(ipu_state && ipu_state->fb); 286 } 287 288 return 0; 289 } 290 291 static enum drm_mode_status 292 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 293 { 294 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 295 long rate; 296 297 if (mode->hdisplay > priv->soc_info->max_width) 298 return MODE_BAD_HVALUE; 299 if (mode->vdisplay > priv->soc_info->max_height) 300 return MODE_BAD_VVALUE; 301 302 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 303 if (rate < 0) 304 return MODE_CLOCK_RANGE; 305 306 return MODE_OK; 307 } 308 309 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 310 struct drm_atomic_state *state) 311 { 312 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 313 crtc); 314 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 315 u32 ctrl = 0; 316 317 if (priv->soc_info->has_osd && 318 drm_atomic_crtc_needs_modeset(crtc_state)) { 319 /* 320 * If IPU plane is enabled, enable IPU as source for the F1 321 * plane; otherwise use regular DMA. 322 */ 323 if (priv->ipu_plane && priv->ipu_plane->state->fb) 324 ctrl |= JZ_LCD_OSDCTRL_IPU; 325 326 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 327 JZ_LCD_OSDCTRL_IPU, ctrl); 328 } 329 } 330 331 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 332 struct drm_atomic_state *state) 333 { 334 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 335 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 336 crtc); 337 struct drm_pending_vblank_event *event = crtc_state->event; 338 339 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 340 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode); 341 priv->update_clk_rate = true; 342 } 343 344 if (priv->update_clk_rate) { 345 mutex_lock(&priv->clk_mutex); 346 clk_set_rate(priv->pix_clk, 347 crtc_state->adjusted_mode.crtc_clock * 1000); 348 priv->update_clk_rate = false; 349 mutex_unlock(&priv->clk_mutex); 350 } 351 352 if (event) { 353 crtc_state->event = NULL; 354 355 spin_lock_irq(&crtc->dev->event_lock); 356 if (drm_crtc_vblank_get(crtc) == 0) 357 drm_crtc_arm_vblank_event(crtc, event); 358 else 359 drm_crtc_send_vblank_event(crtc, event); 360 spin_unlock_irq(&crtc->dev->event_lock); 361 } 362 } 363 364 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 365 struct drm_atomic_state *state) 366 { 367 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 368 plane); 369 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 370 plane); 371 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 372 struct drm_crtc_state *crtc_state; 373 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 374 int ret; 375 376 if (!crtc) 377 return 0; 378 379 crtc_state = drm_atomic_get_existing_crtc_state(state, 380 crtc); 381 if (WARN_ON(!crtc_state)) 382 return -EINVAL; 383 384 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 385 DRM_PLANE_HELPER_NO_SCALING, 386 DRM_PLANE_HELPER_NO_SCALING, 387 priv->soc_info->has_osd, 388 true); 389 if (ret) 390 return ret; 391 392 /* 393 * If OSD is not available, check that the width/height match. 394 * Note that state->src_* are in 16.16 fixed-point format. 395 */ 396 if (!priv->soc_info->has_osd && 397 (new_plane_state->src_x != 0 || 398 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w || 399 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) 400 return -EINVAL; 401 402 /* 403 * Require full modeset if enabling or disabling a plane, or changing 404 * its position, size or depth. 405 */ 406 if (priv->soc_info->has_osd && 407 (!old_plane_state->fb || !new_plane_state->fb || 408 old_plane_state->crtc_x != new_plane_state->crtc_x || 409 old_plane_state->crtc_y != new_plane_state->crtc_y || 410 old_plane_state->crtc_w != new_plane_state->crtc_w || 411 old_plane_state->crtc_h != new_plane_state->crtc_h || 412 old_plane_state->fb->format->format != new_plane_state->fb->format->format)) 413 crtc_state->mode_changed = true; 414 415 if (priv->soc_info->map_noncoherent) 416 drm_atomic_helper_check_plane_damage(state, new_plane_state); 417 418 return 0; 419 } 420 421 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 422 struct drm_plane *plane) 423 { 424 unsigned int en_bit; 425 426 if (priv->soc_info->has_osd) { 427 if (plane != &priv->f0) 428 en_bit = JZ_LCD_OSDC_F1EN; 429 else 430 en_bit = JZ_LCD_OSDC_F0EN; 431 432 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 433 } 434 } 435 436 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 437 { 438 struct ingenic_drm *priv = dev_get_drvdata(dev); 439 unsigned int en_bit; 440 441 if (priv->soc_info->has_osd) { 442 if (plane != &priv->f0) 443 en_bit = JZ_LCD_OSDC_F1EN; 444 else 445 en_bit = JZ_LCD_OSDC_F0EN; 446 447 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 448 } 449 } 450 451 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 452 struct drm_atomic_state *state) 453 { 454 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 455 456 ingenic_drm_plane_disable(priv->dev, plane); 457 } 458 459 void ingenic_drm_plane_config(struct device *dev, 460 struct drm_plane *plane, u32 fourcc) 461 { 462 struct ingenic_drm *priv = dev_get_drvdata(dev); 463 struct drm_plane_state *state = plane->state; 464 unsigned int xy_reg, size_reg; 465 unsigned int ctrl = 0; 466 467 ingenic_drm_plane_enable(priv, plane); 468 469 if (priv->soc_info->has_osd && plane != &priv->f0) { 470 switch (fourcc) { 471 case DRM_FORMAT_XRGB1555: 472 ctrl |= JZ_LCD_OSDCTRL_RGB555; 473 fallthrough; 474 case DRM_FORMAT_RGB565: 475 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 476 break; 477 case DRM_FORMAT_RGB888: 478 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 479 break; 480 case DRM_FORMAT_XRGB8888: 481 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 482 break; 483 case DRM_FORMAT_XRGB2101010: 484 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 485 break; 486 } 487 488 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 489 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 490 } else { 491 switch (fourcc) { 492 case DRM_FORMAT_C8: 493 ctrl |= JZ_LCD_CTRL_BPP_8; 494 break; 495 case DRM_FORMAT_XRGB1555: 496 ctrl |= JZ_LCD_CTRL_RGB555; 497 fallthrough; 498 case DRM_FORMAT_RGB565: 499 ctrl |= JZ_LCD_CTRL_BPP_15_16; 500 break; 501 case DRM_FORMAT_RGB888: 502 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 503 break; 504 case DRM_FORMAT_XRGB8888: 505 ctrl |= JZ_LCD_CTRL_BPP_18_24; 506 break; 507 case DRM_FORMAT_XRGB2101010: 508 ctrl |= JZ_LCD_CTRL_BPP_30; 509 break; 510 } 511 512 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 513 JZ_LCD_CTRL_BPP_MASK, ctrl); 514 } 515 516 if (priv->soc_info->has_osd) { 517 if (plane != &priv->f0) { 518 xy_reg = JZ_REG_LCD_XYP1; 519 size_reg = JZ_REG_LCD_SIZE1; 520 } else { 521 xy_reg = JZ_REG_LCD_XYP0; 522 size_reg = JZ_REG_LCD_SIZE0; 523 } 524 525 regmap_write(priv->map, xy_reg, 526 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 527 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 528 regmap_write(priv->map, size_reg, 529 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 530 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 531 } 532 } 533 534 bool ingenic_drm_map_noncoherent(const struct device *dev) 535 { 536 const struct ingenic_drm *priv = dev_get_drvdata(dev); 537 538 return priv->soc_info->map_noncoherent; 539 } 540 541 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 542 const struct drm_color_lut *lut) 543 { 544 unsigned int i; 545 546 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 547 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 548 | drm_color_lut_extract(lut[i].green, 6) << 5 549 | drm_color_lut_extract(lut[i].blue, 5); 550 551 priv->dma_hwdescs->palette[i] = color; 552 } 553 } 554 555 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 556 struct drm_atomic_state *state) 557 { 558 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 559 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); 560 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); 561 struct drm_crtc_state *crtc_state; 562 struct ingenic_dma_hwdesc *hwdesc; 563 unsigned int width, height, cpp, offset; 564 dma_addr_t addr; 565 u32 fourcc; 566 567 if (newstate && newstate->fb) { 568 if (priv->soc_info->map_noncoherent) 569 drm_fb_cma_sync_non_coherent(&priv->drm, oldstate, newstate); 570 571 crtc_state = newstate->crtc->state; 572 573 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0); 574 width = newstate->src_w >> 16; 575 height = newstate->src_h >> 16; 576 cpp = newstate->fb->format->cpp[0]; 577 578 if (!priv->soc_info->has_osd || plane == &priv->f0) 579 hwdesc = &priv->dma_hwdescs->hwdesc_f0; 580 else 581 hwdesc = &priv->dma_hwdescs->hwdesc_f1; 582 583 hwdesc->addr = addr; 584 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 585 586 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 587 fourcc = newstate->fb->format->format; 588 589 ingenic_drm_plane_config(priv->dev, plane, fourcc); 590 591 if (fourcc == DRM_FORMAT_C8) 592 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_pal); 593 else 594 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 595 596 priv->dma_hwdescs->hwdesc_f0.next = priv->dma_hwdescs_phys + offset; 597 598 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 599 } 600 601 if (crtc_state->color_mgmt_changed) 602 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 603 } 604 } 605 606 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 607 struct drm_crtc_state *crtc_state, 608 struct drm_connector_state *conn_state) 609 { 610 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 611 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 612 struct drm_connector *conn = conn_state->connector; 613 struct drm_display_info *info = &conn->display_info; 614 unsigned int cfg, rgbcfg = 0; 615 616 priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS; 617 618 if (priv->panel_is_sharp) { 619 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 620 } else { 621 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 622 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 623 } 624 625 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 626 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 627 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 628 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 629 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 630 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 631 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 632 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 633 634 if (!priv->panel_is_sharp) { 635 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) { 636 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 637 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 638 else 639 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 640 } else { 641 switch (*info->bus_formats) { 642 case MEDIA_BUS_FMT_RGB565_1X16: 643 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 644 break; 645 case MEDIA_BUS_FMT_RGB666_1X18: 646 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 647 break; 648 case MEDIA_BUS_FMT_RGB888_1X24: 649 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 650 break; 651 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 652 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; 653 fallthrough; 654 case MEDIA_BUS_FMT_RGB888_3X8: 655 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 656 break; 657 default: 658 break; 659 } 660 } 661 } 662 663 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 664 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); 665 } 666 667 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, 668 struct drm_crtc_state *crtc_state, 669 struct drm_connector_state *conn_state) 670 { 671 struct drm_display_info *info = &conn_state->connector->display_info; 672 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 673 674 if (info->num_bus_formats != 1) 675 return -EINVAL; 676 677 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 678 return 0; 679 680 switch (*info->bus_formats) { 681 case MEDIA_BUS_FMT_RGB888_3X8: 682 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 683 /* 684 * The LCD controller expects timing values in dot-clock ticks, 685 * which is 3x the timing values in pixels when using a 3x8-bit 686 * display; but it will count the display area size in pixels 687 * either way. Go figure. 688 */ 689 mode->crtc_clock = mode->clock * 3; 690 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2; 691 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2; 692 mode->crtc_hdisplay = mode->hdisplay; 693 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2; 694 return 0; 695 case MEDIA_BUS_FMT_RGB565_1X16: 696 case MEDIA_BUS_FMT_RGB666_1X18: 697 case MEDIA_BUS_FMT_RGB888_1X24: 698 return 0; 699 default: 700 return -EINVAL; 701 } 702 } 703 704 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 705 { 706 struct ingenic_drm *priv = drm_device_get_priv(arg); 707 unsigned int state; 708 709 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 710 711 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 712 JZ_LCD_STATE_EOF_IRQ, 0); 713 714 if (state & JZ_LCD_STATE_EOF_IRQ) 715 drm_crtc_handle_vblank(&priv->crtc); 716 717 return IRQ_HANDLED; 718 } 719 720 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 721 { 722 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 723 724 if (priv->no_vblank) 725 return -EINVAL; 726 727 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 728 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 729 730 return 0; 731 } 732 733 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 734 { 735 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 736 737 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 738 } 739 740 static struct drm_framebuffer * 741 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, 742 const struct drm_mode_fb_cmd2 *mode_cmd) 743 { 744 struct ingenic_drm *priv = drm_device_get_priv(drm); 745 746 if (priv->soc_info->map_noncoherent) 747 return drm_gem_fb_create_with_dirty(drm, file, mode_cmd); 748 749 return drm_gem_fb_create(drm, file, mode_cmd); 750 } 751 752 static struct drm_gem_object * 753 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size) 754 { 755 struct ingenic_drm *priv = drm_device_get_priv(drm); 756 struct drm_gem_cma_object *obj; 757 758 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 759 if (!obj) 760 return ERR_PTR(-ENOMEM); 761 762 obj->map_noncoherent = priv->soc_info->map_noncoherent; 763 764 return &obj->base; 765 } 766 767 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 768 769 static const struct drm_driver ingenic_drm_driver_data = { 770 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 771 .name = "ingenic-drm", 772 .desc = "DRM module for Ingenic SoCs", 773 .date = "20200716", 774 .major = 1, 775 .minor = 1, 776 .patchlevel = 0, 777 778 .fops = &ingenic_drm_fops, 779 .gem_create_object = ingenic_drm_gem_create_object, 780 DRM_GEM_CMA_DRIVER_OPS, 781 }; 782 783 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 784 .update_plane = drm_atomic_helper_update_plane, 785 .disable_plane = drm_atomic_helper_disable_plane, 786 .reset = drm_atomic_helper_plane_reset, 787 .destroy = drm_plane_cleanup, 788 789 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 790 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 791 }; 792 793 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 794 .set_config = drm_atomic_helper_set_config, 795 .page_flip = drm_atomic_helper_page_flip, 796 .reset = drm_atomic_helper_crtc_reset, 797 .destroy = drm_crtc_cleanup, 798 799 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 800 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 801 802 .enable_vblank = ingenic_drm_enable_vblank, 803 .disable_vblank = ingenic_drm_disable_vblank, 804 }; 805 806 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 807 .atomic_update = ingenic_drm_plane_atomic_update, 808 .atomic_check = ingenic_drm_plane_atomic_check, 809 .atomic_disable = ingenic_drm_plane_atomic_disable, 810 }; 811 812 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 813 .atomic_enable = ingenic_drm_crtc_atomic_enable, 814 .atomic_disable = ingenic_drm_crtc_atomic_disable, 815 .atomic_begin = ingenic_drm_crtc_atomic_begin, 816 .atomic_flush = ingenic_drm_crtc_atomic_flush, 817 .atomic_check = ingenic_drm_crtc_atomic_check, 818 .mode_valid = ingenic_drm_crtc_mode_valid, 819 }; 820 821 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 822 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 823 .atomic_check = ingenic_drm_encoder_atomic_check, 824 }; 825 826 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 827 .fb_create = ingenic_drm_gem_fb_create, 828 .output_poll_changed = drm_fb_helper_output_poll_changed, 829 .atomic_check = drm_atomic_helper_check, 830 .atomic_commit = drm_atomic_helper_commit, 831 }; 832 833 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 834 .atomic_commit_tail = drm_atomic_helper_commit_tail, 835 }; 836 837 static void ingenic_drm_unbind_all(void *d) 838 { 839 struct ingenic_drm *priv = d; 840 841 component_unbind_all(priv->dev, &priv->drm); 842 } 843 844 static void __maybe_unused ingenic_drm_release_rmem(void *d) 845 { 846 of_reserved_mem_device_release(d); 847 } 848 849 static int ingenic_drm_bind(struct device *dev, bool has_components) 850 { 851 struct platform_device *pdev = to_platform_device(dev); 852 const struct jz_soc_info *soc_info; 853 struct ingenic_drm *priv; 854 struct clk *parent_clk; 855 struct drm_plane *primary; 856 struct drm_bridge *bridge; 857 struct drm_panel *panel; 858 struct drm_encoder *encoder; 859 struct drm_device *drm; 860 void __iomem *base; 861 long parent_rate; 862 unsigned int i, clone_mask = 0; 863 dma_addr_t dma_hwdesc_phys_f0, dma_hwdesc_phys_f1; 864 int ret, irq; 865 866 soc_info = of_device_get_match_data(dev); 867 if (!soc_info) { 868 dev_err(dev, "Missing platform data\n"); 869 return -EINVAL; 870 } 871 872 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 873 ret = of_reserved_mem_device_init(dev); 874 875 if (ret && ret != -ENODEV) 876 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 877 878 if (!ret) { 879 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 880 if (ret) 881 return ret; 882 } 883 } 884 885 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 886 struct ingenic_drm, drm); 887 if (IS_ERR(priv)) 888 return PTR_ERR(priv); 889 890 priv->soc_info = soc_info; 891 priv->dev = dev; 892 drm = &priv->drm; 893 894 platform_set_drvdata(pdev, priv); 895 896 ret = drmm_mode_config_init(drm); 897 if (ret) 898 return ret; 899 900 drm->mode_config.min_width = 0; 901 drm->mode_config.min_height = 0; 902 drm->mode_config.max_width = soc_info->max_width; 903 drm->mode_config.max_height = 4095; 904 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 905 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 906 907 base = devm_platform_ioremap_resource(pdev, 0); 908 if (IS_ERR(base)) { 909 dev_err(dev, "Failed to get memory resource\n"); 910 return PTR_ERR(base); 911 } 912 913 priv->map = devm_regmap_init_mmio(dev, base, 914 &ingenic_drm_regmap_config); 915 if (IS_ERR(priv->map)) { 916 dev_err(dev, "Failed to create regmap\n"); 917 return PTR_ERR(priv->map); 918 } 919 920 irq = platform_get_irq(pdev, 0); 921 if (irq < 0) 922 return irq; 923 924 if (soc_info->needs_dev_clk) { 925 priv->lcd_clk = devm_clk_get(dev, "lcd"); 926 if (IS_ERR(priv->lcd_clk)) { 927 dev_err(dev, "Failed to get lcd clock\n"); 928 return PTR_ERR(priv->lcd_clk); 929 } 930 } 931 932 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 933 if (IS_ERR(priv->pix_clk)) { 934 dev_err(dev, "Failed to get pixel clock\n"); 935 return PTR_ERR(priv->pix_clk); 936 } 937 938 priv->dma_hwdescs = dmam_alloc_coherent(dev, 939 sizeof(*priv->dma_hwdescs), 940 &priv->dma_hwdescs_phys, 941 GFP_KERNEL); 942 if (!priv->dma_hwdescs) 943 return -ENOMEM; 944 945 946 /* Configure DMA hwdesc for foreground0 plane */ 947 dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys 948 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 949 priv->dma_hwdescs->hwdesc_f0.next = dma_hwdesc_phys_f0; 950 priv->dma_hwdescs->hwdesc_f0.id = 0xf0; 951 952 /* Configure DMA hwdesc for foreground1 plane */ 953 dma_hwdesc_phys_f1 = priv->dma_hwdescs_phys 954 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f1); 955 priv->dma_hwdescs->hwdesc_f1.next = dma_hwdesc_phys_f1; 956 priv->dma_hwdescs->hwdesc_f1.id = 0xf1; 957 958 /* Configure DMA hwdesc for palette */ 959 priv->dma_hwdescs->hwdesc_pal.next = priv->dma_hwdescs_phys 960 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 961 priv->dma_hwdescs->hwdesc_pal.id = 0xc0; 962 priv->dma_hwdescs->hwdesc_pal.addr = priv->dma_hwdescs_phys 963 + offsetof(struct ingenic_dma_hwdescs, palette); 964 priv->dma_hwdescs->hwdesc_pal.cmd = JZ_LCD_CMD_ENABLE_PAL 965 | (sizeof(priv->dma_hwdescs->palette) / 4); 966 967 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0; 968 969 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs); 970 971 ret = drm_universal_plane_init(drm, primary, 1, 972 &ingenic_drm_primary_plane_funcs, 973 priv->soc_info->formats_f1, 974 priv->soc_info->num_formats_f1, 975 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 976 if (ret) { 977 dev_err(dev, "Failed to register plane: %i\n", ret); 978 return ret; 979 } 980 981 if (soc_info->map_noncoherent) 982 drm_plane_enable_fb_damage_clips(&priv->f1); 983 984 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 985 986 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary, 987 NULL, &ingenic_drm_crtc_funcs, NULL); 988 if (ret) { 989 dev_err(dev, "Failed to init CRTC: %i\n", ret); 990 return ret; 991 } 992 993 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 994 ARRAY_SIZE(priv->dma_hwdescs->palette)); 995 996 if (soc_info->has_osd) { 997 drm_plane_helper_add(&priv->f0, 998 &ingenic_drm_plane_helper_funcs); 999 1000 ret = drm_universal_plane_init(drm, &priv->f0, 1, 1001 &ingenic_drm_primary_plane_funcs, 1002 priv->soc_info->formats_f0, 1003 priv->soc_info->num_formats_f0, 1004 NULL, DRM_PLANE_TYPE_OVERLAY, 1005 NULL); 1006 if (ret) { 1007 dev_err(dev, "Failed to register overlay plane: %i\n", 1008 ret); 1009 return ret; 1010 } 1011 1012 if (soc_info->map_noncoherent) 1013 drm_plane_enable_fb_damage_clips(&priv->f0); 1014 1015 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 1016 ret = component_bind_all(dev, drm); 1017 if (ret) { 1018 if (ret != -EPROBE_DEFER) 1019 dev_err(dev, "Failed to bind components: %i\n", ret); 1020 return ret; 1021 } 1022 1023 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 1024 if (ret) 1025 return ret; 1026 1027 priv->ipu_plane = drm_plane_from_index(drm, 2); 1028 if (!priv->ipu_plane) { 1029 dev_err(dev, "Failed to retrieve IPU plane\n"); 1030 return -EINVAL; 1031 } 1032 } 1033 } 1034 1035 for (i = 0; ; i++) { 1036 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 1037 if (ret) { 1038 if (ret == -ENODEV) 1039 break; /* we're done */ 1040 if (ret != -EPROBE_DEFER) 1041 dev_err(dev, "Failed to get bridge handle\n"); 1042 return ret; 1043 } 1044 1045 if (panel) 1046 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 1047 DRM_MODE_CONNECTOR_DPI); 1048 1049 encoder = drmm_plain_encoder_alloc(drm, NULL, DRM_MODE_ENCODER_DPI, NULL); 1050 if (IS_ERR(encoder)) { 1051 ret = PTR_ERR(encoder); 1052 dev_err(dev, "Failed to init encoder: %d\n", ret); 1053 return ret; 1054 } 1055 1056 encoder->possible_crtcs = 1; 1057 1058 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1059 1060 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1061 if (ret) 1062 return ret; 1063 } 1064 1065 drm_for_each_encoder(encoder, drm) { 1066 clone_mask |= BIT(drm_encoder_index(encoder)); 1067 } 1068 1069 drm_for_each_encoder(encoder, drm) { 1070 encoder->possible_clones = clone_mask; 1071 } 1072 1073 ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm); 1074 if (ret) { 1075 dev_err(dev, "Unable to install IRQ handler\n"); 1076 return ret; 1077 } 1078 1079 ret = drm_vblank_init(drm, 1); 1080 if (ret) { 1081 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1082 return ret; 1083 } 1084 1085 drm_mode_config_reset(drm); 1086 1087 ret = clk_prepare_enable(priv->pix_clk); 1088 if (ret) { 1089 dev_err(dev, "Unable to start pixel clock\n"); 1090 return ret; 1091 } 1092 1093 if (priv->lcd_clk) { 1094 parent_clk = clk_get_parent(priv->lcd_clk); 1095 parent_rate = clk_get_rate(parent_clk); 1096 1097 /* LCD Device clock must be 3x the pixel clock for STN panels, 1098 * or 1.5x the pixel clock for TFT panels. To avoid having to 1099 * check for the LCD device clock everytime we do a mode change, 1100 * we set the LCD device clock to the highest rate possible. 1101 */ 1102 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1103 if (ret) { 1104 dev_err(dev, "Unable to set LCD clock rate\n"); 1105 goto err_pixclk_disable; 1106 } 1107 1108 ret = clk_prepare_enable(priv->lcd_clk); 1109 if (ret) { 1110 dev_err(dev, "Unable to start lcd clock\n"); 1111 goto err_pixclk_disable; 1112 } 1113 } 1114 1115 /* Set address of our DMA descriptor chain */ 1116 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0); 1117 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1); 1118 1119 /* Enable OSD if available */ 1120 if (soc_info->has_osd) 1121 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); 1122 1123 mutex_init(&priv->clk_mutex); 1124 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1125 1126 parent_clk = clk_get_parent(priv->pix_clk); 1127 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1128 if (ret) { 1129 dev_err(dev, "Unable to register clock notifier\n"); 1130 goto err_devclk_disable; 1131 } 1132 1133 ret = drm_dev_register(drm, 0); 1134 if (ret) { 1135 dev_err(dev, "Failed to register DRM driver\n"); 1136 goto err_clk_notifier_unregister; 1137 } 1138 1139 drm_fbdev_generic_setup(drm, 32); 1140 1141 return 0; 1142 1143 err_clk_notifier_unregister: 1144 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1145 err_devclk_disable: 1146 if (priv->lcd_clk) 1147 clk_disable_unprepare(priv->lcd_clk); 1148 err_pixclk_disable: 1149 clk_disable_unprepare(priv->pix_clk); 1150 return ret; 1151 } 1152 1153 static int ingenic_drm_bind_with_components(struct device *dev) 1154 { 1155 return ingenic_drm_bind(dev, true); 1156 } 1157 1158 static int compare_of(struct device *dev, void *data) 1159 { 1160 return dev->of_node == data; 1161 } 1162 1163 static void ingenic_drm_unbind(struct device *dev) 1164 { 1165 struct ingenic_drm *priv = dev_get_drvdata(dev); 1166 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1167 1168 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1169 if (priv->lcd_clk) 1170 clk_disable_unprepare(priv->lcd_clk); 1171 clk_disable_unprepare(priv->pix_clk); 1172 1173 drm_dev_unregister(&priv->drm); 1174 drm_atomic_helper_shutdown(&priv->drm); 1175 } 1176 1177 static const struct component_master_ops ingenic_master_ops = { 1178 .bind = ingenic_drm_bind_with_components, 1179 .unbind = ingenic_drm_unbind, 1180 }; 1181 1182 static int ingenic_drm_probe(struct platform_device *pdev) 1183 { 1184 struct device *dev = &pdev->dev; 1185 struct component_match *match = NULL; 1186 struct device_node *np; 1187 1188 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1189 return ingenic_drm_bind(dev, false); 1190 1191 /* IPU is at port address 8 */ 1192 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1193 if (!np) 1194 return ingenic_drm_bind(dev, false); 1195 1196 drm_of_component_match_add(dev, &match, compare_of, np); 1197 of_node_put(np); 1198 1199 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1200 } 1201 1202 static int ingenic_drm_remove(struct platform_device *pdev) 1203 { 1204 struct device *dev = &pdev->dev; 1205 1206 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1207 ingenic_drm_unbind(dev); 1208 else 1209 component_master_del(dev, &ingenic_master_ops); 1210 1211 return 0; 1212 } 1213 1214 static int __maybe_unused ingenic_drm_suspend(struct device *dev) 1215 { 1216 struct ingenic_drm *priv = dev_get_drvdata(dev); 1217 1218 return drm_mode_config_helper_suspend(&priv->drm); 1219 } 1220 1221 static int __maybe_unused ingenic_drm_resume(struct device *dev) 1222 { 1223 struct ingenic_drm *priv = dev_get_drvdata(dev); 1224 1225 return drm_mode_config_helper_resume(&priv->drm); 1226 } 1227 1228 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume); 1229 1230 static const u32 jz4740_formats[] = { 1231 DRM_FORMAT_XRGB1555, 1232 DRM_FORMAT_RGB565, 1233 DRM_FORMAT_XRGB8888, 1234 }; 1235 1236 static const u32 jz4725b_formats_f1[] = { 1237 DRM_FORMAT_XRGB1555, 1238 DRM_FORMAT_RGB565, 1239 DRM_FORMAT_XRGB8888, 1240 }; 1241 1242 static const u32 jz4725b_formats_f0[] = { 1243 DRM_FORMAT_C8, 1244 DRM_FORMAT_XRGB1555, 1245 DRM_FORMAT_RGB565, 1246 DRM_FORMAT_XRGB8888, 1247 }; 1248 1249 static const u32 jz4770_formats_f1[] = { 1250 DRM_FORMAT_XRGB1555, 1251 DRM_FORMAT_RGB565, 1252 DRM_FORMAT_RGB888, 1253 DRM_FORMAT_XRGB8888, 1254 DRM_FORMAT_XRGB2101010, 1255 }; 1256 1257 static const u32 jz4770_formats_f0[] = { 1258 DRM_FORMAT_C8, 1259 DRM_FORMAT_XRGB1555, 1260 DRM_FORMAT_RGB565, 1261 DRM_FORMAT_RGB888, 1262 DRM_FORMAT_XRGB8888, 1263 DRM_FORMAT_XRGB2101010, 1264 }; 1265 1266 static const struct jz_soc_info jz4740_soc_info = { 1267 .needs_dev_clk = true, 1268 .has_osd = false, 1269 .map_noncoherent = false, 1270 .max_width = 800, 1271 .max_height = 600, 1272 .formats_f1 = jz4740_formats, 1273 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1274 /* JZ4740 has only one plane */ 1275 }; 1276 1277 static const struct jz_soc_info jz4725b_soc_info = { 1278 .needs_dev_clk = false, 1279 .has_osd = true, 1280 .map_noncoherent = false, 1281 .max_width = 800, 1282 .max_height = 600, 1283 .formats_f1 = jz4725b_formats_f1, 1284 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1285 .formats_f0 = jz4725b_formats_f0, 1286 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1287 }; 1288 1289 static const struct jz_soc_info jz4770_soc_info = { 1290 .needs_dev_clk = false, 1291 .has_osd = true, 1292 .map_noncoherent = true, 1293 .max_width = 1280, 1294 .max_height = 720, 1295 .formats_f1 = jz4770_formats_f1, 1296 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1297 .formats_f0 = jz4770_formats_f0, 1298 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1299 }; 1300 1301 static const struct of_device_id ingenic_drm_of_match[] = { 1302 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1303 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1304 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1305 { /* sentinel */ }, 1306 }; 1307 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1308 1309 static struct platform_driver ingenic_drm_driver = { 1310 .driver = { 1311 .name = "ingenic-drm", 1312 .pm = pm_ptr(&ingenic_drm_pm_ops), 1313 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1314 }, 1315 .probe = ingenic_drm_probe, 1316 .remove = ingenic_drm_remove, 1317 }; 1318 1319 static int ingenic_drm_init(void) 1320 { 1321 int err; 1322 1323 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1324 err = platform_driver_register(ingenic_ipu_driver_ptr); 1325 if (err) 1326 return err; 1327 } 1328 1329 return platform_driver_register(&ingenic_drm_driver); 1330 } 1331 module_init(ingenic_drm_init); 1332 1333 static void ingenic_drm_exit(void) 1334 { 1335 platform_driver_unregister(&ingenic_drm_driver); 1336 1337 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1338 platform_driver_unregister(ingenic_ipu_driver_ptr); 1339 } 1340 module_exit(ingenic_drm_exit); 1341 1342 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1343 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1344 MODULE_LICENSE("GPL v2"); 1345