1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/component.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of_device.h> 16 #include <linux/of_reserved_mem.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/regmap.h> 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_color_mgmt.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_crtc_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_drv.h> 29 #include <drm/drm_encoder.h> 30 #include <drm/drm_gem_cma_helper.h> 31 #include <drm/drm_fb_cma_helper.h> 32 #include <drm/drm_fb_helper.h> 33 #include <drm/drm_fourcc.h> 34 #include <drm/drm_gem_atomic_helper.h> 35 #include <drm/drm_gem_framebuffer_helper.h> 36 #include <drm/drm_irq.h> 37 #include <drm/drm_managed.h> 38 #include <drm/drm_of.h> 39 #include <drm/drm_panel.h> 40 #include <drm/drm_plane.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_vblank.h> 44 45 struct ingenic_dma_hwdesc { 46 u32 next; 47 u32 addr; 48 u32 id; 49 u32 cmd; 50 } __aligned(16); 51 52 struct ingenic_dma_hwdescs { 53 struct ingenic_dma_hwdesc hwdesc_f0; 54 struct ingenic_dma_hwdesc hwdesc_f1; 55 struct ingenic_dma_hwdesc hwdesc_pal; 56 u16 palette[256] __aligned(16); 57 }; 58 59 struct jz_soc_info { 60 bool needs_dev_clk; 61 bool has_osd; 62 bool map_noncoherent; 63 unsigned int max_width, max_height; 64 const u32 *formats_f0, *formats_f1; 65 unsigned int num_formats_f0, num_formats_f1; 66 }; 67 68 struct ingenic_drm { 69 struct drm_device drm; 70 /* 71 * f1 (aka. foreground1) is our primary plane, on top of which 72 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 73 * hardware and cannot be changed. 74 */ 75 struct drm_plane f0, f1, *ipu_plane; 76 struct drm_crtc crtc; 77 78 struct device *dev; 79 struct regmap *map; 80 struct clk *lcd_clk, *pix_clk; 81 const struct jz_soc_info *soc_info; 82 83 struct ingenic_dma_hwdescs *dma_hwdescs; 84 dma_addr_t dma_hwdescs_phys; 85 86 bool panel_is_sharp; 87 bool no_vblank; 88 89 /* 90 * clk_mutex is used to synchronize the pixel clock rate update with 91 * the VBLANK. When the pixel clock's parent clock needs to be updated, 92 * clock_nb's notifier function will lock the mutex, then wait until the 93 * next VBLANK. At that point, the parent clock's rate can be updated, 94 * and the mutex is then unlocked. If an atomic commit happens in the 95 * meantime, it will lock on the mutex, effectively waiting until the 96 * clock update process finishes. Finally, the pixel clock's rate will 97 * be recomputed when the mutex has been released, in the pending atomic 98 * commit, or a future one. 99 */ 100 struct mutex clk_mutex; 101 bool update_clk_rate; 102 struct notifier_block clock_nb; 103 }; 104 105 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 106 { 107 switch (reg) { 108 case JZ_REG_LCD_IID: 109 case JZ_REG_LCD_SA0: 110 case JZ_REG_LCD_FID0: 111 case JZ_REG_LCD_CMD0: 112 case JZ_REG_LCD_SA1: 113 case JZ_REG_LCD_FID1: 114 case JZ_REG_LCD_CMD1: 115 return false; 116 default: 117 return true; 118 } 119 } 120 121 static const struct regmap_config ingenic_drm_regmap_config = { 122 .reg_bits = 32, 123 .val_bits = 32, 124 .reg_stride = 4, 125 126 .max_register = JZ_REG_LCD_SIZE1, 127 .writeable_reg = ingenic_drm_writeable_reg, 128 }; 129 130 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 131 { 132 return container_of(drm, struct ingenic_drm, drm); 133 } 134 135 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 136 { 137 return container_of(crtc, struct ingenic_drm, crtc); 138 } 139 140 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 141 { 142 return container_of(nb, struct ingenic_drm, clock_nb); 143 } 144 145 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 146 unsigned long action, 147 void *data) 148 { 149 struct ingenic_drm *priv = drm_nb_get_priv(nb); 150 151 switch (action) { 152 case PRE_RATE_CHANGE: 153 mutex_lock(&priv->clk_mutex); 154 priv->update_clk_rate = true; 155 drm_crtc_wait_one_vblank(&priv->crtc); 156 return NOTIFY_OK; 157 default: 158 mutex_unlock(&priv->clk_mutex); 159 return NOTIFY_OK; 160 } 161 } 162 163 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 164 struct drm_atomic_state *state) 165 { 166 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 167 168 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 169 170 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 171 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 172 JZ_LCD_CTRL_ENABLE); 173 174 drm_crtc_vblank_on(crtc); 175 } 176 177 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 178 struct drm_atomic_state *state) 179 { 180 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 181 unsigned int var; 182 183 drm_crtc_vblank_off(crtc); 184 185 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 186 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 187 188 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 189 var & JZ_LCD_STATE_DISABLED, 190 1000, 0); 191 } 192 193 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 194 struct drm_display_mode *mode) 195 { 196 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 197 198 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start; 199 vds = mode->crtc_vtotal - mode->crtc_vsync_start; 200 vde = vds + mode->crtc_vdisplay; 201 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay; 202 203 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start; 204 hds = mode->crtc_htotal - mode->crtc_hsync_start; 205 hde = hds + mode->crtc_hdisplay; 206 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay; 207 208 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 209 0 << JZ_LCD_VSYNC_VPS_OFFSET | 210 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 211 212 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 213 0 << JZ_LCD_HSYNC_HPS_OFFSET | 214 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 215 216 regmap_write(priv->map, JZ_REG_LCD_VAT, 217 ht << JZ_LCD_VAT_HT_OFFSET | 218 vt << JZ_LCD_VAT_VT_OFFSET); 219 220 regmap_write(priv->map, JZ_REG_LCD_DAH, 221 hds << JZ_LCD_DAH_HDS_OFFSET | 222 hde << JZ_LCD_DAH_HDE_OFFSET); 223 regmap_write(priv->map, JZ_REG_LCD_DAV, 224 vds << JZ_LCD_DAV_VDS_OFFSET | 225 vde << JZ_LCD_DAV_VDE_OFFSET); 226 227 if (priv->panel_is_sharp) { 228 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 229 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 230 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 231 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 232 } 233 234 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 235 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 236 237 /* 238 * IPU restart - specify how much time the LCDC will wait before 239 * transferring a new frame from the IPU. The value is the one 240 * suggested in the programming manual. 241 */ 242 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 243 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 244 } 245 246 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 247 struct drm_atomic_state *state) 248 { 249 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 250 crtc); 251 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 252 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 253 254 if (crtc_state->gamma_lut && 255 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 256 dev_dbg(priv->dev, "Invalid palette size\n"); 257 return -EINVAL; 258 } 259 260 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 261 f1_state = drm_atomic_get_plane_state(crtc_state->state, 262 &priv->f1); 263 if (IS_ERR(f1_state)) 264 return PTR_ERR(f1_state); 265 266 f0_state = drm_atomic_get_plane_state(crtc_state->state, 267 &priv->f0); 268 if (IS_ERR(f0_state)) 269 return PTR_ERR(f0_state); 270 271 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 272 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 273 priv->ipu_plane); 274 if (IS_ERR(ipu_state)) 275 return PTR_ERR(ipu_state); 276 277 /* IPU and F1 planes cannot be enabled at the same time. */ 278 if (f1_state->fb && ipu_state->fb) { 279 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 280 return -EINVAL; 281 } 282 } 283 284 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 285 priv->no_vblank = !f1_state->fb && !f0_state->fb && 286 !(ipu_state && ipu_state->fb); 287 } 288 289 return 0; 290 } 291 292 static enum drm_mode_status 293 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 294 { 295 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 296 long rate; 297 298 if (mode->hdisplay > priv->soc_info->max_width) 299 return MODE_BAD_HVALUE; 300 if (mode->vdisplay > priv->soc_info->max_height) 301 return MODE_BAD_VVALUE; 302 303 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 304 if (rate < 0) 305 return MODE_CLOCK_RANGE; 306 307 return MODE_OK; 308 } 309 310 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 311 struct drm_atomic_state *state) 312 { 313 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 314 crtc); 315 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 316 u32 ctrl = 0; 317 318 if (priv->soc_info->has_osd && 319 drm_atomic_crtc_needs_modeset(crtc_state)) { 320 /* 321 * If IPU plane is enabled, enable IPU as source for the F1 322 * plane; otherwise use regular DMA. 323 */ 324 if (priv->ipu_plane && priv->ipu_plane->state->fb) 325 ctrl |= JZ_LCD_OSDCTRL_IPU; 326 327 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 328 JZ_LCD_OSDCTRL_IPU, ctrl); 329 } 330 } 331 332 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 333 struct drm_atomic_state *state) 334 { 335 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 336 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 337 crtc); 338 struct drm_pending_vblank_event *event = crtc_state->event; 339 340 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 341 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode); 342 priv->update_clk_rate = true; 343 } 344 345 if (priv->update_clk_rate) { 346 mutex_lock(&priv->clk_mutex); 347 clk_set_rate(priv->pix_clk, 348 crtc_state->adjusted_mode.crtc_clock * 1000); 349 priv->update_clk_rate = false; 350 mutex_unlock(&priv->clk_mutex); 351 } 352 353 if (event) { 354 crtc_state->event = NULL; 355 356 spin_lock_irq(&crtc->dev->event_lock); 357 if (drm_crtc_vblank_get(crtc) == 0) 358 drm_crtc_arm_vblank_event(crtc, event); 359 else 360 drm_crtc_send_vblank_event(crtc, event); 361 spin_unlock_irq(&crtc->dev->event_lock); 362 } 363 } 364 365 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 366 struct drm_atomic_state *state) 367 { 368 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 369 plane); 370 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 371 plane); 372 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 373 struct drm_crtc_state *crtc_state; 374 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 375 int ret; 376 377 if (!crtc) 378 return 0; 379 380 crtc_state = drm_atomic_get_existing_crtc_state(state, 381 crtc); 382 if (WARN_ON(!crtc_state)) 383 return -EINVAL; 384 385 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 386 DRM_PLANE_HELPER_NO_SCALING, 387 DRM_PLANE_HELPER_NO_SCALING, 388 priv->soc_info->has_osd, 389 true); 390 if (ret) 391 return ret; 392 393 /* 394 * If OSD is not available, check that the width/height match. 395 * Note that state->src_* are in 16.16 fixed-point format. 396 */ 397 if (!priv->soc_info->has_osd && 398 (new_plane_state->src_x != 0 || 399 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w || 400 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) 401 return -EINVAL; 402 403 /* 404 * Require full modeset if enabling or disabling a plane, or changing 405 * its position, size or depth. 406 */ 407 if (priv->soc_info->has_osd && 408 (!old_plane_state->fb || !new_plane_state->fb || 409 old_plane_state->crtc_x != new_plane_state->crtc_x || 410 old_plane_state->crtc_y != new_plane_state->crtc_y || 411 old_plane_state->crtc_w != new_plane_state->crtc_w || 412 old_plane_state->crtc_h != new_plane_state->crtc_h || 413 old_plane_state->fb->format->format != new_plane_state->fb->format->format)) 414 crtc_state->mode_changed = true; 415 416 if (priv->soc_info->map_noncoherent) 417 drm_atomic_helper_check_plane_damage(state, new_plane_state); 418 419 return 0; 420 } 421 422 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 423 struct drm_plane *plane) 424 { 425 unsigned int en_bit; 426 427 if (priv->soc_info->has_osd) { 428 if (plane != &priv->f0) 429 en_bit = JZ_LCD_OSDC_F1EN; 430 else 431 en_bit = JZ_LCD_OSDC_F0EN; 432 433 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 434 } 435 } 436 437 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 438 { 439 struct ingenic_drm *priv = dev_get_drvdata(dev); 440 unsigned int en_bit; 441 442 if (priv->soc_info->has_osd) { 443 if (plane != &priv->f0) 444 en_bit = JZ_LCD_OSDC_F1EN; 445 else 446 en_bit = JZ_LCD_OSDC_F0EN; 447 448 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 449 } 450 } 451 452 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 453 struct drm_atomic_state *state) 454 { 455 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 456 457 ingenic_drm_plane_disable(priv->dev, plane); 458 } 459 460 void ingenic_drm_plane_config(struct device *dev, 461 struct drm_plane *plane, u32 fourcc) 462 { 463 struct ingenic_drm *priv = dev_get_drvdata(dev); 464 struct drm_plane_state *state = plane->state; 465 unsigned int xy_reg, size_reg; 466 unsigned int ctrl = 0; 467 468 ingenic_drm_plane_enable(priv, plane); 469 470 if (priv->soc_info->has_osd && plane != &priv->f0) { 471 switch (fourcc) { 472 case DRM_FORMAT_XRGB1555: 473 ctrl |= JZ_LCD_OSDCTRL_RGB555; 474 fallthrough; 475 case DRM_FORMAT_RGB565: 476 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 477 break; 478 case DRM_FORMAT_RGB888: 479 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 480 break; 481 case DRM_FORMAT_XRGB8888: 482 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 483 break; 484 case DRM_FORMAT_XRGB2101010: 485 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 486 break; 487 } 488 489 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 490 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 491 } else { 492 switch (fourcc) { 493 case DRM_FORMAT_C8: 494 ctrl |= JZ_LCD_CTRL_BPP_8; 495 break; 496 case DRM_FORMAT_XRGB1555: 497 ctrl |= JZ_LCD_CTRL_RGB555; 498 fallthrough; 499 case DRM_FORMAT_RGB565: 500 ctrl |= JZ_LCD_CTRL_BPP_15_16; 501 break; 502 case DRM_FORMAT_RGB888: 503 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 504 break; 505 case DRM_FORMAT_XRGB8888: 506 ctrl |= JZ_LCD_CTRL_BPP_18_24; 507 break; 508 case DRM_FORMAT_XRGB2101010: 509 ctrl |= JZ_LCD_CTRL_BPP_30; 510 break; 511 } 512 513 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 514 JZ_LCD_CTRL_BPP_MASK, ctrl); 515 } 516 517 if (priv->soc_info->has_osd) { 518 if (plane != &priv->f0) { 519 xy_reg = JZ_REG_LCD_XYP1; 520 size_reg = JZ_REG_LCD_SIZE1; 521 } else { 522 xy_reg = JZ_REG_LCD_XYP0; 523 size_reg = JZ_REG_LCD_SIZE0; 524 } 525 526 regmap_write(priv->map, xy_reg, 527 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 528 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 529 regmap_write(priv->map, size_reg, 530 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 531 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 532 } 533 } 534 535 bool ingenic_drm_map_noncoherent(const struct device *dev) 536 { 537 const struct ingenic_drm *priv = dev_get_drvdata(dev); 538 539 return priv->soc_info->map_noncoherent; 540 } 541 542 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 543 const struct drm_color_lut *lut) 544 { 545 unsigned int i; 546 547 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 548 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 549 | drm_color_lut_extract(lut[i].green, 6) << 5 550 | drm_color_lut_extract(lut[i].blue, 5); 551 552 priv->dma_hwdescs->palette[i] = color; 553 } 554 } 555 556 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 557 struct drm_atomic_state *state) 558 { 559 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 560 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); 561 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); 562 struct drm_crtc_state *crtc_state; 563 struct ingenic_dma_hwdesc *hwdesc; 564 unsigned int width, height, cpp, offset; 565 dma_addr_t addr; 566 u32 fourcc; 567 568 if (newstate && newstate->fb) { 569 if (priv->soc_info->map_noncoherent) 570 drm_fb_cma_sync_non_coherent(&priv->drm, oldstate, newstate); 571 572 crtc_state = newstate->crtc->state; 573 574 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0); 575 width = newstate->src_w >> 16; 576 height = newstate->src_h >> 16; 577 cpp = newstate->fb->format->cpp[0]; 578 579 if (!priv->soc_info->has_osd || plane == &priv->f0) 580 hwdesc = &priv->dma_hwdescs->hwdesc_f0; 581 else 582 hwdesc = &priv->dma_hwdescs->hwdesc_f1; 583 584 hwdesc->addr = addr; 585 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 586 587 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 588 fourcc = newstate->fb->format->format; 589 590 ingenic_drm_plane_config(priv->dev, plane, fourcc); 591 592 if (fourcc == DRM_FORMAT_C8) 593 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_pal); 594 else 595 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 596 597 priv->dma_hwdescs->hwdesc_f0.next = priv->dma_hwdescs_phys + offset; 598 599 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 600 } 601 602 if (crtc_state->color_mgmt_changed) 603 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 604 } 605 } 606 607 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 608 struct drm_crtc_state *crtc_state, 609 struct drm_connector_state *conn_state) 610 { 611 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 612 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 613 struct drm_connector *conn = conn_state->connector; 614 struct drm_display_info *info = &conn->display_info; 615 unsigned int cfg, rgbcfg = 0; 616 617 priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS; 618 619 if (priv->panel_is_sharp) { 620 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 621 } else { 622 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 623 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 624 } 625 626 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 627 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 628 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 629 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 630 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 631 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 632 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 633 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 634 635 if (!priv->panel_is_sharp) { 636 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) { 637 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 638 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 639 else 640 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 641 } else { 642 switch (*info->bus_formats) { 643 case MEDIA_BUS_FMT_RGB565_1X16: 644 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 645 break; 646 case MEDIA_BUS_FMT_RGB666_1X18: 647 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 648 break; 649 case MEDIA_BUS_FMT_RGB888_1X24: 650 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 651 break; 652 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 653 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; 654 fallthrough; 655 case MEDIA_BUS_FMT_RGB888_3X8: 656 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 657 break; 658 default: 659 break; 660 } 661 } 662 } 663 664 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 665 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); 666 } 667 668 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, 669 struct drm_crtc_state *crtc_state, 670 struct drm_connector_state *conn_state) 671 { 672 struct drm_display_info *info = &conn_state->connector->display_info; 673 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 674 675 if (info->num_bus_formats != 1) 676 return -EINVAL; 677 678 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 679 return 0; 680 681 switch (*info->bus_formats) { 682 case MEDIA_BUS_FMT_RGB888_3X8: 683 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 684 /* 685 * The LCD controller expects timing values in dot-clock ticks, 686 * which is 3x the timing values in pixels when using a 3x8-bit 687 * display; but it will count the display area size in pixels 688 * either way. Go figure. 689 */ 690 mode->crtc_clock = mode->clock * 3; 691 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2; 692 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2; 693 mode->crtc_hdisplay = mode->hdisplay; 694 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2; 695 return 0; 696 case MEDIA_BUS_FMT_RGB565_1X16: 697 case MEDIA_BUS_FMT_RGB666_1X18: 698 case MEDIA_BUS_FMT_RGB888_1X24: 699 return 0; 700 default: 701 return -EINVAL; 702 } 703 } 704 705 static void ingenic_drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state) 706 { 707 /* 708 * Just your regular drm_atomic_helper_commit_tail(), but only calls 709 * drm_atomic_helper_wait_for_vblanks() if priv->no_vblank. 710 */ 711 struct drm_device *dev = old_state->dev; 712 struct ingenic_drm *priv = drm_device_get_priv(dev); 713 714 drm_atomic_helper_commit_modeset_disables(dev, old_state); 715 716 drm_atomic_helper_commit_planes(dev, old_state, 0); 717 718 drm_atomic_helper_commit_modeset_enables(dev, old_state); 719 720 drm_atomic_helper_commit_hw_done(old_state); 721 722 if (!priv->no_vblank) 723 drm_atomic_helper_wait_for_vblanks(dev, old_state); 724 725 drm_atomic_helper_cleanup_planes(dev, old_state); 726 } 727 728 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 729 { 730 struct ingenic_drm *priv = drm_device_get_priv(arg); 731 unsigned int state; 732 733 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 734 735 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 736 JZ_LCD_STATE_EOF_IRQ, 0); 737 738 if (state & JZ_LCD_STATE_EOF_IRQ) 739 drm_crtc_handle_vblank(&priv->crtc); 740 741 return IRQ_HANDLED; 742 } 743 744 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 745 { 746 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 747 748 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 749 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 750 751 return 0; 752 } 753 754 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 755 { 756 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 757 758 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 759 } 760 761 static struct drm_framebuffer * 762 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, 763 const struct drm_mode_fb_cmd2 *mode_cmd) 764 { 765 struct ingenic_drm *priv = drm_device_get_priv(drm); 766 767 if (priv->soc_info->map_noncoherent) 768 return drm_gem_fb_create_with_dirty(drm, file, mode_cmd); 769 770 return drm_gem_fb_create(drm, file, mode_cmd); 771 } 772 773 static struct drm_gem_object * 774 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size) 775 { 776 struct ingenic_drm *priv = drm_device_get_priv(drm); 777 struct drm_gem_cma_object *obj; 778 779 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 780 if (!obj) 781 return ERR_PTR(-ENOMEM); 782 783 obj->map_noncoherent = priv->soc_info->map_noncoherent; 784 785 return &obj->base; 786 } 787 788 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 789 790 static const struct drm_driver ingenic_drm_driver_data = { 791 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 792 .name = "ingenic-drm", 793 .desc = "DRM module for Ingenic SoCs", 794 .date = "20200716", 795 .major = 1, 796 .minor = 1, 797 .patchlevel = 0, 798 799 .fops = &ingenic_drm_fops, 800 .gem_create_object = ingenic_drm_gem_create_object, 801 DRM_GEM_CMA_DRIVER_OPS, 802 803 .irq_handler = ingenic_drm_irq_handler, 804 }; 805 806 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 807 .update_plane = drm_atomic_helper_update_plane, 808 .disable_plane = drm_atomic_helper_disable_plane, 809 .reset = drm_atomic_helper_plane_reset, 810 .destroy = drm_plane_cleanup, 811 812 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 813 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 814 }; 815 816 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 817 .set_config = drm_atomic_helper_set_config, 818 .page_flip = drm_atomic_helper_page_flip, 819 .reset = drm_atomic_helper_crtc_reset, 820 .destroy = drm_crtc_cleanup, 821 822 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 823 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 824 825 .enable_vblank = ingenic_drm_enable_vblank, 826 .disable_vblank = ingenic_drm_disable_vblank, 827 }; 828 829 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 830 .atomic_update = ingenic_drm_plane_atomic_update, 831 .atomic_check = ingenic_drm_plane_atomic_check, 832 .atomic_disable = ingenic_drm_plane_atomic_disable, 833 .prepare_fb = drm_gem_plane_helper_prepare_fb, 834 }; 835 836 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 837 .atomic_enable = ingenic_drm_crtc_atomic_enable, 838 .atomic_disable = ingenic_drm_crtc_atomic_disable, 839 .atomic_begin = ingenic_drm_crtc_atomic_begin, 840 .atomic_flush = ingenic_drm_crtc_atomic_flush, 841 .atomic_check = ingenic_drm_crtc_atomic_check, 842 .mode_valid = ingenic_drm_crtc_mode_valid, 843 }; 844 845 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 846 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 847 .atomic_check = ingenic_drm_encoder_atomic_check, 848 }; 849 850 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 851 .fb_create = ingenic_drm_gem_fb_create, 852 .output_poll_changed = drm_fb_helper_output_poll_changed, 853 .atomic_check = drm_atomic_helper_check, 854 .atomic_commit = drm_atomic_helper_commit, 855 }; 856 857 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 858 .atomic_commit_tail = ingenic_drm_atomic_helper_commit_tail, 859 }; 860 861 static void ingenic_drm_unbind_all(void *d) 862 { 863 struct ingenic_drm *priv = d; 864 865 component_unbind_all(priv->dev, &priv->drm); 866 } 867 868 static void __maybe_unused ingenic_drm_release_rmem(void *d) 869 { 870 of_reserved_mem_device_release(d); 871 } 872 873 static int ingenic_drm_bind(struct device *dev, bool has_components) 874 { 875 struct platform_device *pdev = to_platform_device(dev); 876 const struct jz_soc_info *soc_info; 877 struct ingenic_drm *priv; 878 struct clk *parent_clk; 879 struct drm_plane *primary; 880 struct drm_bridge *bridge; 881 struct drm_panel *panel; 882 struct drm_encoder *encoder; 883 struct drm_device *drm; 884 void __iomem *base; 885 long parent_rate; 886 unsigned int i, clone_mask = 0; 887 dma_addr_t dma_hwdesc_phys_f0, dma_hwdesc_phys_f1; 888 int ret, irq; 889 890 soc_info = of_device_get_match_data(dev); 891 if (!soc_info) { 892 dev_err(dev, "Missing platform data\n"); 893 return -EINVAL; 894 } 895 896 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 897 ret = of_reserved_mem_device_init(dev); 898 899 if (ret && ret != -ENODEV) 900 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 901 902 if (!ret) { 903 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 904 if (ret) 905 return ret; 906 } 907 } 908 909 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 910 struct ingenic_drm, drm); 911 if (IS_ERR(priv)) 912 return PTR_ERR(priv); 913 914 priv->soc_info = soc_info; 915 priv->dev = dev; 916 drm = &priv->drm; 917 918 platform_set_drvdata(pdev, priv); 919 920 ret = drmm_mode_config_init(drm); 921 if (ret) 922 return ret; 923 924 drm->mode_config.min_width = 0; 925 drm->mode_config.min_height = 0; 926 drm->mode_config.max_width = soc_info->max_width; 927 drm->mode_config.max_height = 4095; 928 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 929 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 930 931 base = devm_platform_ioremap_resource(pdev, 0); 932 if (IS_ERR(base)) { 933 dev_err(dev, "Failed to get memory resource\n"); 934 return PTR_ERR(base); 935 } 936 937 priv->map = devm_regmap_init_mmio(dev, base, 938 &ingenic_drm_regmap_config); 939 if (IS_ERR(priv->map)) { 940 dev_err(dev, "Failed to create regmap\n"); 941 return PTR_ERR(priv->map); 942 } 943 944 irq = platform_get_irq(pdev, 0); 945 if (irq < 0) 946 return irq; 947 948 if (soc_info->needs_dev_clk) { 949 priv->lcd_clk = devm_clk_get(dev, "lcd"); 950 if (IS_ERR(priv->lcd_clk)) { 951 dev_err(dev, "Failed to get lcd clock\n"); 952 return PTR_ERR(priv->lcd_clk); 953 } 954 } 955 956 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 957 if (IS_ERR(priv->pix_clk)) { 958 dev_err(dev, "Failed to get pixel clock\n"); 959 return PTR_ERR(priv->pix_clk); 960 } 961 962 priv->dma_hwdescs = dmam_alloc_coherent(dev, 963 sizeof(*priv->dma_hwdescs), 964 &priv->dma_hwdescs_phys, 965 GFP_KERNEL); 966 if (!priv->dma_hwdescs) 967 return -ENOMEM; 968 969 970 /* Configure DMA hwdesc for foreground0 plane */ 971 dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys 972 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 973 priv->dma_hwdescs->hwdesc_f0.next = dma_hwdesc_phys_f0; 974 priv->dma_hwdescs->hwdesc_f0.id = 0xf0; 975 976 /* Configure DMA hwdesc for foreground1 plane */ 977 dma_hwdesc_phys_f1 = priv->dma_hwdescs_phys 978 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f1); 979 priv->dma_hwdescs->hwdesc_f1.next = dma_hwdesc_phys_f1; 980 priv->dma_hwdescs->hwdesc_f1.id = 0xf1; 981 982 /* Configure DMA hwdesc for palette */ 983 priv->dma_hwdescs->hwdesc_pal.next = priv->dma_hwdescs_phys 984 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 985 priv->dma_hwdescs->hwdesc_pal.id = 0xc0; 986 priv->dma_hwdescs->hwdesc_pal.addr = priv->dma_hwdescs_phys 987 + offsetof(struct ingenic_dma_hwdescs, palette); 988 priv->dma_hwdescs->hwdesc_pal.cmd = JZ_LCD_CMD_ENABLE_PAL 989 | (sizeof(priv->dma_hwdescs->palette) / 4); 990 991 if (soc_info->has_osd) 992 priv->ipu_plane = drm_plane_from_index(drm, 0); 993 994 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0; 995 996 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs); 997 998 ret = drm_universal_plane_init(drm, primary, 1, 999 &ingenic_drm_primary_plane_funcs, 1000 priv->soc_info->formats_f1, 1001 priv->soc_info->num_formats_f1, 1002 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1003 if (ret) { 1004 dev_err(dev, "Failed to register plane: %i\n", ret); 1005 return ret; 1006 } 1007 1008 if (soc_info->map_noncoherent) 1009 drm_plane_enable_fb_damage_clips(&priv->f1); 1010 1011 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 1012 1013 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary, 1014 NULL, &ingenic_drm_crtc_funcs, NULL); 1015 if (ret) { 1016 dev_err(dev, "Failed to init CRTC: %i\n", ret); 1017 return ret; 1018 } 1019 1020 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 1021 ARRAY_SIZE(priv->dma_hwdescs->palette)); 1022 1023 if (soc_info->has_osd) { 1024 drm_plane_helper_add(&priv->f0, 1025 &ingenic_drm_plane_helper_funcs); 1026 1027 ret = drm_universal_plane_init(drm, &priv->f0, 1, 1028 &ingenic_drm_primary_plane_funcs, 1029 priv->soc_info->formats_f0, 1030 priv->soc_info->num_formats_f0, 1031 NULL, DRM_PLANE_TYPE_OVERLAY, 1032 NULL); 1033 if (ret) { 1034 dev_err(dev, "Failed to register overlay plane: %i\n", 1035 ret); 1036 return ret; 1037 } 1038 1039 if (soc_info->map_noncoherent) 1040 drm_plane_enable_fb_damage_clips(&priv->f0); 1041 1042 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 1043 ret = component_bind_all(dev, drm); 1044 if (ret) { 1045 if (ret != -EPROBE_DEFER) 1046 dev_err(dev, "Failed to bind components: %i\n", ret); 1047 return ret; 1048 } 1049 1050 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 1051 if (ret) 1052 return ret; 1053 1054 priv->ipu_plane = drm_plane_from_index(drm, 2); 1055 if (!priv->ipu_plane) { 1056 dev_err(dev, "Failed to retrieve IPU plane\n"); 1057 return -EINVAL; 1058 } 1059 } 1060 } 1061 1062 for (i = 0; ; i++) { 1063 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 1064 if (ret) { 1065 if (ret == -ENODEV) 1066 break; /* we're done */ 1067 if (ret != -EPROBE_DEFER) 1068 dev_err(dev, "Failed to get bridge handle\n"); 1069 return ret; 1070 } 1071 1072 if (panel) 1073 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 1074 DRM_MODE_CONNECTOR_DPI); 1075 1076 encoder = drmm_plain_encoder_alloc(drm, NULL, DRM_MODE_ENCODER_DPI, NULL); 1077 if (IS_ERR(encoder)) { 1078 ret = PTR_ERR(encoder); 1079 dev_err(dev, "Failed to init encoder: %d\n", ret); 1080 return ret; 1081 } 1082 1083 encoder->possible_crtcs = 1; 1084 1085 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1086 1087 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1088 if (ret) { 1089 dev_err(dev, "Unable to attach bridge\n"); 1090 return ret; 1091 } 1092 } 1093 1094 drm_for_each_encoder(encoder, drm) { 1095 clone_mask |= BIT(drm_encoder_index(encoder)); 1096 } 1097 1098 drm_for_each_encoder(encoder, drm) { 1099 encoder->possible_clones = clone_mask; 1100 } 1101 1102 ret = drm_irq_install(drm, irq); 1103 if (ret) { 1104 dev_err(dev, "Unable to install IRQ handler\n"); 1105 return ret; 1106 } 1107 1108 ret = drm_vblank_init(drm, 1); 1109 if (ret) { 1110 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1111 return ret; 1112 } 1113 1114 drm_mode_config_reset(drm); 1115 1116 ret = clk_prepare_enable(priv->pix_clk); 1117 if (ret) { 1118 dev_err(dev, "Unable to start pixel clock\n"); 1119 return ret; 1120 } 1121 1122 if (priv->lcd_clk) { 1123 parent_clk = clk_get_parent(priv->lcd_clk); 1124 parent_rate = clk_get_rate(parent_clk); 1125 1126 /* LCD Device clock must be 3x the pixel clock for STN panels, 1127 * or 1.5x the pixel clock for TFT panels. To avoid having to 1128 * check for the LCD device clock everytime we do a mode change, 1129 * we set the LCD device clock to the highest rate possible. 1130 */ 1131 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1132 if (ret) { 1133 dev_err(dev, "Unable to set LCD clock rate\n"); 1134 goto err_pixclk_disable; 1135 } 1136 1137 ret = clk_prepare_enable(priv->lcd_clk); 1138 if (ret) { 1139 dev_err(dev, "Unable to start lcd clock\n"); 1140 goto err_pixclk_disable; 1141 } 1142 } 1143 1144 /* Set address of our DMA descriptor chain */ 1145 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0); 1146 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1); 1147 1148 /* Enable OSD if available */ 1149 if (soc_info->has_osd) 1150 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); 1151 1152 mutex_init(&priv->clk_mutex); 1153 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1154 1155 parent_clk = clk_get_parent(priv->pix_clk); 1156 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1157 if (ret) { 1158 dev_err(dev, "Unable to register clock notifier\n"); 1159 goto err_devclk_disable; 1160 } 1161 1162 ret = drm_dev_register(drm, 0); 1163 if (ret) { 1164 dev_err(dev, "Failed to register DRM driver\n"); 1165 goto err_clk_notifier_unregister; 1166 } 1167 1168 drm_fbdev_generic_setup(drm, 32); 1169 1170 return 0; 1171 1172 err_clk_notifier_unregister: 1173 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1174 err_devclk_disable: 1175 if (priv->lcd_clk) 1176 clk_disable_unprepare(priv->lcd_clk); 1177 err_pixclk_disable: 1178 clk_disable_unprepare(priv->pix_clk); 1179 return ret; 1180 } 1181 1182 static int ingenic_drm_bind_with_components(struct device *dev) 1183 { 1184 return ingenic_drm_bind(dev, true); 1185 } 1186 1187 static int compare_of(struct device *dev, void *data) 1188 { 1189 return dev->of_node == data; 1190 } 1191 1192 static void ingenic_drm_unbind(struct device *dev) 1193 { 1194 struct ingenic_drm *priv = dev_get_drvdata(dev); 1195 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1196 1197 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1198 if (priv->lcd_clk) 1199 clk_disable_unprepare(priv->lcd_clk); 1200 clk_disable_unprepare(priv->pix_clk); 1201 1202 drm_dev_unregister(&priv->drm); 1203 drm_atomic_helper_shutdown(&priv->drm); 1204 } 1205 1206 static const struct component_master_ops ingenic_master_ops = { 1207 .bind = ingenic_drm_bind_with_components, 1208 .unbind = ingenic_drm_unbind, 1209 }; 1210 1211 static int ingenic_drm_probe(struct platform_device *pdev) 1212 { 1213 struct device *dev = &pdev->dev; 1214 struct component_match *match = NULL; 1215 struct device_node *np; 1216 1217 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1218 return ingenic_drm_bind(dev, false); 1219 1220 /* IPU is at port address 8 */ 1221 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1222 if (!np) 1223 return ingenic_drm_bind(dev, false); 1224 1225 drm_of_component_match_add(dev, &match, compare_of, np); 1226 of_node_put(np); 1227 1228 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1229 } 1230 1231 static int ingenic_drm_remove(struct platform_device *pdev) 1232 { 1233 struct device *dev = &pdev->dev; 1234 1235 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1236 ingenic_drm_unbind(dev); 1237 else 1238 component_master_del(dev, &ingenic_master_ops); 1239 1240 return 0; 1241 } 1242 1243 static int __maybe_unused ingenic_drm_suspend(struct device *dev) 1244 { 1245 struct ingenic_drm *priv = dev_get_drvdata(dev); 1246 1247 return drm_mode_config_helper_suspend(&priv->drm); 1248 } 1249 1250 static int __maybe_unused ingenic_drm_resume(struct device *dev) 1251 { 1252 struct ingenic_drm *priv = dev_get_drvdata(dev); 1253 1254 return drm_mode_config_helper_resume(&priv->drm); 1255 } 1256 1257 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume); 1258 1259 static const u32 jz4740_formats[] = { 1260 DRM_FORMAT_XRGB1555, 1261 DRM_FORMAT_RGB565, 1262 DRM_FORMAT_XRGB8888, 1263 }; 1264 1265 static const u32 jz4725b_formats_f1[] = { 1266 DRM_FORMAT_XRGB1555, 1267 DRM_FORMAT_RGB565, 1268 DRM_FORMAT_XRGB8888, 1269 }; 1270 1271 static const u32 jz4725b_formats_f0[] = { 1272 DRM_FORMAT_C8, 1273 DRM_FORMAT_XRGB1555, 1274 DRM_FORMAT_RGB565, 1275 DRM_FORMAT_XRGB8888, 1276 }; 1277 1278 static const u32 jz4770_formats_f1[] = { 1279 DRM_FORMAT_XRGB1555, 1280 DRM_FORMAT_RGB565, 1281 DRM_FORMAT_RGB888, 1282 DRM_FORMAT_XRGB8888, 1283 DRM_FORMAT_XRGB2101010, 1284 }; 1285 1286 static const u32 jz4770_formats_f0[] = { 1287 DRM_FORMAT_C8, 1288 DRM_FORMAT_XRGB1555, 1289 DRM_FORMAT_RGB565, 1290 DRM_FORMAT_RGB888, 1291 DRM_FORMAT_XRGB8888, 1292 DRM_FORMAT_XRGB2101010, 1293 }; 1294 1295 static const struct jz_soc_info jz4740_soc_info = { 1296 .needs_dev_clk = true, 1297 .has_osd = false, 1298 .map_noncoherent = false, 1299 .max_width = 800, 1300 .max_height = 600, 1301 .formats_f1 = jz4740_formats, 1302 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1303 /* JZ4740 has only one plane */ 1304 }; 1305 1306 static const struct jz_soc_info jz4725b_soc_info = { 1307 .needs_dev_clk = false, 1308 .has_osd = true, 1309 .map_noncoherent = false, 1310 .max_width = 800, 1311 .max_height = 600, 1312 .formats_f1 = jz4725b_formats_f1, 1313 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1314 .formats_f0 = jz4725b_formats_f0, 1315 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1316 }; 1317 1318 static const struct jz_soc_info jz4770_soc_info = { 1319 .needs_dev_clk = false, 1320 .has_osd = true, 1321 .map_noncoherent = true, 1322 .max_width = 1280, 1323 .max_height = 720, 1324 .formats_f1 = jz4770_formats_f1, 1325 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1326 .formats_f0 = jz4770_formats_f0, 1327 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1328 }; 1329 1330 static const struct of_device_id ingenic_drm_of_match[] = { 1331 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1332 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1333 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1334 { /* sentinel */ }, 1335 }; 1336 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1337 1338 static struct platform_driver ingenic_drm_driver = { 1339 .driver = { 1340 .name = "ingenic-drm", 1341 .pm = pm_ptr(&ingenic_drm_pm_ops), 1342 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1343 }, 1344 .probe = ingenic_drm_probe, 1345 .remove = ingenic_drm_remove, 1346 }; 1347 1348 static int ingenic_drm_init(void) 1349 { 1350 int err; 1351 1352 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1353 err = platform_driver_register(ingenic_ipu_driver_ptr); 1354 if (err) 1355 return err; 1356 } 1357 1358 return platform_driver_register(&ingenic_drm_driver); 1359 } 1360 module_init(ingenic_drm_init); 1361 1362 static void ingenic_drm_exit(void) 1363 { 1364 platform_driver_unregister(&ingenic_drm_driver); 1365 1366 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1367 platform_driver_unregister(ingenic_ipu_driver_ptr); 1368 } 1369 module_exit(ingenic_drm_exit); 1370 1371 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1372 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1373 MODULE_LICENSE("GPL v2"); 1374