1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/component.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of_device.h> 15 #include <linux/of_reserved_mem.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_bridge.h> 22 #include <drm/drm_color_mgmt.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_drv.h> 26 #include <drm/drm_gem_cma_helper.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_fb_helper.h> 29 #include <drm/drm_fourcc.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_irq.h> 32 #include <drm/drm_managed.h> 33 #include <drm/drm_of.h> 34 #include <drm/drm_panel.h> 35 #include <drm/drm_plane.h> 36 #include <drm/drm_plane_helper.h> 37 #include <drm/drm_probe_helper.h> 38 #include <drm/drm_simple_kms_helper.h> 39 #include <drm/drm_vblank.h> 40 41 struct ingenic_dma_hwdesc { 42 u32 next; 43 u32 addr; 44 u32 id; 45 u32 cmd; 46 } __aligned(16); 47 48 struct ingenic_dma_hwdescs { 49 struct ingenic_dma_hwdesc hwdesc_f0; 50 struct ingenic_dma_hwdesc hwdesc_f1; 51 struct ingenic_dma_hwdesc hwdesc_pal; 52 u16 palette[256] __aligned(16); 53 }; 54 55 struct jz_soc_info { 56 bool needs_dev_clk; 57 bool has_osd; 58 unsigned int max_width, max_height; 59 const u32 *formats_f0, *formats_f1; 60 unsigned int num_formats_f0, num_formats_f1; 61 }; 62 63 struct ingenic_drm { 64 struct drm_device drm; 65 /* 66 * f1 (aka. foreground1) is our primary plane, on top of which 67 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 68 * hardware and cannot be changed. 69 */ 70 struct drm_plane f0, f1, *ipu_plane; 71 struct drm_crtc crtc; 72 73 struct device *dev; 74 struct regmap *map; 75 struct clk *lcd_clk, *pix_clk; 76 const struct jz_soc_info *soc_info; 77 78 struct ingenic_dma_hwdescs *dma_hwdescs; 79 dma_addr_t dma_hwdescs_phys; 80 81 bool panel_is_sharp; 82 bool no_vblank; 83 84 /* 85 * clk_mutex is used to synchronize the pixel clock rate update with 86 * the VBLANK. When the pixel clock's parent clock needs to be updated, 87 * clock_nb's notifier function will lock the mutex, then wait until the 88 * next VBLANK. At that point, the parent clock's rate can be updated, 89 * and the mutex is then unlocked. If an atomic commit happens in the 90 * meantime, it will lock on the mutex, effectively waiting until the 91 * clock update process finishes. Finally, the pixel clock's rate will 92 * be recomputed when the mutex has been released, in the pending atomic 93 * commit, or a future one. 94 */ 95 struct mutex clk_mutex; 96 bool update_clk_rate; 97 struct notifier_block clock_nb; 98 }; 99 100 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 101 { 102 switch (reg) { 103 case JZ_REG_LCD_IID: 104 case JZ_REG_LCD_SA0: 105 case JZ_REG_LCD_FID0: 106 case JZ_REG_LCD_CMD0: 107 case JZ_REG_LCD_SA1: 108 case JZ_REG_LCD_FID1: 109 case JZ_REG_LCD_CMD1: 110 return false; 111 default: 112 return true; 113 } 114 } 115 116 static const struct regmap_config ingenic_drm_regmap_config = { 117 .reg_bits = 32, 118 .val_bits = 32, 119 .reg_stride = 4, 120 121 .max_register = JZ_REG_LCD_SIZE1, 122 .writeable_reg = ingenic_drm_writeable_reg, 123 }; 124 125 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 126 { 127 return container_of(drm, struct ingenic_drm, drm); 128 } 129 130 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 131 { 132 return container_of(crtc, struct ingenic_drm, crtc); 133 } 134 135 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 136 { 137 return container_of(nb, struct ingenic_drm, clock_nb); 138 } 139 140 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 141 unsigned long action, 142 void *data) 143 { 144 struct ingenic_drm *priv = drm_nb_get_priv(nb); 145 146 switch (action) { 147 case PRE_RATE_CHANGE: 148 mutex_lock(&priv->clk_mutex); 149 priv->update_clk_rate = true; 150 drm_crtc_wait_one_vblank(&priv->crtc); 151 return NOTIFY_OK; 152 default: 153 mutex_unlock(&priv->clk_mutex); 154 return NOTIFY_OK; 155 } 156 } 157 158 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 159 struct drm_atomic_state *state) 160 { 161 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 162 163 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 164 165 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 166 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 167 JZ_LCD_CTRL_ENABLE); 168 169 drm_crtc_vblank_on(crtc); 170 } 171 172 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 173 struct drm_atomic_state *state) 174 { 175 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 176 unsigned int var; 177 178 drm_crtc_vblank_off(crtc); 179 180 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 181 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 182 183 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 184 var & JZ_LCD_STATE_DISABLED, 185 1000, 0); 186 } 187 188 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 189 struct drm_display_mode *mode) 190 { 191 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 192 193 vpe = mode->vsync_end - mode->vsync_start; 194 vds = mode->vtotal - mode->vsync_start; 195 vde = vds + mode->vdisplay; 196 vt = vde + mode->vsync_start - mode->vdisplay; 197 198 hpe = mode->hsync_end - mode->hsync_start; 199 hds = mode->htotal - mode->hsync_start; 200 hde = hds + mode->hdisplay; 201 ht = hde + mode->hsync_start - mode->hdisplay; 202 203 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 204 0 << JZ_LCD_VSYNC_VPS_OFFSET | 205 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 206 207 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 208 0 << JZ_LCD_HSYNC_HPS_OFFSET | 209 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 210 211 regmap_write(priv->map, JZ_REG_LCD_VAT, 212 ht << JZ_LCD_VAT_HT_OFFSET | 213 vt << JZ_LCD_VAT_VT_OFFSET); 214 215 regmap_write(priv->map, JZ_REG_LCD_DAH, 216 hds << JZ_LCD_DAH_HDS_OFFSET | 217 hde << JZ_LCD_DAH_HDE_OFFSET); 218 regmap_write(priv->map, JZ_REG_LCD_DAV, 219 vds << JZ_LCD_DAV_VDS_OFFSET | 220 vde << JZ_LCD_DAV_VDE_OFFSET); 221 222 if (priv->panel_is_sharp) { 223 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 224 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 225 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 226 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 227 } 228 229 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 230 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 231 232 /* 233 * IPU restart - specify how much time the LCDC will wait before 234 * transferring a new frame from the IPU. The value is the one 235 * suggested in the programming manual. 236 */ 237 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 238 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 239 } 240 241 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 242 struct drm_atomic_state *state) 243 { 244 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 245 crtc); 246 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 247 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 248 249 if (crtc_state->gamma_lut && 250 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 251 dev_dbg(priv->dev, "Invalid palette size\n"); 252 return -EINVAL; 253 } 254 255 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 256 f1_state = drm_atomic_get_plane_state(crtc_state->state, 257 &priv->f1); 258 if (IS_ERR(f1_state)) 259 return PTR_ERR(f1_state); 260 261 f0_state = drm_atomic_get_plane_state(crtc_state->state, 262 &priv->f0); 263 if (IS_ERR(f0_state)) 264 return PTR_ERR(f0_state); 265 266 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 267 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 268 priv->ipu_plane); 269 if (IS_ERR(ipu_state)) 270 return PTR_ERR(ipu_state); 271 272 /* IPU and F1 planes cannot be enabled at the same time. */ 273 if (f1_state->fb && ipu_state->fb) { 274 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 275 return -EINVAL; 276 } 277 } 278 279 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 280 priv->no_vblank = !f1_state->fb && !f0_state->fb && 281 !(ipu_state && ipu_state->fb); 282 } 283 284 return 0; 285 } 286 287 static enum drm_mode_status 288 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 289 { 290 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 291 long rate; 292 293 if (mode->hdisplay > priv->soc_info->max_width) 294 return MODE_BAD_HVALUE; 295 if (mode->vdisplay > priv->soc_info->max_height) 296 return MODE_BAD_VVALUE; 297 298 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 299 if (rate < 0) 300 return MODE_CLOCK_RANGE; 301 302 return MODE_OK; 303 } 304 305 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 306 struct drm_atomic_state *state) 307 { 308 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 309 crtc); 310 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 311 u32 ctrl = 0; 312 313 if (priv->soc_info->has_osd && 314 drm_atomic_crtc_needs_modeset(crtc_state)) { 315 /* 316 * If IPU plane is enabled, enable IPU as source for the F1 317 * plane; otherwise use regular DMA. 318 */ 319 if (priv->ipu_plane && priv->ipu_plane->state->fb) 320 ctrl |= JZ_LCD_OSDCTRL_IPU; 321 322 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 323 JZ_LCD_OSDCTRL_IPU, ctrl); 324 } 325 } 326 327 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 328 struct drm_atomic_state *state) 329 { 330 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 331 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 332 crtc); 333 struct drm_pending_vblank_event *event = crtc_state->event; 334 335 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 336 ingenic_drm_crtc_update_timings(priv, &crtc_state->mode); 337 priv->update_clk_rate = true; 338 } 339 340 if (priv->update_clk_rate) { 341 mutex_lock(&priv->clk_mutex); 342 clk_set_rate(priv->pix_clk, 343 crtc_state->adjusted_mode.clock * 1000); 344 priv->update_clk_rate = false; 345 mutex_unlock(&priv->clk_mutex); 346 } 347 348 if (event) { 349 crtc_state->event = NULL; 350 351 spin_lock_irq(&crtc->dev->event_lock); 352 if (drm_crtc_vblank_get(crtc) == 0) 353 drm_crtc_arm_vblank_event(crtc, event); 354 else 355 drm_crtc_send_vblank_event(crtc, event); 356 spin_unlock_irq(&crtc->dev->event_lock); 357 } 358 } 359 360 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 361 struct drm_plane_state *state) 362 { 363 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 364 struct drm_crtc_state *crtc_state; 365 struct drm_crtc *crtc = state->crtc ?: plane->state->crtc; 366 int ret; 367 368 if (!crtc) 369 return 0; 370 371 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 372 if (WARN_ON(!crtc_state)) 373 return -EINVAL; 374 375 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 376 DRM_PLANE_HELPER_NO_SCALING, 377 DRM_PLANE_HELPER_NO_SCALING, 378 priv->soc_info->has_osd, 379 true); 380 if (ret) 381 return ret; 382 383 /* 384 * If OSD is not available, check that the width/height match. 385 * Note that state->src_* are in 16.16 fixed-point format. 386 */ 387 if (!priv->soc_info->has_osd && 388 (state->src_x != 0 || 389 (state->src_w >> 16) != state->crtc_w || 390 (state->src_h >> 16) != state->crtc_h)) 391 return -EINVAL; 392 393 /* 394 * Require full modeset if enabling or disabling a plane, or changing 395 * its position, size or depth. 396 */ 397 if (priv->soc_info->has_osd && 398 (!plane->state->fb || !state->fb || 399 plane->state->crtc_x != state->crtc_x || 400 plane->state->crtc_y != state->crtc_y || 401 plane->state->crtc_w != state->crtc_w || 402 plane->state->crtc_h != state->crtc_h || 403 plane->state->fb->format->format != state->fb->format->format)) 404 crtc_state->mode_changed = true; 405 406 return 0; 407 } 408 409 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 410 struct drm_plane *plane) 411 { 412 unsigned int en_bit; 413 414 if (priv->soc_info->has_osd) { 415 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 416 en_bit = JZ_LCD_OSDC_F1EN; 417 else 418 en_bit = JZ_LCD_OSDC_F0EN; 419 420 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 421 } 422 } 423 424 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 425 { 426 struct ingenic_drm *priv = dev_get_drvdata(dev); 427 unsigned int en_bit; 428 429 if (priv->soc_info->has_osd) { 430 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 431 en_bit = JZ_LCD_OSDC_F1EN; 432 else 433 en_bit = JZ_LCD_OSDC_F0EN; 434 435 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 436 } 437 } 438 439 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 440 struct drm_plane_state *old_state) 441 { 442 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 443 444 ingenic_drm_plane_disable(priv->dev, plane); 445 } 446 447 void ingenic_drm_plane_config(struct device *dev, 448 struct drm_plane *plane, u32 fourcc) 449 { 450 struct ingenic_drm *priv = dev_get_drvdata(dev); 451 struct drm_plane_state *state = plane->state; 452 unsigned int xy_reg, size_reg; 453 unsigned int ctrl = 0; 454 455 ingenic_drm_plane_enable(priv, plane); 456 457 if (priv->soc_info->has_osd && 458 plane->type == DRM_PLANE_TYPE_PRIMARY) { 459 switch (fourcc) { 460 case DRM_FORMAT_XRGB1555: 461 ctrl |= JZ_LCD_OSDCTRL_RGB555; 462 fallthrough; 463 case DRM_FORMAT_RGB565: 464 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 465 break; 466 case DRM_FORMAT_RGB888: 467 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 468 break; 469 case DRM_FORMAT_XRGB8888: 470 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 471 break; 472 case DRM_FORMAT_XRGB2101010: 473 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 474 break; 475 } 476 477 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 478 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 479 } else { 480 switch (fourcc) { 481 case DRM_FORMAT_C8: 482 ctrl |= JZ_LCD_CTRL_BPP_8; 483 break; 484 case DRM_FORMAT_XRGB1555: 485 ctrl |= JZ_LCD_CTRL_RGB555; 486 fallthrough; 487 case DRM_FORMAT_RGB565: 488 ctrl |= JZ_LCD_CTRL_BPP_15_16; 489 break; 490 case DRM_FORMAT_RGB888: 491 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 492 break; 493 case DRM_FORMAT_XRGB8888: 494 ctrl |= JZ_LCD_CTRL_BPP_18_24; 495 break; 496 case DRM_FORMAT_XRGB2101010: 497 ctrl |= JZ_LCD_CTRL_BPP_30; 498 break; 499 } 500 501 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 502 JZ_LCD_CTRL_BPP_MASK, ctrl); 503 } 504 505 if (priv->soc_info->has_osd) { 506 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 507 xy_reg = JZ_REG_LCD_XYP1; 508 size_reg = JZ_REG_LCD_SIZE1; 509 } else { 510 xy_reg = JZ_REG_LCD_XYP0; 511 size_reg = JZ_REG_LCD_SIZE0; 512 } 513 514 regmap_write(priv->map, xy_reg, 515 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 516 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 517 regmap_write(priv->map, size_reg, 518 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 519 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 520 } 521 } 522 523 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 524 const struct drm_color_lut *lut) 525 { 526 unsigned int i; 527 528 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 529 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 530 | drm_color_lut_extract(lut[i].green, 6) << 5 531 | drm_color_lut_extract(lut[i].blue, 5); 532 533 priv->dma_hwdescs->palette[i] = color; 534 } 535 } 536 537 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 538 struct drm_plane_state *oldstate) 539 { 540 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 541 struct drm_plane_state *state = plane->state; 542 struct drm_crtc_state *crtc_state; 543 struct ingenic_dma_hwdesc *hwdesc; 544 unsigned int width, height, cpp, offset; 545 dma_addr_t addr; 546 u32 fourcc; 547 548 if (state && state->fb) { 549 crtc_state = state->crtc->state; 550 551 addr = drm_fb_cma_get_gem_addr(state->fb, state, 0); 552 width = state->src_w >> 16; 553 height = state->src_h >> 16; 554 cpp = state->fb->format->cpp[0]; 555 556 if (priv->soc_info->has_osd && plane->type == DRM_PLANE_TYPE_OVERLAY) 557 hwdesc = &priv->dma_hwdescs->hwdesc_f0; 558 else 559 hwdesc = &priv->dma_hwdescs->hwdesc_f1; 560 561 hwdesc->addr = addr; 562 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 563 564 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 565 fourcc = state->fb->format->format; 566 567 ingenic_drm_plane_config(priv->dev, plane, fourcc); 568 569 if (fourcc == DRM_FORMAT_C8) 570 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_pal); 571 else 572 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 573 574 priv->dma_hwdescs->hwdesc_f0.next = priv->dma_hwdescs_phys + offset; 575 576 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 577 } 578 579 if (crtc_state->color_mgmt_changed) 580 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 581 } 582 } 583 584 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 585 struct drm_crtc_state *crtc_state, 586 struct drm_connector_state *conn_state) 587 { 588 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 589 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 590 struct drm_connector *conn = conn_state->connector; 591 struct drm_display_info *info = &conn->display_info; 592 unsigned int cfg; 593 594 priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS; 595 596 if (priv->panel_is_sharp) { 597 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 598 } else { 599 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 600 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 601 } 602 603 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 604 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 605 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 606 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 607 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 608 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 609 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 610 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 611 612 if (!priv->panel_is_sharp) { 613 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) { 614 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 615 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 616 else 617 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 618 } else { 619 switch (*info->bus_formats) { 620 case MEDIA_BUS_FMT_RGB565_1X16: 621 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 622 break; 623 case MEDIA_BUS_FMT_RGB666_1X18: 624 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 625 break; 626 case MEDIA_BUS_FMT_RGB888_1X24: 627 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 628 break; 629 case MEDIA_BUS_FMT_RGB888_3X8: 630 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 631 break; 632 default: 633 break; 634 } 635 } 636 } 637 638 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 639 } 640 641 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, 642 struct drm_crtc_state *crtc_state, 643 struct drm_connector_state *conn_state) 644 { 645 struct drm_display_info *info = &conn_state->connector->display_info; 646 647 if (info->num_bus_formats != 1) 648 return -EINVAL; 649 650 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 651 return 0; 652 653 switch (*info->bus_formats) { 654 case MEDIA_BUS_FMT_RGB565_1X16: 655 case MEDIA_BUS_FMT_RGB666_1X18: 656 case MEDIA_BUS_FMT_RGB888_1X24: 657 case MEDIA_BUS_FMT_RGB888_3X8: 658 return 0; 659 default: 660 return -EINVAL; 661 } 662 } 663 664 static void ingenic_drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state) 665 { 666 /* 667 * Just your regular drm_atomic_helper_commit_tail(), but only calls 668 * drm_atomic_helper_wait_for_vblanks() if priv->no_vblank. 669 */ 670 struct drm_device *dev = old_state->dev; 671 struct ingenic_drm *priv = drm_device_get_priv(dev); 672 673 drm_atomic_helper_commit_modeset_disables(dev, old_state); 674 675 drm_atomic_helper_commit_planes(dev, old_state, 0); 676 677 drm_atomic_helper_commit_modeset_enables(dev, old_state); 678 679 drm_atomic_helper_commit_hw_done(old_state); 680 681 if (!priv->no_vblank) 682 drm_atomic_helper_wait_for_vblanks(dev, old_state); 683 684 drm_atomic_helper_cleanup_planes(dev, old_state); 685 } 686 687 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 688 { 689 struct ingenic_drm *priv = drm_device_get_priv(arg); 690 unsigned int state; 691 692 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 693 694 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 695 JZ_LCD_STATE_EOF_IRQ, 0); 696 697 if (state & JZ_LCD_STATE_EOF_IRQ) 698 drm_crtc_handle_vblank(&priv->crtc); 699 700 return IRQ_HANDLED; 701 } 702 703 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 704 { 705 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 706 707 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 708 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 709 710 return 0; 711 } 712 713 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 714 { 715 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 716 717 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 718 } 719 720 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 721 722 static const struct drm_driver ingenic_drm_driver_data = { 723 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 724 .name = "ingenic-drm", 725 .desc = "DRM module for Ingenic SoCs", 726 .date = "20200716", 727 .major = 1, 728 .minor = 1, 729 .patchlevel = 0, 730 731 .fops = &ingenic_drm_fops, 732 DRM_GEM_CMA_DRIVER_OPS, 733 734 .irq_handler = ingenic_drm_irq_handler, 735 }; 736 737 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 738 .update_plane = drm_atomic_helper_update_plane, 739 .disable_plane = drm_atomic_helper_disable_plane, 740 .reset = drm_atomic_helper_plane_reset, 741 .destroy = drm_plane_cleanup, 742 743 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 744 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 745 }; 746 747 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 748 .set_config = drm_atomic_helper_set_config, 749 .page_flip = drm_atomic_helper_page_flip, 750 .reset = drm_atomic_helper_crtc_reset, 751 .destroy = drm_crtc_cleanup, 752 753 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 754 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 755 756 .enable_vblank = ingenic_drm_enable_vblank, 757 .disable_vblank = ingenic_drm_disable_vblank, 758 759 .gamma_set = drm_atomic_helper_legacy_gamma_set, 760 }; 761 762 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 763 .atomic_update = ingenic_drm_plane_atomic_update, 764 .atomic_check = ingenic_drm_plane_atomic_check, 765 .atomic_disable = ingenic_drm_plane_atomic_disable, 766 .prepare_fb = drm_gem_fb_prepare_fb, 767 }; 768 769 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 770 .atomic_enable = ingenic_drm_crtc_atomic_enable, 771 .atomic_disable = ingenic_drm_crtc_atomic_disable, 772 .atomic_begin = ingenic_drm_crtc_atomic_begin, 773 .atomic_flush = ingenic_drm_crtc_atomic_flush, 774 .atomic_check = ingenic_drm_crtc_atomic_check, 775 .mode_valid = ingenic_drm_crtc_mode_valid, 776 }; 777 778 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 779 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 780 .atomic_check = ingenic_drm_encoder_atomic_check, 781 }; 782 783 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 784 .fb_create = drm_gem_fb_create, 785 .output_poll_changed = drm_fb_helper_output_poll_changed, 786 .atomic_check = drm_atomic_helper_check, 787 .atomic_commit = drm_atomic_helper_commit, 788 }; 789 790 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 791 .atomic_commit_tail = ingenic_drm_atomic_helper_commit_tail, 792 }; 793 794 static void ingenic_drm_unbind_all(void *d) 795 { 796 struct ingenic_drm *priv = d; 797 798 component_unbind_all(priv->dev, &priv->drm); 799 } 800 801 static void __maybe_unused ingenic_drm_release_rmem(void *d) 802 { 803 of_reserved_mem_device_release(d); 804 } 805 806 static int ingenic_drm_bind(struct device *dev, bool has_components) 807 { 808 struct platform_device *pdev = to_platform_device(dev); 809 const struct jz_soc_info *soc_info; 810 struct ingenic_drm *priv; 811 struct clk *parent_clk; 812 struct drm_bridge *bridge; 813 struct drm_panel *panel; 814 struct drm_encoder *encoder; 815 struct drm_device *drm; 816 void __iomem *base; 817 long parent_rate; 818 unsigned int i, clone_mask = 0; 819 dma_addr_t dma_hwdesc_phys_f0, dma_hwdesc_phys_f1; 820 int ret, irq; 821 822 soc_info = of_device_get_match_data(dev); 823 if (!soc_info) { 824 dev_err(dev, "Missing platform data\n"); 825 return -EINVAL; 826 } 827 828 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 829 ret = of_reserved_mem_device_init(dev); 830 831 if (ret && ret != -ENODEV) 832 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 833 834 if (!ret) { 835 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 836 if (ret) 837 return ret; 838 } 839 } 840 841 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 842 struct ingenic_drm, drm); 843 if (IS_ERR(priv)) 844 return PTR_ERR(priv); 845 846 priv->soc_info = soc_info; 847 priv->dev = dev; 848 drm = &priv->drm; 849 850 platform_set_drvdata(pdev, priv); 851 852 ret = drmm_mode_config_init(drm); 853 if (ret) 854 return ret; 855 856 drm->mode_config.min_width = 0; 857 drm->mode_config.min_height = 0; 858 drm->mode_config.max_width = soc_info->max_width; 859 drm->mode_config.max_height = 4095; 860 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 861 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 862 863 base = devm_platform_ioremap_resource(pdev, 0); 864 if (IS_ERR(base)) { 865 dev_err(dev, "Failed to get memory resource\n"); 866 return PTR_ERR(base); 867 } 868 869 priv->map = devm_regmap_init_mmio(dev, base, 870 &ingenic_drm_regmap_config); 871 if (IS_ERR(priv->map)) { 872 dev_err(dev, "Failed to create regmap\n"); 873 return PTR_ERR(priv->map); 874 } 875 876 irq = platform_get_irq(pdev, 0); 877 if (irq < 0) 878 return irq; 879 880 if (soc_info->needs_dev_clk) { 881 priv->lcd_clk = devm_clk_get(dev, "lcd"); 882 if (IS_ERR(priv->lcd_clk)) { 883 dev_err(dev, "Failed to get lcd clock\n"); 884 return PTR_ERR(priv->lcd_clk); 885 } 886 } 887 888 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 889 if (IS_ERR(priv->pix_clk)) { 890 dev_err(dev, "Failed to get pixel clock\n"); 891 return PTR_ERR(priv->pix_clk); 892 } 893 894 priv->dma_hwdescs = dmam_alloc_coherent(dev, 895 sizeof(*priv->dma_hwdescs), 896 &priv->dma_hwdescs_phys, 897 GFP_KERNEL); 898 if (!priv->dma_hwdescs) 899 return -ENOMEM; 900 901 902 /* Configure DMA hwdesc for foreground0 plane */ 903 dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys 904 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 905 priv->dma_hwdescs->hwdesc_f0.next = dma_hwdesc_phys_f0; 906 priv->dma_hwdescs->hwdesc_f0.id = 0xf0; 907 908 /* Configure DMA hwdesc for foreground1 plane */ 909 dma_hwdesc_phys_f1 = priv->dma_hwdescs_phys 910 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f1); 911 priv->dma_hwdescs->hwdesc_f1.next = dma_hwdesc_phys_f1; 912 priv->dma_hwdescs->hwdesc_f1.id = 0xf1; 913 914 /* Configure DMA hwdesc for palette */ 915 priv->dma_hwdescs->hwdesc_pal.next = priv->dma_hwdescs_phys 916 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 917 priv->dma_hwdescs->hwdesc_pal.id = 0xc0; 918 priv->dma_hwdescs->hwdesc_pal.addr = priv->dma_hwdescs_phys 919 + offsetof(struct ingenic_dma_hwdescs, palette); 920 priv->dma_hwdescs->hwdesc_pal.cmd = JZ_LCD_CMD_ENABLE_PAL 921 | (sizeof(priv->dma_hwdescs->palette) / 4); 922 923 if (soc_info->has_osd) 924 priv->ipu_plane = drm_plane_from_index(drm, 0); 925 926 drm_plane_helper_add(&priv->f1, &ingenic_drm_plane_helper_funcs); 927 928 ret = drm_universal_plane_init(drm, &priv->f1, 1, 929 &ingenic_drm_primary_plane_funcs, 930 priv->soc_info->formats_f1, 931 priv->soc_info->num_formats_f1, 932 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 933 if (ret) { 934 dev_err(dev, "Failed to register plane: %i\n", ret); 935 return ret; 936 } 937 938 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 939 940 ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->f1, 941 NULL, &ingenic_drm_crtc_funcs, NULL); 942 if (ret) { 943 dev_err(dev, "Failed to init CRTC: %i\n", ret); 944 return ret; 945 } 946 947 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 948 ARRAY_SIZE(priv->dma_hwdescs->palette)); 949 950 if (soc_info->has_osd) { 951 drm_plane_helper_add(&priv->f0, 952 &ingenic_drm_plane_helper_funcs); 953 954 ret = drm_universal_plane_init(drm, &priv->f0, 1, 955 &ingenic_drm_primary_plane_funcs, 956 priv->soc_info->formats_f0, 957 priv->soc_info->num_formats_f0, 958 NULL, DRM_PLANE_TYPE_OVERLAY, 959 NULL); 960 if (ret) { 961 dev_err(dev, "Failed to register overlay plane: %i\n", 962 ret); 963 return ret; 964 } 965 966 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 967 ret = component_bind_all(dev, drm); 968 if (ret) { 969 if (ret != -EPROBE_DEFER) 970 dev_err(dev, "Failed to bind components: %i\n", ret); 971 return ret; 972 } 973 974 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 975 if (ret) 976 return ret; 977 978 priv->ipu_plane = drm_plane_from_index(drm, 2); 979 if (!priv->ipu_plane) { 980 dev_err(dev, "Failed to retrieve IPU plane\n"); 981 return -EINVAL; 982 } 983 } 984 } 985 986 for (i = 0; ; i++) { 987 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 988 if (ret) { 989 if (ret == -ENODEV) 990 break; /* we're done */ 991 if (ret != -EPROBE_DEFER) 992 dev_err(dev, "Failed to get bridge handle\n"); 993 return ret; 994 } 995 996 if (panel) 997 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 998 DRM_MODE_CONNECTOR_DPI); 999 1000 encoder = devm_kzalloc(dev, sizeof(*encoder), GFP_KERNEL); 1001 if (!encoder) 1002 return -ENOMEM; 1003 1004 encoder->possible_crtcs = 1; 1005 1006 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1007 1008 ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_DPI); 1009 if (ret) { 1010 dev_err(dev, "Failed to init encoder: %d\n", ret); 1011 return ret; 1012 } 1013 1014 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1015 if (ret) { 1016 dev_err(dev, "Unable to attach bridge\n"); 1017 return ret; 1018 } 1019 } 1020 1021 drm_for_each_encoder(encoder, drm) { 1022 clone_mask |= BIT(drm_encoder_index(encoder)); 1023 } 1024 1025 drm_for_each_encoder(encoder, drm) { 1026 encoder->possible_clones = clone_mask; 1027 } 1028 1029 ret = drm_irq_install(drm, irq); 1030 if (ret) { 1031 dev_err(dev, "Unable to install IRQ handler\n"); 1032 return ret; 1033 } 1034 1035 ret = drm_vblank_init(drm, 1); 1036 if (ret) { 1037 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1038 return ret; 1039 } 1040 1041 drm_mode_config_reset(drm); 1042 1043 ret = clk_prepare_enable(priv->pix_clk); 1044 if (ret) { 1045 dev_err(dev, "Unable to start pixel clock\n"); 1046 return ret; 1047 } 1048 1049 if (priv->lcd_clk) { 1050 parent_clk = clk_get_parent(priv->lcd_clk); 1051 parent_rate = clk_get_rate(parent_clk); 1052 1053 /* LCD Device clock must be 3x the pixel clock for STN panels, 1054 * or 1.5x the pixel clock for TFT panels. To avoid having to 1055 * check for the LCD device clock everytime we do a mode change, 1056 * we set the LCD device clock to the highest rate possible. 1057 */ 1058 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1059 if (ret) { 1060 dev_err(dev, "Unable to set LCD clock rate\n"); 1061 goto err_pixclk_disable; 1062 } 1063 1064 ret = clk_prepare_enable(priv->lcd_clk); 1065 if (ret) { 1066 dev_err(dev, "Unable to start lcd clock\n"); 1067 goto err_pixclk_disable; 1068 } 1069 } 1070 1071 /* Set address of our DMA descriptor chain */ 1072 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0); 1073 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1); 1074 1075 /* Enable OSD if available */ 1076 if (soc_info->has_osd) 1077 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); 1078 1079 mutex_init(&priv->clk_mutex); 1080 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1081 1082 parent_clk = clk_get_parent(priv->pix_clk); 1083 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1084 if (ret) { 1085 dev_err(dev, "Unable to register clock notifier\n"); 1086 goto err_devclk_disable; 1087 } 1088 1089 ret = drm_dev_register(drm, 0); 1090 if (ret) { 1091 dev_err(dev, "Failed to register DRM driver\n"); 1092 goto err_clk_notifier_unregister; 1093 } 1094 1095 drm_fbdev_generic_setup(drm, 32); 1096 1097 return 0; 1098 1099 err_clk_notifier_unregister: 1100 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1101 err_devclk_disable: 1102 if (priv->lcd_clk) 1103 clk_disable_unprepare(priv->lcd_clk); 1104 err_pixclk_disable: 1105 clk_disable_unprepare(priv->pix_clk); 1106 return ret; 1107 } 1108 1109 static int ingenic_drm_bind_with_components(struct device *dev) 1110 { 1111 return ingenic_drm_bind(dev, true); 1112 } 1113 1114 static int compare_of(struct device *dev, void *data) 1115 { 1116 return dev->of_node == data; 1117 } 1118 1119 static void ingenic_drm_unbind(struct device *dev) 1120 { 1121 struct ingenic_drm *priv = dev_get_drvdata(dev); 1122 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1123 1124 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1125 if (priv->lcd_clk) 1126 clk_disable_unprepare(priv->lcd_clk); 1127 clk_disable_unprepare(priv->pix_clk); 1128 1129 drm_dev_unregister(&priv->drm); 1130 drm_atomic_helper_shutdown(&priv->drm); 1131 } 1132 1133 static const struct component_master_ops ingenic_master_ops = { 1134 .bind = ingenic_drm_bind_with_components, 1135 .unbind = ingenic_drm_unbind, 1136 }; 1137 1138 static int ingenic_drm_probe(struct platform_device *pdev) 1139 { 1140 struct device *dev = &pdev->dev; 1141 struct component_match *match = NULL; 1142 struct device_node *np; 1143 1144 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1145 return ingenic_drm_bind(dev, false); 1146 1147 /* IPU is at port address 8 */ 1148 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1149 if (!np) 1150 return ingenic_drm_bind(dev, false); 1151 1152 drm_of_component_match_add(dev, &match, compare_of, np); 1153 of_node_put(np); 1154 1155 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1156 } 1157 1158 static int ingenic_drm_remove(struct platform_device *pdev) 1159 { 1160 struct device *dev = &pdev->dev; 1161 1162 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1163 ingenic_drm_unbind(dev); 1164 else 1165 component_master_del(dev, &ingenic_master_ops); 1166 1167 return 0; 1168 } 1169 1170 static const u32 jz4740_formats[] = { 1171 DRM_FORMAT_XRGB1555, 1172 DRM_FORMAT_RGB565, 1173 DRM_FORMAT_XRGB8888, 1174 }; 1175 1176 static const u32 jz4725b_formats_f1[] = { 1177 DRM_FORMAT_XRGB1555, 1178 DRM_FORMAT_RGB565, 1179 DRM_FORMAT_XRGB8888, 1180 }; 1181 1182 static const u32 jz4725b_formats_f0[] = { 1183 DRM_FORMAT_C8, 1184 DRM_FORMAT_XRGB1555, 1185 DRM_FORMAT_RGB565, 1186 DRM_FORMAT_XRGB8888, 1187 }; 1188 1189 static const u32 jz4770_formats_f1[] = { 1190 DRM_FORMAT_XRGB1555, 1191 DRM_FORMAT_RGB565, 1192 DRM_FORMAT_RGB888, 1193 DRM_FORMAT_XRGB8888, 1194 DRM_FORMAT_XRGB2101010, 1195 }; 1196 1197 static const u32 jz4770_formats_f0[] = { 1198 DRM_FORMAT_C8, 1199 DRM_FORMAT_XRGB1555, 1200 DRM_FORMAT_RGB565, 1201 DRM_FORMAT_RGB888, 1202 DRM_FORMAT_XRGB8888, 1203 DRM_FORMAT_XRGB2101010, 1204 }; 1205 1206 static const struct jz_soc_info jz4740_soc_info = { 1207 .needs_dev_clk = true, 1208 .has_osd = false, 1209 .max_width = 800, 1210 .max_height = 600, 1211 .formats_f1 = jz4740_formats, 1212 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1213 /* JZ4740 has only one plane */ 1214 }; 1215 1216 static const struct jz_soc_info jz4725b_soc_info = { 1217 .needs_dev_clk = false, 1218 .has_osd = true, 1219 .max_width = 800, 1220 .max_height = 600, 1221 .formats_f1 = jz4725b_formats_f1, 1222 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1223 .formats_f0 = jz4725b_formats_f0, 1224 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1225 }; 1226 1227 static const struct jz_soc_info jz4770_soc_info = { 1228 .needs_dev_clk = false, 1229 .has_osd = true, 1230 .max_width = 1280, 1231 .max_height = 720, 1232 .formats_f1 = jz4770_formats_f1, 1233 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1234 .formats_f0 = jz4770_formats_f0, 1235 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1236 }; 1237 1238 static const struct of_device_id ingenic_drm_of_match[] = { 1239 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1240 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1241 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1242 { /* sentinel */ }, 1243 }; 1244 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1245 1246 static struct platform_driver ingenic_drm_driver = { 1247 .driver = { 1248 .name = "ingenic-drm", 1249 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1250 }, 1251 .probe = ingenic_drm_probe, 1252 .remove = ingenic_drm_remove, 1253 }; 1254 1255 static int ingenic_drm_init(void) 1256 { 1257 int err; 1258 1259 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1260 err = platform_driver_register(ingenic_ipu_driver_ptr); 1261 if (err) 1262 return err; 1263 } 1264 1265 return platform_driver_register(&ingenic_drm_driver); 1266 } 1267 module_init(ingenic_drm_init); 1268 1269 static void ingenic_drm_exit(void) 1270 { 1271 platform_driver_unregister(&ingenic_drm_driver); 1272 1273 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1274 platform_driver_unregister(ingenic_ipu_driver_ptr); 1275 } 1276 module_exit(ingenic_drm_exit); 1277 1278 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1279 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1280 MODULE_LICENSE("GPL v2"); 1281