1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/component.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of_device.h> 16 #include <linux/of_reserved_mem.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/regmap.h> 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_bridge_connector.h> 25 #include <drm/drm_color_mgmt.h> 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drm_damage_helper.h> 29 #include <drm/drm_drv.h> 30 #include <drm/drm_encoder.h> 31 #include <drm/drm_gem_cma_helper.h> 32 #include <drm/drm_fb_cma_helper.h> 33 #include <drm/drm_fb_helper.h> 34 #include <drm/drm_fourcc.h> 35 #include <drm/drm_gem_atomic_helper.h> 36 #include <drm/drm_gem_framebuffer_helper.h> 37 #include <drm/drm_managed.h> 38 #include <drm/drm_of.h> 39 #include <drm/drm_panel.h> 40 #include <drm/drm_plane.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_vblank.h> 44 45 #define HWDESC_PALETTE 2 46 47 struct ingenic_dma_hwdesc { 48 u32 next; 49 u32 addr; 50 u32 id; 51 u32 cmd; 52 } __aligned(16); 53 54 struct ingenic_dma_hwdescs { 55 struct ingenic_dma_hwdesc hwdesc[3]; 56 u16 palette[256] __aligned(16); 57 }; 58 59 struct jz_soc_info { 60 bool needs_dev_clk; 61 bool has_osd; 62 bool map_noncoherent; 63 unsigned int max_width, max_height; 64 const u32 *formats_f0, *formats_f1; 65 unsigned int num_formats_f0, num_formats_f1; 66 }; 67 68 struct ingenic_drm_private_state { 69 struct drm_private_state base; 70 bool use_palette; 71 }; 72 73 struct ingenic_drm { 74 struct drm_device drm; 75 /* 76 * f1 (aka. foreground1) is our primary plane, on top of which 77 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 78 * hardware and cannot be changed. 79 */ 80 struct drm_plane f0, f1, *ipu_plane; 81 struct drm_crtc crtc; 82 83 struct device *dev; 84 struct regmap *map; 85 struct clk *lcd_clk, *pix_clk; 86 const struct jz_soc_info *soc_info; 87 88 struct ingenic_dma_hwdescs *dma_hwdescs; 89 dma_addr_t dma_hwdescs_phys; 90 91 bool panel_is_sharp; 92 bool no_vblank; 93 94 /* 95 * clk_mutex is used to synchronize the pixel clock rate update with 96 * the VBLANK. When the pixel clock's parent clock needs to be updated, 97 * clock_nb's notifier function will lock the mutex, then wait until the 98 * next VBLANK. At that point, the parent clock's rate can be updated, 99 * and the mutex is then unlocked. If an atomic commit happens in the 100 * meantime, it will lock on the mutex, effectively waiting until the 101 * clock update process finishes. Finally, the pixel clock's rate will 102 * be recomputed when the mutex has been released, in the pending atomic 103 * commit, or a future one. 104 */ 105 struct mutex clk_mutex; 106 bool update_clk_rate; 107 struct notifier_block clock_nb; 108 109 struct drm_private_obj private_obj; 110 }; 111 112 struct ingenic_drm_bridge { 113 struct drm_encoder encoder; 114 struct drm_bridge bridge, *next_bridge; 115 116 struct drm_bus_cfg bus_cfg; 117 }; 118 119 static inline struct ingenic_drm_bridge * 120 to_ingenic_drm_bridge(struct drm_encoder *encoder) 121 { 122 return container_of(encoder, struct ingenic_drm_bridge, encoder); 123 } 124 125 static inline struct ingenic_drm_private_state * 126 to_ingenic_drm_priv_state(struct drm_private_state *state) 127 { 128 return container_of(state, struct ingenic_drm_private_state, base); 129 } 130 131 static struct ingenic_drm_private_state * 132 ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 133 { 134 struct drm_private_state *priv_state; 135 136 priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj); 137 if (IS_ERR(priv_state)) 138 return ERR_CAST(priv_state); 139 140 return to_ingenic_drm_priv_state(priv_state); 141 } 142 143 static struct ingenic_drm_private_state * 144 ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 145 { 146 struct drm_private_state *priv_state; 147 148 priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj); 149 if (!priv_state) 150 return NULL; 151 152 return to_ingenic_drm_priv_state(priv_state); 153 } 154 155 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 156 { 157 switch (reg) { 158 case JZ_REG_LCD_IID: 159 case JZ_REG_LCD_SA0: 160 case JZ_REG_LCD_FID0: 161 case JZ_REG_LCD_CMD0: 162 case JZ_REG_LCD_SA1: 163 case JZ_REG_LCD_FID1: 164 case JZ_REG_LCD_CMD1: 165 return false; 166 default: 167 return true; 168 } 169 } 170 171 static const struct regmap_config ingenic_drm_regmap_config = { 172 .reg_bits = 32, 173 .val_bits = 32, 174 .reg_stride = 4, 175 176 .max_register = JZ_REG_LCD_SIZE1, 177 .writeable_reg = ingenic_drm_writeable_reg, 178 }; 179 180 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 181 { 182 return container_of(drm, struct ingenic_drm, drm); 183 } 184 185 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 186 { 187 return container_of(crtc, struct ingenic_drm, crtc); 188 } 189 190 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 191 { 192 return container_of(nb, struct ingenic_drm, clock_nb); 193 } 194 195 static inline dma_addr_t dma_hwdesc_addr(const struct ingenic_drm *priv, 196 unsigned int idx) 197 { 198 u32 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc[idx]); 199 200 return priv->dma_hwdescs_phys + offset; 201 } 202 203 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 204 unsigned long action, 205 void *data) 206 { 207 struct ingenic_drm *priv = drm_nb_get_priv(nb); 208 209 switch (action) { 210 case PRE_RATE_CHANGE: 211 mutex_lock(&priv->clk_mutex); 212 priv->update_clk_rate = true; 213 drm_crtc_wait_one_vblank(&priv->crtc); 214 return NOTIFY_OK; 215 default: 216 mutex_unlock(&priv->clk_mutex); 217 return NOTIFY_OK; 218 } 219 } 220 221 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 222 struct drm_atomic_state *state) 223 { 224 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 225 struct ingenic_drm_private_state *priv_state; 226 unsigned int next_id; 227 228 priv_state = ingenic_drm_get_priv_state(priv, state); 229 if (WARN_ON(IS_ERR(priv_state))) 230 return; 231 232 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 233 234 /* Set addresses of our DMA descriptor chains */ 235 next_id = priv_state->use_palette ? HWDESC_PALETTE : 0; 236 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id)); 237 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); 238 239 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 240 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 241 JZ_LCD_CTRL_ENABLE); 242 243 drm_crtc_vblank_on(crtc); 244 } 245 246 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 247 struct drm_atomic_state *state) 248 { 249 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 250 unsigned int var; 251 252 drm_crtc_vblank_off(crtc); 253 254 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 255 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 256 257 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 258 var & JZ_LCD_STATE_DISABLED, 259 1000, 0); 260 } 261 262 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 263 struct drm_display_mode *mode) 264 { 265 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 266 267 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start; 268 vds = mode->crtc_vtotal - mode->crtc_vsync_start; 269 vde = vds + mode->crtc_vdisplay; 270 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay; 271 272 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start; 273 hds = mode->crtc_htotal - mode->crtc_hsync_start; 274 hde = hds + mode->crtc_hdisplay; 275 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay; 276 277 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 278 0 << JZ_LCD_VSYNC_VPS_OFFSET | 279 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 280 281 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 282 0 << JZ_LCD_HSYNC_HPS_OFFSET | 283 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 284 285 regmap_write(priv->map, JZ_REG_LCD_VAT, 286 ht << JZ_LCD_VAT_HT_OFFSET | 287 vt << JZ_LCD_VAT_VT_OFFSET); 288 289 regmap_write(priv->map, JZ_REG_LCD_DAH, 290 hds << JZ_LCD_DAH_HDS_OFFSET | 291 hde << JZ_LCD_DAH_HDE_OFFSET); 292 regmap_write(priv->map, JZ_REG_LCD_DAV, 293 vds << JZ_LCD_DAV_VDS_OFFSET | 294 vde << JZ_LCD_DAV_VDE_OFFSET); 295 296 if (priv->panel_is_sharp) { 297 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 298 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 299 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 300 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 301 } 302 303 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 304 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 305 306 /* 307 * IPU restart - specify how much time the LCDC will wait before 308 * transferring a new frame from the IPU. The value is the one 309 * suggested in the programming manual. 310 */ 311 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 312 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 313 } 314 315 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 316 struct drm_atomic_state *state) 317 { 318 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 319 crtc); 320 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 321 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 322 323 if (crtc_state->gamma_lut && 324 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 325 dev_dbg(priv->dev, "Invalid palette size\n"); 326 return -EINVAL; 327 } 328 329 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 330 f1_state = drm_atomic_get_plane_state(crtc_state->state, 331 &priv->f1); 332 if (IS_ERR(f1_state)) 333 return PTR_ERR(f1_state); 334 335 f0_state = drm_atomic_get_plane_state(crtc_state->state, 336 &priv->f0); 337 if (IS_ERR(f0_state)) 338 return PTR_ERR(f0_state); 339 340 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 341 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 342 priv->ipu_plane); 343 if (IS_ERR(ipu_state)) 344 return PTR_ERR(ipu_state); 345 346 /* IPU and F1 planes cannot be enabled at the same time. */ 347 if (f1_state->fb && ipu_state->fb) { 348 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 349 return -EINVAL; 350 } 351 } 352 353 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 354 priv->no_vblank = !f1_state->fb && !f0_state->fb && 355 !(ipu_state && ipu_state->fb); 356 } 357 358 return 0; 359 } 360 361 static enum drm_mode_status 362 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 363 { 364 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 365 long rate; 366 367 if (mode->hdisplay > priv->soc_info->max_width) 368 return MODE_BAD_HVALUE; 369 if (mode->vdisplay > priv->soc_info->max_height) 370 return MODE_BAD_VVALUE; 371 372 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 373 if (rate < 0) 374 return MODE_CLOCK_RANGE; 375 376 return MODE_OK; 377 } 378 379 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 380 struct drm_atomic_state *state) 381 { 382 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 383 crtc); 384 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 385 u32 ctrl = 0; 386 387 if (priv->soc_info->has_osd && 388 drm_atomic_crtc_needs_modeset(crtc_state)) { 389 /* 390 * If IPU plane is enabled, enable IPU as source for the F1 391 * plane; otherwise use regular DMA. 392 */ 393 if (priv->ipu_plane && priv->ipu_plane->state->fb) 394 ctrl |= JZ_LCD_OSDCTRL_IPU; 395 396 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 397 JZ_LCD_OSDCTRL_IPU, ctrl); 398 } 399 } 400 401 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 402 struct drm_atomic_state *state) 403 { 404 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 405 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 406 crtc); 407 struct drm_pending_vblank_event *event = crtc_state->event; 408 409 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 410 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode); 411 priv->update_clk_rate = true; 412 } 413 414 if (priv->update_clk_rate) { 415 mutex_lock(&priv->clk_mutex); 416 clk_set_rate(priv->pix_clk, 417 crtc_state->adjusted_mode.crtc_clock * 1000); 418 priv->update_clk_rate = false; 419 mutex_unlock(&priv->clk_mutex); 420 } 421 422 if (event) { 423 crtc_state->event = NULL; 424 425 spin_lock_irq(&crtc->dev->event_lock); 426 if (drm_crtc_vblank_get(crtc) == 0) 427 drm_crtc_arm_vblank_event(crtc, event); 428 else 429 drm_crtc_send_vblank_event(crtc, event); 430 spin_unlock_irq(&crtc->dev->event_lock); 431 } 432 } 433 434 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 435 struct drm_atomic_state *state) 436 { 437 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 438 plane); 439 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 440 plane); 441 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 442 struct ingenic_drm_private_state *priv_state; 443 struct drm_crtc_state *crtc_state; 444 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 445 int ret; 446 447 if (!crtc) 448 return 0; 449 450 crtc_state = drm_atomic_get_existing_crtc_state(state, 451 crtc); 452 if (WARN_ON(!crtc_state)) 453 return -EINVAL; 454 455 priv_state = ingenic_drm_get_priv_state(priv, state); 456 if (IS_ERR(priv_state)) 457 return PTR_ERR(priv_state); 458 459 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 460 DRM_PLANE_HELPER_NO_SCALING, 461 DRM_PLANE_HELPER_NO_SCALING, 462 priv->soc_info->has_osd, 463 true); 464 if (ret) 465 return ret; 466 467 /* 468 * If OSD is not available, check that the width/height match. 469 * Note that state->src_* are in 16.16 fixed-point format. 470 */ 471 if (!priv->soc_info->has_osd && 472 (new_plane_state->src_x != 0 || 473 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w || 474 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) 475 return -EINVAL; 476 477 priv_state->use_palette = new_plane_state->fb && 478 new_plane_state->fb->format->format == DRM_FORMAT_C8; 479 480 /* 481 * Require full modeset if enabling or disabling a plane, or changing 482 * its position, size or depth. 483 */ 484 if (priv->soc_info->has_osd && 485 (!old_plane_state->fb || !new_plane_state->fb || 486 old_plane_state->crtc_x != new_plane_state->crtc_x || 487 old_plane_state->crtc_y != new_plane_state->crtc_y || 488 old_plane_state->crtc_w != new_plane_state->crtc_w || 489 old_plane_state->crtc_h != new_plane_state->crtc_h || 490 old_plane_state->fb->format->format != new_plane_state->fb->format->format)) 491 crtc_state->mode_changed = true; 492 493 if (priv->soc_info->map_noncoherent) 494 drm_atomic_helper_check_plane_damage(state, new_plane_state); 495 496 return 0; 497 } 498 499 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 500 struct drm_plane *plane) 501 { 502 unsigned int en_bit; 503 504 if (priv->soc_info->has_osd) { 505 if (plane != &priv->f0) 506 en_bit = JZ_LCD_OSDC_F1EN; 507 else 508 en_bit = JZ_LCD_OSDC_F0EN; 509 510 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 511 } 512 } 513 514 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 515 { 516 struct ingenic_drm *priv = dev_get_drvdata(dev); 517 unsigned int en_bit; 518 519 if (priv->soc_info->has_osd) { 520 if (plane != &priv->f0) 521 en_bit = JZ_LCD_OSDC_F1EN; 522 else 523 en_bit = JZ_LCD_OSDC_F0EN; 524 525 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 526 } 527 } 528 529 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 530 struct drm_atomic_state *state) 531 { 532 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 533 534 ingenic_drm_plane_disable(priv->dev, plane); 535 } 536 537 void ingenic_drm_plane_config(struct device *dev, 538 struct drm_plane *plane, u32 fourcc) 539 { 540 struct ingenic_drm *priv = dev_get_drvdata(dev); 541 struct drm_plane_state *state = plane->state; 542 unsigned int xy_reg, size_reg; 543 unsigned int ctrl = 0; 544 545 ingenic_drm_plane_enable(priv, plane); 546 547 if (priv->soc_info->has_osd && plane != &priv->f0) { 548 switch (fourcc) { 549 case DRM_FORMAT_XRGB1555: 550 ctrl |= JZ_LCD_OSDCTRL_RGB555; 551 fallthrough; 552 case DRM_FORMAT_RGB565: 553 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 554 break; 555 case DRM_FORMAT_RGB888: 556 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 557 break; 558 case DRM_FORMAT_XRGB8888: 559 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 560 break; 561 case DRM_FORMAT_XRGB2101010: 562 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 563 break; 564 } 565 566 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 567 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 568 } else { 569 switch (fourcc) { 570 case DRM_FORMAT_C8: 571 ctrl |= JZ_LCD_CTRL_BPP_8; 572 break; 573 case DRM_FORMAT_XRGB1555: 574 ctrl |= JZ_LCD_CTRL_RGB555; 575 fallthrough; 576 case DRM_FORMAT_RGB565: 577 ctrl |= JZ_LCD_CTRL_BPP_15_16; 578 break; 579 case DRM_FORMAT_RGB888: 580 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 581 break; 582 case DRM_FORMAT_XRGB8888: 583 ctrl |= JZ_LCD_CTRL_BPP_18_24; 584 break; 585 case DRM_FORMAT_XRGB2101010: 586 ctrl |= JZ_LCD_CTRL_BPP_30; 587 break; 588 } 589 590 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 591 JZ_LCD_CTRL_BPP_MASK, ctrl); 592 } 593 594 if (priv->soc_info->has_osd) { 595 if (plane != &priv->f0) { 596 xy_reg = JZ_REG_LCD_XYP1; 597 size_reg = JZ_REG_LCD_SIZE1; 598 } else { 599 xy_reg = JZ_REG_LCD_XYP0; 600 size_reg = JZ_REG_LCD_SIZE0; 601 } 602 603 regmap_write(priv->map, xy_reg, 604 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 605 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 606 regmap_write(priv->map, size_reg, 607 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 608 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 609 } 610 } 611 612 bool ingenic_drm_map_noncoherent(const struct device *dev) 613 { 614 const struct ingenic_drm *priv = dev_get_drvdata(dev); 615 616 return priv->soc_info->map_noncoherent; 617 } 618 619 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 620 const struct drm_color_lut *lut) 621 { 622 unsigned int i; 623 624 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 625 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 626 | drm_color_lut_extract(lut[i].green, 6) << 5 627 | drm_color_lut_extract(lut[i].blue, 5); 628 629 priv->dma_hwdescs->palette[i] = color; 630 } 631 } 632 633 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 634 struct drm_atomic_state *state) 635 { 636 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 637 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); 638 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); 639 unsigned int width, height, cpp, next_id, plane_id; 640 struct ingenic_drm_private_state *priv_state; 641 struct drm_crtc_state *crtc_state; 642 struct ingenic_dma_hwdesc *hwdesc; 643 dma_addr_t addr; 644 u32 fourcc; 645 646 if (newstate && newstate->fb) { 647 if (priv->soc_info->map_noncoherent) 648 drm_fb_cma_sync_non_coherent(&priv->drm, oldstate, newstate); 649 650 crtc_state = newstate->crtc->state; 651 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0); 652 653 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0); 654 width = newstate->src_w >> 16; 655 height = newstate->src_h >> 16; 656 cpp = newstate->fb->format->cpp[0]; 657 658 priv_state = ingenic_drm_get_new_priv_state(priv, state); 659 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id; 660 661 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; 662 hwdesc->addr = addr; 663 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 664 hwdesc->next = dma_hwdesc_addr(priv, next_id); 665 666 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 667 fourcc = newstate->fb->format->format; 668 669 ingenic_drm_plane_config(priv->dev, plane, fourcc); 670 671 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 672 } 673 674 if (crtc_state->color_mgmt_changed) 675 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 676 } 677 } 678 679 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 680 struct drm_crtc_state *crtc_state, 681 struct drm_connector_state *conn_state) 682 { 683 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 684 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 685 struct ingenic_drm_bridge *bridge = to_ingenic_drm_bridge(encoder); 686 unsigned int cfg, rgbcfg = 0; 687 688 priv->panel_is_sharp = bridge->bus_cfg.flags & DRM_BUS_FLAG_SHARP_SIGNALS; 689 690 if (priv->panel_is_sharp) { 691 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 692 } else { 693 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 694 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 695 } 696 697 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 698 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 699 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 700 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 701 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_DE_LOW) 702 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 703 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 704 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 705 706 if (!priv->panel_is_sharp) { 707 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) { 708 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 709 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 710 else 711 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 712 } else { 713 switch (bridge->bus_cfg.format) { 714 case MEDIA_BUS_FMT_RGB565_1X16: 715 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 716 break; 717 case MEDIA_BUS_FMT_RGB666_1X18: 718 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 719 break; 720 case MEDIA_BUS_FMT_RGB888_1X24: 721 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 722 break; 723 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 724 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; 725 fallthrough; 726 case MEDIA_BUS_FMT_RGB888_3X8: 727 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 728 break; 729 default: 730 break; 731 } 732 } 733 } 734 735 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 736 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); 737 } 738 739 static int ingenic_drm_bridge_attach(struct drm_bridge *bridge, 740 enum drm_bridge_attach_flags flags) 741 { 742 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder); 743 744 return drm_bridge_attach(bridge->encoder, ib->next_bridge, 745 &ib->bridge, flags); 746 } 747 748 static int ingenic_drm_bridge_atomic_check(struct drm_bridge *bridge, 749 struct drm_bridge_state *bridge_state, 750 struct drm_crtc_state *crtc_state, 751 struct drm_connector_state *conn_state) 752 { 753 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 754 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder); 755 756 ib->bus_cfg = bridge_state->output_bus_cfg; 757 758 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 759 return 0; 760 761 switch (bridge_state->output_bus_cfg.format) { 762 case MEDIA_BUS_FMT_RGB888_3X8: 763 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 764 /* 765 * The LCD controller expects timing values in dot-clock ticks, 766 * which is 3x the timing values in pixels when using a 3x8-bit 767 * display; but it will count the display area size in pixels 768 * either way. Go figure. 769 */ 770 mode->crtc_clock = mode->clock * 3; 771 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2; 772 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2; 773 mode->crtc_hdisplay = mode->hdisplay; 774 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2; 775 return 0; 776 case MEDIA_BUS_FMT_RGB565_1X16: 777 case MEDIA_BUS_FMT_RGB666_1X18: 778 case MEDIA_BUS_FMT_RGB888_1X24: 779 return 0; 780 default: 781 return -EINVAL; 782 } 783 } 784 785 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 786 { 787 struct ingenic_drm *priv = drm_device_get_priv(arg); 788 unsigned int state; 789 790 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 791 792 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 793 JZ_LCD_STATE_EOF_IRQ, 0); 794 795 if (state & JZ_LCD_STATE_EOF_IRQ) 796 drm_crtc_handle_vblank(&priv->crtc); 797 798 return IRQ_HANDLED; 799 } 800 801 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 802 { 803 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 804 805 if (priv->no_vblank) 806 return -EINVAL; 807 808 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 809 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 810 811 return 0; 812 } 813 814 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 815 { 816 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 817 818 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 819 } 820 821 static struct drm_framebuffer * 822 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, 823 const struct drm_mode_fb_cmd2 *mode_cmd) 824 { 825 struct ingenic_drm *priv = drm_device_get_priv(drm); 826 827 if (priv->soc_info->map_noncoherent) 828 return drm_gem_fb_create_with_dirty(drm, file, mode_cmd); 829 830 return drm_gem_fb_create(drm, file, mode_cmd); 831 } 832 833 static struct drm_gem_object * 834 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size) 835 { 836 struct ingenic_drm *priv = drm_device_get_priv(drm); 837 struct drm_gem_cma_object *obj; 838 839 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 840 if (!obj) 841 return ERR_PTR(-ENOMEM); 842 843 obj->map_noncoherent = priv->soc_info->map_noncoherent; 844 845 return &obj->base; 846 } 847 848 static struct drm_private_state * 849 ingenic_drm_duplicate_state(struct drm_private_obj *obj) 850 { 851 struct ingenic_drm_private_state *state = to_ingenic_drm_priv_state(obj->state); 852 853 state = kmemdup(state, sizeof(*state), GFP_KERNEL); 854 if (!state) 855 return NULL; 856 857 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 858 859 return &state->base; 860 } 861 862 static void ingenic_drm_destroy_state(struct drm_private_obj *obj, 863 struct drm_private_state *state) 864 { 865 struct ingenic_drm_private_state *priv_state = to_ingenic_drm_priv_state(state); 866 867 kfree(priv_state); 868 } 869 870 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 871 872 static const struct drm_driver ingenic_drm_driver_data = { 873 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 874 .name = "ingenic-drm", 875 .desc = "DRM module for Ingenic SoCs", 876 .date = "20200716", 877 .major = 1, 878 .minor = 1, 879 .patchlevel = 0, 880 881 .fops = &ingenic_drm_fops, 882 .gem_create_object = ingenic_drm_gem_create_object, 883 DRM_GEM_CMA_DRIVER_OPS, 884 }; 885 886 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 887 .update_plane = drm_atomic_helper_update_plane, 888 .disable_plane = drm_atomic_helper_disable_plane, 889 .reset = drm_atomic_helper_plane_reset, 890 .destroy = drm_plane_cleanup, 891 892 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 893 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 894 }; 895 896 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 897 .set_config = drm_atomic_helper_set_config, 898 .page_flip = drm_atomic_helper_page_flip, 899 .reset = drm_atomic_helper_crtc_reset, 900 .destroy = drm_crtc_cleanup, 901 902 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 903 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 904 905 .enable_vblank = ingenic_drm_enable_vblank, 906 .disable_vblank = ingenic_drm_disable_vblank, 907 }; 908 909 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 910 .atomic_update = ingenic_drm_plane_atomic_update, 911 .atomic_check = ingenic_drm_plane_atomic_check, 912 .atomic_disable = ingenic_drm_plane_atomic_disable, 913 }; 914 915 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 916 .atomic_enable = ingenic_drm_crtc_atomic_enable, 917 .atomic_disable = ingenic_drm_crtc_atomic_disable, 918 .atomic_begin = ingenic_drm_crtc_atomic_begin, 919 .atomic_flush = ingenic_drm_crtc_atomic_flush, 920 .atomic_check = ingenic_drm_crtc_atomic_check, 921 .mode_valid = ingenic_drm_crtc_mode_valid, 922 }; 923 924 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 925 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 926 }; 927 928 static const struct drm_bridge_funcs ingenic_drm_bridge_funcs = { 929 .attach = ingenic_drm_bridge_attach, 930 .atomic_check = ingenic_drm_bridge_atomic_check, 931 .atomic_reset = drm_atomic_helper_bridge_reset, 932 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 933 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 934 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, 935 }; 936 937 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 938 .fb_create = ingenic_drm_gem_fb_create, 939 .output_poll_changed = drm_fb_helper_output_poll_changed, 940 .atomic_check = drm_atomic_helper_check, 941 .atomic_commit = drm_atomic_helper_commit, 942 }; 943 944 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 945 .atomic_commit_tail = drm_atomic_helper_commit_tail, 946 }; 947 948 static const struct drm_private_state_funcs ingenic_drm_private_state_funcs = { 949 .atomic_duplicate_state = ingenic_drm_duplicate_state, 950 .atomic_destroy_state = ingenic_drm_destroy_state, 951 }; 952 953 static void ingenic_drm_unbind_all(void *d) 954 { 955 struct ingenic_drm *priv = d; 956 957 component_unbind_all(priv->dev, &priv->drm); 958 } 959 960 static void __maybe_unused ingenic_drm_release_rmem(void *d) 961 { 962 of_reserved_mem_device_release(d); 963 } 964 965 static void ingenic_drm_configure_hwdesc(struct ingenic_drm *priv, 966 unsigned int hwdesc, 967 unsigned int next_hwdesc, u32 id) 968 { 969 struct ingenic_dma_hwdesc *desc = &priv->dma_hwdescs->hwdesc[hwdesc]; 970 971 desc->next = dma_hwdesc_addr(priv, next_hwdesc); 972 desc->id = id; 973 } 974 975 static void ingenic_drm_configure_hwdesc_palette(struct ingenic_drm *priv) 976 { 977 struct ingenic_dma_hwdesc *desc; 978 979 ingenic_drm_configure_hwdesc(priv, HWDESC_PALETTE, 0, 0xc0); 980 981 desc = &priv->dma_hwdescs->hwdesc[HWDESC_PALETTE]; 982 desc->addr = priv->dma_hwdescs_phys 983 + offsetof(struct ingenic_dma_hwdescs, palette); 984 desc->cmd = JZ_LCD_CMD_ENABLE_PAL 985 | (sizeof(priv->dma_hwdescs->palette) / 4); 986 } 987 988 static void ingenic_drm_configure_hwdesc_plane(struct ingenic_drm *priv, 989 unsigned int plane) 990 { 991 ingenic_drm_configure_hwdesc(priv, plane, plane, 0xf0 | plane); 992 } 993 994 static void ingenic_drm_atomic_private_obj_fini(struct drm_device *drm, void *private_obj) 995 { 996 drm_atomic_private_obj_fini(private_obj); 997 } 998 999 static int ingenic_drm_bind(struct device *dev, bool has_components) 1000 { 1001 struct platform_device *pdev = to_platform_device(dev); 1002 struct ingenic_drm_private_state *private_state; 1003 const struct jz_soc_info *soc_info; 1004 struct ingenic_drm *priv; 1005 struct clk *parent_clk; 1006 struct drm_plane *primary; 1007 struct drm_bridge *bridge; 1008 struct drm_panel *panel; 1009 struct drm_connector *connector; 1010 struct drm_encoder *encoder; 1011 struct ingenic_drm_bridge *ib; 1012 struct drm_device *drm; 1013 void __iomem *base; 1014 long parent_rate; 1015 unsigned int i, clone_mask = 0; 1016 int ret, irq; 1017 1018 soc_info = of_device_get_match_data(dev); 1019 if (!soc_info) { 1020 dev_err(dev, "Missing platform data\n"); 1021 return -EINVAL; 1022 } 1023 1024 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 1025 ret = of_reserved_mem_device_init(dev); 1026 1027 if (ret && ret != -ENODEV) 1028 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 1029 1030 if (!ret) { 1031 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 1032 if (ret) 1033 return ret; 1034 } 1035 } 1036 1037 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 1038 struct ingenic_drm, drm); 1039 if (IS_ERR(priv)) 1040 return PTR_ERR(priv); 1041 1042 priv->soc_info = soc_info; 1043 priv->dev = dev; 1044 drm = &priv->drm; 1045 1046 platform_set_drvdata(pdev, priv); 1047 1048 ret = drmm_mode_config_init(drm); 1049 if (ret) 1050 return ret; 1051 1052 drm->mode_config.min_width = 0; 1053 drm->mode_config.min_height = 0; 1054 drm->mode_config.max_width = soc_info->max_width; 1055 drm->mode_config.max_height = 4095; 1056 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 1057 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 1058 1059 base = devm_platform_ioremap_resource(pdev, 0); 1060 if (IS_ERR(base)) { 1061 dev_err(dev, "Failed to get memory resource\n"); 1062 return PTR_ERR(base); 1063 } 1064 1065 priv->map = devm_regmap_init_mmio(dev, base, 1066 &ingenic_drm_regmap_config); 1067 if (IS_ERR(priv->map)) { 1068 dev_err(dev, "Failed to create regmap\n"); 1069 return PTR_ERR(priv->map); 1070 } 1071 1072 irq = platform_get_irq(pdev, 0); 1073 if (irq < 0) 1074 return irq; 1075 1076 if (soc_info->needs_dev_clk) { 1077 priv->lcd_clk = devm_clk_get(dev, "lcd"); 1078 if (IS_ERR(priv->lcd_clk)) { 1079 dev_err(dev, "Failed to get lcd clock\n"); 1080 return PTR_ERR(priv->lcd_clk); 1081 } 1082 } 1083 1084 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 1085 if (IS_ERR(priv->pix_clk)) { 1086 dev_err(dev, "Failed to get pixel clock\n"); 1087 return PTR_ERR(priv->pix_clk); 1088 } 1089 1090 priv->dma_hwdescs = dmam_alloc_coherent(dev, 1091 sizeof(*priv->dma_hwdescs), 1092 &priv->dma_hwdescs_phys, 1093 GFP_KERNEL); 1094 if (!priv->dma_hwdescs) 1095 return -ENOMEM; 1096 1097 /* Configure DMA hwdesc for foreground0 plane */ 1098 ingenic_drm_configure_hwdesc_plane(priv, 0); 1099 1100 /* Configure DMA hwdesc for foreground1 plane */ 1101 ingenic_drm_configure_hwdesc_plane(priv, 1); 1102 1103 /* Configure DMA hwdesc for palette */ 1104 ingenic_drm_configure_hwdesc_palette(priv); 1105 1106 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0; 1107 1108 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs); 1109 1110 ret = drm_universal_plane_init(drm, primary, 1, 1111 &ingenic_drm_primary_plane_funcs, 1112 priv->soc_info->formats_f1, 1113 priv->soc_info->num_formats_f1, 1114 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1115 if (ret) { 1116 dev_err(dev, "Failed to register plane: %i\n", ret); 1117 return ret; 1118 } 1119 1120 if (soc_info->map_noncoherent) 1121 drm_plane_enable_fb_damage_clips(&priv->f1); 1122 1123 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 1124 1125 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary, 1126 NULL, &ingenic_drm_crtc_funcs, NULL); 1127 if (ret) { 1128 dev_err(dev, "Failed to init CRTC: %i\n", ret); 1129 return ret; 1130 } 1131 1132 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 1133 ARRAY_SIZE(priv->dma_hwdescs->palette)); 1134 1135 if (soc_info->has_osd) { 1136 drm_plane_helper_add(&priv->f0, 1137 &ingenic_drm_plane_helper_funcs); 1138 1139 ret = drm_universal_plane_init(drm, &priv->f0, 1, 1140 &ingenic_drm_primary_plane_funcs, 1141 priv->soc_info->formats_f0, 1142 priv->soc_info->num_formats_f0, 1143 NULL, DRM_PLANE_TYPE_OVERLAY, 1144 NULL); 1145 if (ret) { 1146 dev_err(dev, "Failed to register overlay plane: %i\n", 1147 ret); 1148 return ret; 1149 } 1150 1151 if (soc_info->map_noncoherent) 1152 drm_plane_enable_fb_damage_clips(&priv->f0); 1153 1154 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 1155 ret = component_bind_all(dev, drm); 1156 if (ret) { 1157 if (ret != -EPROBE_DEFER) 1158 dev_err(dev, "Failed to bind components: %i\n", ret); 1159 return ret; 1160 } 1161 1162 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 1163 if (ret) 1164 return ret; 1165 1166 priv->ipu_plane = drm_plane_from_index(drm, 2); 1167 if (!priv->ipu_plane) { 1168 dev_err(dev, "Failed to retrieve IPU plane\n"); 1169 return -EINVAL; 1170 } 1171 } 1172 } 1173 1174 for (i = 0; ; i++) { 1175 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 1176 if (ret) { 1177 if (ret == -ENODEV) 1178 break; /* we're done */ 1179 if (ret != -EPROBE_DEFER) 1180 dev_err(dev, "Failed to get bridge handle\n"); 1181 return ret; 1182 } 1183 1184 if (panel) 1185 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 1186 DRM_MODE_CONNECTOR_DPI); 1187 1188 ib = drmm_encoder_alloc(drm, struct ingenic_drm_bridge, encoder, 1189 NULL, DRM_MODE_ENCODER_DPI, NULL); 1190 if (IS_ERR(ib)) { 1191 ret = PTR_ERR(ib); 1192 dev_err(dev, "Failed to init encoder: %d\n", ret); 1193 return ret; 1194 } 1195 1196 encoder = &ib->encoder; 1197 encoder->possible_crtcs = drm_crtc_mask(&priv->crtc); 1198 1199 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1200 1201 ib->bridge.funcs = &ingenic_drm_bridge_funcs; 1202 ib->next_bridge = bridge; 1203 1204 ret = drm_bridge_attach(encoder, &ib->bridge, NULL, 1205 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1206 if (ret) { 1207 dev_err(dev, "Unable to attach bridge\n"); 1208 return ret; 1209 } 1210 1211 connector = drm_bridge_connector_init(drm, encoder); 1212 if (IS_ERR(connector)) { 1213 dev_err(dev, "Unable to init connector\n"); 1214 return PTR_ERR(connector); 1215 } 1216 1217 drm_connector_attach_encoder(connector, encoder); 1218 } 1219 1220 drm_for_each_encoder(encoder, drm) { 1221 clone_mask |= BIT(drm_encoder_index(encoder)); 1222 } 1223 1224 drm_for_each_encoder(encoder, drm) { 1225 encoder->possible_clones = clone_mask; 1226 } 1227 1228 ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm); 1229 if (ret) { 1230 dev_err(dev, "Unable to install IRQ handler\n"); 1231 return ret; 1232 } 1233 1234 ret = drm_vblank_init(drm, 1); 1235 if (ret) { 1236 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1237 return ret; 1238 } 1239 1240 drm_mode_config_reset(drm); 1241 1242 ret = clk_prepare_enable(priv->pix_clk); 1243 if (ret) { 1244 dev_err(dev, "Unable to start pixel clock\n"); 1245 return ret; 1246 } 1247 1248 if (priv->lcd_clk) { 1249 parent_clk = clk_get_parent(priv->lcd_clk); 1250 parent_rate = clk_get_rate(parent_clk); 1251 1252 /* LCD Device clock must be 3x the pixel clock for STN panels, 1253 * or 1.5x the pixel clock for TFT panels. To avoid having to 1254 * check for the LCD device clock everytime we do a mode change, 1255 * we set the LCD device clock to the highest rate possible. 1256 */ 1257 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1258 if (ret) { 1259 dev_err(dev, "Unable to set LCD clock rate\n"); 1260 goto err_pixclk_disable; 1261 } 1262 1263 ret = clk_prepare_enable(priv->lcd_clk); 1264 if (ret) { 1265 dev_err(dev, "Unable to start lcd clock\n"); 1266 goto err_pixclk_disable; 1267 } 1268 } 1269 1270 /* Enable OSD if available */ 1271 if (soc_info->has_osd) 1272 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); 1273 1274 mutex_init(&priv->clk_mutex); 1275 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1276 1277 parent_clk = clk_get_parent(priv->pix_clk); 1278 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1279 if (ret) { 1280 dev_err(dev, "Unable to register clock notifier\n"); 1281 goto err_devclk_disable; 1282 } 1283 1284 private_state = kzalloc(sizeof(*private_state), GFP_KERNEL); 1285 if (!private_state) { 1286 ret = -ENOMEM; 1287 goto err_clk_notifier_unregister; 1288 } 1289 1290 drm_atomic_private_obj_init(drm, &priv->private_obj, &private_state->base, 1291 &ingenic_drm_private_state_funcs); 1292 1293 ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini, 1294 &priv->private_obj); 1295 if (ret) 1296 goto err_private_state_free; 1297 1298 ret = drm_dev_register(drm, 0); 1299 if (ret) { 1300 dev_err(dev, "Failed to register DRM driver\n"); 1301 goto err_clk_notifier_unregister; 1302 } 1303 1304 drm_fbdev_generic_setup(drm, 32); 1305 1306 return 0; 1307 1308 err_private_state_free: 1309 kfree(private_state); 1310 err_clk_notifier_unregister: 1311 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1312 err_devclk_disable: 1313 if (priv->lcd_clk) 1314 clk_disable_unprepare(priv->lcd_clk); 1315 err_pixclk_disable: 1316 clk_disable_unprepare(priv->pix_clk); 1317 return ret; 1318 } 1319 1320 static int ingenic_drm_bind_with_components(struct device *dev) 1321 { 1322 return ingenic_drm_bind(dev, true); 1323 } 1324 1325 static int compare_of(struct device *dev, void *data) 1326 { 1327 return dev->of_node == data; 1328 } 1329 1330 static void ingenic_drm_unbind(struct device *dev) 1331 { 1332 struct ingenic_drm *priv = dev_get_drvdata(dev); 1333 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1334 1335 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1336 if (priv->lcd_clk) 1337 clk_disable_unprepare(priv->lcd_clk); 1338 clk_disable_unprepare(priv->pix_clk); 1339 1340 drm_dev_unregister(&priv->drm); 1341 drm_atomic_helper_shutdown(&priv->drm); 1342 } 1343 1344 static const struct component_master_ops ingenic_master_ops = { 1345 .bind = ingenic_drm_bind_with_components, 1346 .unbind = ingenic_drm_unbind, 1347 }; 1348 1349 static int ingenic_drm_probe(struct platform_device *pdev) 1350 { 1351 struct device *dev = &pdev->dev; 1352 struct component_match *match = NULL; 1353 struct device_node *np; 1354 1355 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1356 return ingenic_drm_bind(dev, false); 1357 1358 /* IPU is at port address 8 */ 1359 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1360 if (!np) 1361 return ingenic_drm_bind(dev, false); 1362 1363 drm_of_component_match_add(dev, &match, compare_of, np); 1364 of_node_put(np); 1365 1366 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1367 } 1368 1369 static int ingenic_drm_remove(struct platform_device *pdev) 1370 { 1371 struct device *dev = &pdev->dev; 1372 1373 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1374 ingenic_drm_unbind(dev); 1375 else 1376 component_master_del(dev, &ingenic_master_ops); 1377 1378 return 0; 1379 } 1380 1381 static int __maybe_unused ingenic_drm_suspend(struct device *dev) 1382 { 1383 struct ingenic_drm *priv = dev_get_drvdata(dev); 1384 1385 return drm_mode_config_helper_suspend(&priv->drm); 1386 } 1387 1388 static int __maybe_unused ingenic_drm_resume(struct device *dev) 1389 { 1390 struct ingenic_drm *priv = dev_get_drvdata(dev); 1391 1392 return drm_mode_config_helper_resume(&priv->drm); 1393 } 1394 1395 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume); 1396 1397 static const u32 jz4740_formats[] = { 1398 DRM_FORMAT_XRGB1555, 1399 DRM_FORMAT_RGB565, 1400 DRM_FORMAT_XRGB8888, 1401 }; 1402 1403 static const u32 jz4725b_formats_f1[] = { 1404 DRM_FORMAT_XRGB1555, 1405 DRM_FORMAT_RGB565, 1406 DRM_FORMAT_XRGB8888, 1407 }; 1408 1409 static const u32 jz4725b_formats_f0[] = { 1410 DRM_FORMAT_C8, 1411 DRM_FORMAT_XRGB1555, 1412 DRM_FORMAT_RGB565, 1413 DRM_FORMAT_XRGB8888, 1414 }; 1415 1416 static const u32 jz4770_formats_f1[] = { 1417 DRM_FORMAT_XRGB1555, 1418 DRM_FORMAT_RGB565, 1419 DRM_FORMAT_RGB888, 1420 DRM_FORMAT_XRGB8888, 1421 DRM_FORMAT_XRGB2101010, 1422 }; 1423 1424 static const u32 jz4770_formats_f0[] = { 1425 DRM_FORMAT_C8, 1426 DRM_FORMAT_XRGB1555, 1427 DRM_FORMAT_RGB565, 1428 DRM_FORMAT_RGB888, 1429 DRM_FORMAT_XRGB8888, 1430 DRM_FORMAT_XRGB2101010, 1431 }; 1432 1433 static const struct jz_soc_info jz4740_soc_info = { 1434 .needs_dev_clk = true, 1435 .has_osd = false, 1436 .map_noncoherent = false, 1437 .max_width = 800, 1438 .max_height = 600, 1439 .formats_f1 = jz4740_formats, 1440 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1441 /* JZ4740 has only one plane */ 1442 }; 1443 1444 static const struct jz_soc_info jz4725b_soc_info = { 1445 .needs_dev_clk = false, 1446 .has_osd = true, 1447 .map_noncoherent = false, 1448 .max_width = 800, 1449 .max_height = 600, 1450 .formats_f1 = jz4725b_formats_f1, 1451 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1452 .formats_f0 = jz4725b_formats_f0, 1453 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1454 }; 1455 1456 static const struct jz_soc_info jz4770_soc_info = { 1457 .needs_dev_clk = false, 1458 .has_osd = true, 1459 .map_noncoherent = true, 1460 .max_width = 1280, 1461 .max_height = 720, 1462 .formats_f1 = jz4770_formats_f1, 1463 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1464 .formats_f0 = jz4770_formats_f0, 1465 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1466 }; 1467 1468 static const struct of_device_id ingenic_drm_of_match[] = { 1469 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1470 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1471 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1472 { /* sentinel */ }, 1473 }; 1474 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1475 1476 static struct platform_driver ingenic_drm_driver = { 1477 .driver = { 1478 .name = "ingenic-drm", 1479 .pm = pm_ptr(&ingenic_drm_pm_ops), 1480 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1481 }, 1482 .probe = ingenic_drm_probe, 1483 .remove = ingenic_drm_remove, 1484 }; 1485 1486 static int ingenic_drm_init(void) 1487 { 1488 int err; 1489 1490 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1491 err = platform_driver_register(ingenic_ipu_driver_ptr); 1492 if (err) 1493 return err; 1494 } 1495 1496 return platform_driver_register(&ingenic_drm_driver); 1497 } 1498 module_init(ingenic_drm_init); 1499 1500 static void ingenic_drm_exit(void) 1501 { 1502 platform_driver_unregister(&ingenic_drm_driver); 1503 1504 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1505 platform_driver_unregister(ingenic_ipu_driver_ptr); 1506 } 1507 module_exit(ingenic_drm_exit); 1508 1509 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1510 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1511 MODULE_LICENSE("GPL v2"); 1512