1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/bitfield.h> 10 #include <linux/component.h> 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/regmap.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_bridge_connector.h> 26 #include <drm/drm_color_mgmt.h> 27 #include <drm/drm_crtc.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_damage_helper.h> 30 #include <drm/drm_drv.h> 31 #include <drm/drm_encoder.h> 32 #include <drm/drm_gem_cma_helper.h> 33 #include <drm/drm_fb_cma_helper.h> 34 #include <drm/drm_fb_helper.h> 35 #include <drm/drm_fourcc.h> 36 #include <drm/drm_gem_atomic_helper.h> 37 #include <drm/drm_gem_framebuffer_helper.h> 38 #include <drm/drm_managed.h> 39 #include <drm/drm_of.h> 40 #include <drm/drm_panel.h> 41 #include <drm/drm_plane.h> 42 #include <drm/drm_plane_helper.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_vblank.h> 45 46 #define HWDESC_PALETTE 2 47 48 struct ingenic_dma_hwdesc { 49 u32 next; 50 u32 addr; 51 u32 id; 52 u32 cmd; 53 /* extended hw descriptor for jz4780 */ 54 u32 offsize; 55 u32 pagewidth; 56 u32 cpos; 57 u32 dessize; 58 } __aligned(16); 59 60 struct ingenic_dma_hwdescs { 61 struct ingenic_dma_hwdesc hwdesc[3]; 62 u16 palette[256] __aligned(16); 63 }; 64 65 struct jz_soc_info { 66 bool needs_dev_clk; 67 bool has_osd; 68 bool has_alpha; 69 bool map_noncoherent; 70 bool use_extended_hwdesc; 71 bool plane_f0_not_working; 72 unsigned int max_width, max_height; 73 const u32 *formats_f0, *formats_f1; 74 unsigned int num_formats_f0, num_formats_f1; 75 }; 76 77 struct ingenic_drm_private_state { 78 struct drm_private_state base; 79 bool use_palette; 80 }; 81 82 struct ingenic_drm { 83 struct drm_device drm; 84 /* 85 * f1 (aka. foreground1) is our primary plane, on top of which 86 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 87 * hardware and cannot be changed. 88 */ 89 struct drm_plane f0, f1, *ipu_plane; 90 struct drm_crtc crtc; 91 92 struct device *dev; 93 struct regmap *map; 94 struct clk *lcd_clk, *pix_clk; 95 const struct jz_soc_info *soc_info; 96 97 struct ingenic_dma_hwdescs *dma_hwdescs; 98 dma_addr_t dma_hwdescs_phys; 99 100 bool panel_is_sharp; 101 bool no_vblank; 102 103 /* 104 * clk_mutex is used to synchronize the pixel clock rate update with 105 * the VBLANK. When the pixel clock's parent clock needs to be updated, 106 * clock_nb's notifier function will lock the mutex, then wait until the 107 * next VBLANK. At that point, the parent clock's rate can be updated, 108 * and the mutex is then unlocked. If an atomic commit happens in the 109 * meantime, it will lock on the mutex, effectively waiting until the 110 * clock update process finishes. Finally, the pixel clock's rate will 111 * be recomputed when the mutex has been released, in the pending atomic 112 * commit, or a future one. 113 */ 114 struct mutex clk_mutex; 115 bool update_clk_rate; 116 struct notifier_block clock_nb; 117 118 struct drm_private_obj private_obj; 119 }; 120 121 struct ingenic_drm_bridge { 122 struct drm_encoder encoder; 123 struct drm_bridge bridge, *next_bridge; 124 125 struct drm_bus_cfg bus_cfg; 126 }; 127 128 static inline struct ingenic_drm_bridge * 129 to_ingenic_drm_bridge(struct drm_encoder *encoder) 130 { 131 return container_of(encoder, struct ingenic_drm_bridge, encoder); 132 } 133 134 static inline struct ingenic_drm_private_state * 135 to_ingenic_drm_priv_state(struct drm_private_state *state) 136 { 137 return container_of(state, struct ingenic_drm_private_state, base); 138 } 139 140 static struct ingenic_drm_private_state * 141 ingenic_drm_get_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 142 { 143 struct drm_private_state *priv_state; 144 145 priv_state = drm_atomic_get_private_obj_state(state, &priv->private_obj); 146 if (IS_ERR(priv_state)) 147 return ERR_CAST(priv_state); 148 149 return to_ingenic_drm_priv_state(priv_state); 150 } 151 152 static struct ingenic_drm_private_state * 153 ingenic_drm_get_new_priv_state(struct ingenic_drm *priv, struct drm_atomic_state *state) 154 { 155 struct drm_private_state *priv_state; 156 157 priv_state = drm_atomic_get_new_private_obj_state(state, &priv->private_obj); 158 if (!priv_state) 159 return NULL; 160 161 return to_ingenic_drm_priv_state(priv_state); 162 } 163 164 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 165 { 166 switch (reg) { 167 case JZ_REG_LCD_IID: 168 case JZ_REG_LCD_SA0: 169 case JZ_REG_LCD_FID0: 170 case JZ_REG_LCD_CMD0: 171 case JZ_REG_LCD_SA1: 172 case JZ_REG_LCD_FID1: 173 case JZ_REG_LCD_CMD1: 174 return false; 175 default: 176 return true; 177 } 178 } 179 180 static const struct regmap_config ingenic_drm_regmap_config = { 181 .reg_bits = 32, 182 .val_bits = 32, 183 .reg_stride = 4, 184 185 .writeable_reg = ingenic_drm_writeable_reg, 186 }; 187 188 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 189 { 190 return container_of(drm, struct ingenic_drm, drm); 191 } 192 193 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 194 { 195 return container_of(crtc, struct ingenic_drm, crtc); 196 } 197 198 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 199 { 200 return container_of(nb, struct ingenic_drm, clock_nb); 201 } 202 203 static inline dma_addr_t dma_hwdesc_addr(const struct ingenic_drm *priv, 204 unsigned int idx) 205 { 206 u32 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc[idx]); 207 208 return priv->dma_hwdescs_phys + offset; 209 } 210 211 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 212 unsigned long action, 213 void *data) 214 { 215 struct ingenic_drm *priv = drm_nb_get_priv(nb); 216 217 switch (action) { 218 case PRE_RATE_CHANGE: 219 mutex_lock(&priv->clk_mutex); 220 priv->update_clk_rate = true; 221 drm_crtc_wait_one_vblank(&priv->crtc); 222 return NOTIFY_OK; 223 default: 224 mutex_unlock(&priv->clk_mutex); 225 return NOTIFY_OK; 226 } 227 } 228 229 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 230 struct drm_atomic_state *state) 231 { 232 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 233 struct ingenic_drm_private_state *priv_state; 234 unsigned int next_id; 235 236 priv_state = ingenic_drm_get_priv_state(priv, state); 237 if (WARN_ON(IS_ERR(priv_state))) 238 return; 239 240 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 241 242 /* Set addresses of our DMA descriptor chains */ 243 next_id = priv_state->use_palette ? HWDESC_PALETTE : 0; 244 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, next_id)); 245 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); 246 247 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 248 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 249 JZ_LCD_CTRL_ENABLE); 250 251 drm_crtc_vblank_on(crtc); 252 } 253 254 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 255 struct drm_atomic_state *state) 256 { 257 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 258 unsigned int var; 259 260 drm_crtc_vblank_off(crtc); 261 262 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 263 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 264 265 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 266 var & JZ_LCD_STATE_DISABLED, 267 1000, 0); 268 } 269 270 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 271 struct drm_display_mode *mode) 272 { 273 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 274 275 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start; 276 vds = mode->crtc_vtotal - mode->crtc_vsync_start; 277 vde = vds + mode->crtc_vdisplay; 278 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay; 279 280 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start; 281 hds = mode->crtc_htotal - mode->crtc_hsync_start; 282 hde = hds + mode->crtc_hdisplay; 283 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay; 284 285 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 286 0 << JZ_LCD_VSYNC_VPS_OFFSET | 287 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 288 289 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 290 0 << JZ_LCD_HSYNC_HPS_OFFSET | 291 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 292 293 regmap_write(priv->map, JZ_REG_LCD_VAT, 294 ht << JZ_LCD_VAT_HT_OFFSET | 295 vt << JZ_LCD_VAT_VT_OFFSET); 296 297 regmap_write(priv->map, JZ_REG_LCD_DAH, 298 hds << JZ_LCD_DAH_HDS_OFFSET | 299 hde << JZ_LCD_DAH_HDE_OFFSET); 300 regmap_write(priv->map, JZ_REG_LCD_DAV, 301 vds << JZ_LCD_DAV_VDS_OFFSET | 302 vde << JZ_LCD_DAV_VDE_OFFSET); 303 304 if (priv->panel_is_sharp) { 305 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 306 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 307 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 308 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 309 } 310 311 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 312 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 313 314 /* 315 * IPU restart - specify how much time the LCDC will wait before 316 * transferring a new frame from the IPU. The value is the one 317 * suggested in the programming manual. 318 */ 319 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 320 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 321 } 322 323 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 324 struct drm_atomic_state *state) 325 { 326 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 327 crtc); 328 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 329 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 330 331 if (crtc_state->gamma_lut && 332 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 333 dev_dbg(priv->dev, "Invalid palette size\n"); 334 return -EINVAL; 335 } 336 337 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 338 f1_state = drm_atomic_get_plane_state(crtc_state->state, 339 &priv->f1); 340 if (IS_ERR(f1_state)) 341 return PTR_ERR(f1_state); 342 343 f0_state = drm_atomic_get_plane_state(crtc_state->state, 344 &priv->f0); 345 if (IS_ERR(f0_state)) 346 return PTR_ERR(f0_state); 347 348 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 349 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 350 priv->ipu_plane); 351 if (IS_ERR(ipu_state)) 352 return PTR_ERR(ipu_state); 353 354 /* IPU and F1 planes cannot be enabled at the same time. */ 355 if (f1_state->fb && ipu_state->fb) { 356 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 357 return -EINVAL; 358 } 359 } 360 361 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 362 priv->no_vblank = !f1_state->fb && !f0_state->fb && 363 !(ipu_state && ipu_state->fb); 364 } 365 366 return 0; 367 } 368 369 static enum drm_mode_status 370 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 371 { 372 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 373 long rate; 374 375 if (mode->hdisplay > priv->soc_info->max_width) 376 return MODE_BAD_HVALUE; 377 if (mode->vdisplay > priv->soc_info->max_height) 378 return MODE_BAD_VVALUE; 379 380 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 381 if (rate < 0) 382 return MODE_CLOCK_RANGE; 383 384 return MODE_OK; 385 } 386 387 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 388 struct drm_atomic_state *state) 389 { 390 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 391 crtc); 392 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 393 u32 ctrl = 0; 394 395 if (priv->soc_info->has_osd && 396 drm_atomic_crtc_needs_modeset(crtc_state)) { 397 /* 398 * If IPU plane is enabled, enable IPU as source for the F1 399 * plane; otherwise use regular DMA. 400 */ 401 if (priv->ipu_plane && priv->ipu_plane->state->fb) 402 ctrl |= JZ_LCD_OSDCTRL_IPU; 403 404 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 405 JZ_LCD_OSDCTRL_IPU, ctrl); 406 } 407 } 408 409 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 410 struct drm_atomic_state *state) 411 { 412 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 413 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 414 crtc); 415 struct drm_pending_vblank_event *event = crtc_state->event; 416 417 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 418 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode); 419 priv->update_clk_rate = true; 420 } 421 422 if (priv->update_clk_rate) { 423 mutex_lock(&priv->clk_mutex); 424 clk_set_rate(priv->pix_clk, 425 crtc_state->adjusted_mode.crtc_clock * 1000); 426 priv->update_clk_rate = false; 427 mutex_unlock(&priv->clk_mutex); 428 } 429 430 if (event) { 431 crtc_state->event = NULL; 432 433 spin_lock_irq(&crtc->dev->event_lock); 434 if (drm_crtc_vblank_get(crtc) == 0) 435 drm_crtc_arm_vblank_event(crtc, event); 436 else 437 drm_crtc_send_vblank_event(crtc, event); 438 spin_unlock_irq(&crtc->dev->event_lock); 439 } 440 } 441 442 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 443 struct drm_atomic_state *state) 444 { 445 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 446 plane); 447 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 448 plane); 449 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 450 struct ingenic_drm_private_state *priv_state; 451 struct drm_crtc_state *crtc_state; 452 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 453 int ret; 454 455 if (!crtc) 456 return 0; 457 458 if (priv->soc_info->plane_f0_not_working && plane == &priv->f0) 459 return -EINVAL; 460 461 crtc_state = drm_atomic_get_existing_crtc_state(state, 462 crtc); 463 if (WARN_ON(!crtc_state)) 464 return -EINVAL; 465 466 priv_state = ingenic_drm_get_priv_state(priv, state); 467 if (IS_ERR(priv_state)) 468 return PTR_ERR(priv_state); 469 470 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 471 DRM_PLANE_HELPER_NO_SCALING, 472 DRM_PLANE_HELPER_NO_SCALING, 473 priv->soc_info->has_osd, 474 true); 475 if (ret) 476 return ret; 477 478 /* 479 * If OSD is not available, check that the width/height match. 480 * Note that state->src_* are in 16.16 fixed-point format. 481 */ 482 if (!priv->soc_info->has_osd && 483 (new_plane_state->src_x != 0 || 484 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w || 485 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) 486 return -EINVAL; 487 488 priv_state->use_palette = new_plane_state->fb && 489 new_plane_state->fb->format->format == DRM_FORMAT_C8; 490 491 /* 492 * Require full modeset if enabling or disabling a plane, or changing 493 * its position, size or depth. 494 */ 495 if (priv->soc_info->has_osd && 496 (!old_plane_state->fb || !new_plane_state->fb || 497 old_plane_state->crtc_x != new_plane_state->crtc_x || 498 old_plane_state->crtc_y != new_plane_state->crtc_y || 499 old_plane_state->crtc_w != new_plane_state->crtc_w || 500 old_plane_state->crtc_h != new_plane_state->crtc_h || 501 old_plane_state->fb->format->format != new_plane_state->fb->format->format)) 502 crtc_state->mode_changed = true; 503 504 if (priv->soc_info->map_noncoherent) 505 drm_atomic_helper_check_plane_damage(state, new_plane_state); 506 507 return 0; 508 } 509 510 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 511 struct drm_plane *plane) 512 { 513 unsigned int en_bit; 514 515 if (priv->soc_info->has_osd) { 516 if (plane != &priv->f0) 517 en_bit = JZ_LCD_OSDC_F1EN; 518 else 519 en_bit = JZ_LCD_OSDC_F0EN; 520 521 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 522 } 523 } 524 525 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 526 { 527 struct ingenic_drm *priv = dev_get_drvdata(dev); 528 unsigned int en_bit; 529 530 if (priv->soc_info->has_osd) { 531 if (plane != &priv->f0) 532 en_bit = JZ_LCD_OSDC_F1EN; 533 else 534 en_bit = JZ_LCD_OSDC_F0EN; 535 536 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 537 } 538 } 539 540 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 541 struct drm_atomic_state *state) 542 { 543 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 544 545 ingenic_drm_plane_disable(priv->dev, plane); 546 } 547 548 void ingenic_drm_plane_config(struct device *dev, 549 struct drm_plane *plane, u32 fourcc) 550 { 551 struct ingenic_drm *priv = dev_get_drvdata(dev); 552 struct drm_plane_state *state = plane->state; 553 unsigned int xy_reg, size_reg; 554 unsigned int ctrl = 0; 555 556 ingenic_drm_plane_enable(priv, plane); 557 558 if (priv->soc_info->has_osd && plane != &priv->f0) { 559 switch (fourcc) { 560 case DRM_FORMAT_XRGB1555: 561 ctrl |= JZ_LCD_OSDCTRL_RGB555; 562 fallthrough; 563 case DRM_FORMAT_RGB565: 564 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 565 break; 566 case DRM_FORMAT_RGB888: 567 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 568 break; 569 case DRM_FORMAT_XRGB8888: 570 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 571 break; 572 case DRM_FORMAT_XRGB2101010: 573 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 574 break; 575 } 576 577 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 578 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 579 } else { 580 switch (fourcc) { 581 case DRM_FORMAT_C8: 582 ctrl |= JZ_LCD_CTRL_BPP_8; 583 break; 584 case DRM_FORMAT_XRGB1555: 585 ctrl |= JZ_LCD_CTRL_RGB555; 586 fallthrough; 587 case DRM_FORMAT_RGB565: 588 ctrl |= JZ_LCD_CTRL_BPP_15_16; 589 break; 590 case DRM_FORMAT_RGB888: 591 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 592 break; 593 case DRM_FORMAT_XRGB8888: 594 ctrl |= JZ_LCD_CTRL_BPP_18_24; 595 break; 596 case DRM_FORMAT_XRGB2101010: 597 ctrl |= JZ_LCD_CTRL_BPP_30; 598 break; 599 } 600 601 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 602 JZ_LCD_CTRL_BPP_MASK, ctrl); 603 } 604 605 if (priv->soc_info->has_osd) { 606 if (plane != &priv->f0) { 607 xy_reg = JZ_REG_LCD_XYP1; 608 size_reg = JZ_REG_LCD_SIZE1; 609 } else { 610 xy_reg = JZ_REG_LCD_XYP0; 611 size_reg = JZ_REG_LCD_SIZE0; 612 } 613 614 regmap_write(priv->map, xy_reg, 615 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 616 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 617 regmap_write(priv->map, size_reg, 618 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 619 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 620 } 621 } 622 623 bool ingenic_drm_map_noncoherent(const struct device *dev) 624 { 625 const struct ingenic_drm *priv = dev_get_drvdata(dev); 626 627 return priv->soc_info->map_noncoherent; 628 } 629 630 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 631 const struct drm_color_lut *lut) 632 { 633 unsigned int i; 634 635 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 636 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 637 | drm_color_lut_extract(lut[i].green, 6) << 5 638 | drm_color_lut_extract(lut[i].blue, 5); 639 640 priv->dma_hwdescs->palette[i] = color; 641 } 642 } 643 644 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 645 struct drm_atomic_state *state) 646 { 647 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 648 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, plane); 649 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, plane); 650 unsigned int width, height, cpp, next_id, plane_id; 651 struct ingenic_drm_private_state *priv_state; 652 struct drm_crtc_state *crtc_state; 653 struct ingenic_dma_hwdesc *hwdesc; 654 dma_addr_t addr; 655 u32 fourcc; 656 657 if (newstate && newstate->fb) { 658 if (priv->soc_info->map_noncoherent) 659 drm_fb_cma_sync_non_coherent(&priv->drm, oldstate, newstate); 660 661 crtc_state = newstate->crtc->state; 662 plane_id = !!(priv->soc_info->has_osd && plane != &priv->f0); 663 664 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0); 665 width = newstate->src_w >> 16; 666 height = newstate->src_h >> 16; 667 cpp = newstate->fb->format->cpp[0]; 668 669 priv_state = ingenic_drm_get_new_priv_state(priv, state); 670 next_id = (priv_state && priv_state->use_palette) ? HWDESC_PALETTE : plane_id; 671 672 hwdesc = &priv->dma_hwdescs->hwdesc[plane_id]; 673 hwdesc->addr = addr; 674 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 675 hwdesc->next = dma_hwdesc_addr(priv, next_id); 676 677 if (priv->soc_info->use_extended_hwdesc) { 678 hwdesc->cmd |= JZ_LCD_CMD_FRM_ENABLE; 679 680 /* Extended 8-byte descriptor */ 681 hwdesc->cpos = 0; 682 hwdesc->offsize = 0; 683 hwdesc->pagewidth = 0; 684 685 switch (newstate->fb->format->format) { 686 case DRM_FORMAT_XRGB1555: 687 hwdesc->cpos |= JZ_LCD_CPOS_RGB555; 688 fallthrough; 689 case DRM_FORMAT_RGB565: 690 hwdesc->cpos |= JZ_LCD_CPOS_BPP_15_16; 691 break; 692 case DRM_FORMAT_XRGB8888: 693 hwdesc->cpos |= JZ_LCD_CPOS_BPP_18_24; 694 break; 695 } 696 hwdesc->cpos |= (JZ_LCD_CPOS_COEFFICIENT_1 << 697 JZ_LCD_CPOS_COEFFICIENT_OFFSET); 698 hwdesc->dessize = 699 (0xff << JZ_LCD_DESSIZE_ALPHA_OFFSET) | 700 FIELD_PREP(JZ_LCD_DESSIZE_HEIGHT_MASK, height - 1) | 701 FIELD_PREP(JZ_LCD_DESSIZE_WIDTH_MASK, width - 1); 702 } 703 704 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 705 fourcc = newstate->fb->format->format; 706 707 ingenic_drm_plane_config(priv->dev, plane, fourcc); 708 709 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 710 } 711 712 if (crtc_state->color_mgmt_changed) 713 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 714 } 715 } 716 717 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 718 struct drm_crtc_state *crtc_state, 719 struct drm_connector_state *conn_state) 720 { 721 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 722 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 723 struct ingenic_drm_bridge *bridge = to_ingenic_drm_bridge(encoder); 724 unsigned int cfg, rgbcfg = 0; 725 726 priv->panel_is_sharp = bridge->bus_cfg.flags & DRM_BUS_FLAG_SHARP_SIGNALS; 727 728 if (priv->panel_is_sharp) { 729 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 730 } else { 731 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 732 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 733 } 734 735 if (priv->soc_info->use_extended_hwdesc) 736 cfg |= JZ_LCD_CFG_DESCRIPTOR_8; 737 738 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 739 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 740 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 741 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 742 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_DE_LOW) 743 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 744 if (bridge->bus_cfg.flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 745 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 746 747 if (!priv->panel_is_sharp) { 748 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) { 749 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 750 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 751 else 752 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 753 } else { 754 switch (bridge->bus_cfg.format) { 755 case MEDIA_BUS_FMT_RGB565_1X16: 756 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 757 break; 758 case MEDIA_BUS_FMT_RGB666_1X18: 759 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 760 break; 761 case MEDIA_BUS_FMT_RGB888_1X24: 762 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 763 break; 764 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 765 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; 766 fallthrough; 767 case MEDIA_BUS_FMT_RGB888_3X8: 768 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 769 break; 770 default: 771 break; 772 } 773 } 774 } 775 776 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 777 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); 778 } 779 780 static int ingenic_drm_bridge_attach(struct drm_bridge *bridge, 781 enum drm_bridge_attach_flags flags) 782 { 783 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder); 784 785 return drm_bridge_attach(bridge->encoder, ib->next_bridge, 786 &ib->bridge, flags); 787 } 788 789 static int ingenic_drm_bridge_atomic_check(struct drm_bridge *bridge, 790 struct drm_bridge_state *bridge_state, 791 struct drm_crtc_state *crtc_state, 792 struct drm_connector_state *conn_state) 793 { 794 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 795 struct ingenic_drm_bridge *ib = to_ingenic_drm_bridge(bridge->encoder); 796 797 ib->bus_cfg = bridge_state->output_bus_cfg; 798 799 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 800 return 0; 801 802 switch (bridge_state->output_bus_cfg.format) { 803 case MEDIA_BUS_FMT_RGB888_3X8: 804 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 805 /* 806 * The LCD controller expects timing values in dot-clock ticks, 807 * which is 3x the timing values in pixels when using a 3x8-bit 808 * display; but it will count the display area size in pixels 809 * either way. Go figure. 810 */ 811 mode->crtc_clock = mode->clock * 3; 812 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2; 813 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2; 814 mode->crtc_hdisplay = mode->hdisplay; 815 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2; 816 return 0; 817 case MEDIA_BUS_FMT_RGB565_1X16: 818 case MEDIA_BUS_FMT_RGB666_1X18: 819 case MEDIA_BUS_FMT_RGB888_1X24: 820 return 0; 821 default: 822 return -EINVAL; 823 } 824 } 825 826 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 827 { 828 struct ingenic_drm *priv = drm_device_get_priv(arg); 829 unsigned int state; 830 831 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 832 833 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 834 JZ_LCD_STATE_EOF_IRQ, 0); 835 836 if (state & JZ_LCD_STATE_EOF_IRQ) 837 drm_crtc_handle_vblank(&priv->crtc); 838 839 return IRQ_HANDLED; 840 } 841 842 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 843 { 844 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 845 846 if (priv->no_vblank) 847 return -EINVAL; 848 849 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 850 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 851 852 return 0; 853 } 854 855 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 856 { 857 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 858 859 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 860 } 861 862 static struct drm_framebuffer * 863 ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, 864 const struct drm_mode_fb_cmd2 *mode_cmd) 865 { 866 struct ingenic_drm *priv = drm_device_get_priv(drm); 867 868 if (priv->soc_info->map_noncoherent) 869 return drm_gem_fb_create_with_dirty(drm, file, mode_cmd); 870 871 return drm_gem_fb_create(drm, file, mode_cmd); 872 } 873 874 static struct drm_gem_object * 875 ingenic_drm_gem_create_object(struct drm_device *drm, size_t size) 876 { 877 struct ingenic_drm *priv = drm_device_get_priv(drm); 878 struct drm_gem_cma_object *obj; 879 880 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 881 if (!obj) 882 return ERR_PTR(-ENOMEM); 883 884 obj->map_noncoherent = priv->soc_info->map_noncoherent; 885 886 return &obj->base; 887 } 888 889 static struct drm_private_state * 890 ingenic_drm_duplicate_state(struct drm_private_obj *obj) 891 { 892 struct ingenic_drm_private_state *state = to_ingenic_drm_priv_state(obj->state); 893 894 state = kmemdup(state, sizeof(*state), GFP_KERNEL); 895 if (!state) 896 return NULL; 897 898 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 899 900 return &state->base; 901 } 902 903 static void ingenic_drm_destroy_state(struct drm_private_obj *obj, 904 struct drm_private_state *state) 905 { 906 struct ingenic_drm_private_state *priv_state = to_ingenic_drm_priv_state(state); 907 908 kfree(priv_state); 909 } 910 911 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 912 913 static const struct drm_driver ingenic_drm_driver_data = { 914 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 915 .name = "ingenic-drm", 916 .desc = "DRM module for Ingenic SoCs", 917 .date = "20200716", 918 .major = 1, 919 .minor = 1, 920 .patchlevel = 0, 921 922 .fops = &ingenic_drm_fops, 923 .gem_create_object = ingenic_drm_gem_create_object, 924 DRM_GEM_CMA_DRIVER_OPS, 925 }; 926 927 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 928 .update_plane = drm_atomic_helper_update_plane, 929 .disable_plane = drm_atomic_helper_disable_plane, 930 .reset = drm_atomic_helper_plane_reset, 931 .destroy = drm_plane_cleanup, 932 933 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 934 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 935 }; 936 937 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 938 .set_config = drm_atomic_helper_set_config, 939 .page_flip = drm_atomic_helper_page_flip, 940 .reset = drm_atomic_helper_crtc_reset, 941 .destroy = drm_crtc_cleanup, 942 943 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 944 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 945 946 .enable_vblank = ingenic_drm_enable_vblank, 947 .disable_vblank = ingenic_drm_disable_vblank, 948 }; 949 950 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 951 .atomic_update = ingenic_drm_plane_atomic_update, 952 .atomic_check = ingenic_drm_plane_atomic_check, 953 .atomic_disable = ingenic_drm_plane_atomic_disable, 954 }; 955 956 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 957 .atomic_enable = ingenic_drm_crtc_atomic_enable, 958 .atomic_disable = ingenic_drm_crtc_atomic_disable, 959 .atomic_begin = ingenic_drm_crtc_atomic_begin, 960 .atomic_flush = ingenic_drm_crtc_atomic_flush, 961 .atomic_check = ingenic_drm_crtc_atomic_check, 962 .mode_valid = ingenic_drm_crtc_mode_valid, 963 }; 964 965 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 966 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 967 }; 968 969 static const struct drm_bridge_funcs ingenic_drm_bridge_funcs = { 970 .attach = ingenic_drm_bridge_attach, 971 .atomic_check = ingenic_drm_bridge_atomic_check, 972 .atomic_reset = drm_atomic_helper_bridge_reset, 973 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 974 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 975 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, 976 }; 977 978 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 979 .fb_create = ingenic_drm_gem_fb_create, 980 .output_poll_changed = drm_fb_helper_output_poll_changed, 981 .atomic_check = drm_atomic_helper_check, 982 .atomic_commit = drm_atomic_helper_commit, 983 }; 984 985 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 986 .atomic_commit_tail = drm_atomic_helper_commit_tail, 987 }; 988 989 static const struct drm_private_state_funcs ingenic_drm_private_state_funcs = { 990 .atomic_duplicate_state = ingenic_drm_duplicate_state, 991 .atomic_destroy_state = ingenic_drm_destroy_state, 992 }; 993 994 static void ingenic_drm_unbind_all(void *d) 995 { 996 struct ingenic_drm *priv = d; 997 998 component_unbind_all(priv->dev, &priv->drm); 999 } 1000 1001 static void __maybe_unused ingenic_drm_release_rmem(void *d) 1002 { 1003 of_reserved_mem_device_release(d); 1004 } 1005 1006 static void ingenic_drm_configure_hwdesc(struct ingenic_drm *priv, 1007 unsigned int hwdesc, 1008 unsigned int next_hwdesc, u32 id) 1009 { 1010 struct ingenic_dma_hwdesc *desc = &priv->dma_hwdescs->hwdesc[hwdesc]; 1011 1012 desc->next = dma_hwdesc_addr(priv, next_hwdesc); 1013 desc->id = id; 1014 } 1015 1016 static void ingenic_drm_configure_hwdesc_palette(struct ingenic_drm *priv) 1017 { 1018 struct ingenic_dma_hwdesc *desc; 1019 1020 ingenic_drm_configure_hwdesc(priv, HWDESC_PALETTE, 0, 0xc0); 1021 1022 desc = &priv->dma_hwdescs->hwdesc[HWDESC_PALETTE]; 1023 desc->addr = priv->dma_hwdescs_phys 1024 + offsetof(struct ingenic_dma_hwdescs, palette); 1025 desc->cmd = JZ_LCD_CMD_ENABLE_PAL 1026 | (sizeof(priv->dma_hwdescs->palette) / 4); 1027 } 1028 1029 static void ingenic_drm_configure_hwdesc_plane(struct ingenic_drm *priv, 1030 unsigned int plane) 1031 { 1032 ingenic_drm_configure_hwdesc(priv, plane, plane, 0xf0 | plane); 1033 } 1034 1035 static void ingenic_drm_atomic_private_obj_fini(struct drm_device *drm, void *private_obj) 1036 { 1037 drm_atomic_private_obj_fini(private_obj); 1038 } 1039 1040 static int ingenic_drm_bind(struct device *dev, bool has_components) 1041 { 1042 struct platform_device *pdev = to_platform_device(dev); 1043 struct ingenic_drm_private_state *private_state; 1044 const struct jz_soc_info *soc_info; 1045 struct ingenic_drm *priv; 1046 struct clk *parent_clk; 1047 struct drm_plane *primary; 1048 struct drm_bridge *bridge; 1049 struct drm_panel *panel; 1050 struct drm_connector *connector; 1051 struct drm_encoder *encoder; 1052 struct ingenic_drm_bridge *ib; 1053 struct drm_device *drm; 1054 void __iomem *base; 1055 struct resource *res; 1056 struct regmap_config regmap_config; 1057 long parent_rate; 1058 unsigned int i, clone_mask = 0; 1059 int ret, irq; 1060 u32 osdc = 0; 1061 1062 soc_info = of_device_get_match_data(dev); 1063 if (!soc_info) { 1064 dev_err(dev, "Missing platform data\n"); 1065 return -EINVAL; 1066 } 1067 1068 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 1069 ret = of_reserved_mem_device_init(dev); 1070 1071 if (ret && ret != -ENODEV) 1072 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 1073 1074 if (!ret) { 1075 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 1076 if (ret) 1077 return ret; 1078 } 1079 } 1080 1081 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 1082 struct ingenic_drm, drm); 1083 if (IS_ERR(priv)) 1084 return PTR_ERR(priv); 1085 1086 priv->soc_info = soc_info; 1087 priv->dev = dev; 1088 drm = &priv->drm; 1089 1090 platform_set_drvdata(pdev, priv); 1091 1092 ret = drmm_mode_config_init(drm); 1093 if (ret) 1094 return ret; 1095 1096 drm->mode_config.min_width = 0; 1097 drm->mode_config.min_height = 0; 1098 drm->mode_config.max_width = soc_info->max_width; 1099 drm->mode_config.max_height = 4095; 1100 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 1101 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 1102 1103 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1104 if (IS_ERR(base)) { 1105 dev_err(dev, "Failed to get memory resource\n"); 1106 return PTR_ERR(base); 1107 } 1108 1109 regmap_config = ingenic_drm_regmap_config; 1110 regmap_config.max_register = res->end - res->start; 1111 priv->map = devm_regmap_init_mmio(dev, base, 1112 ®map_config); 1113 if (IS_ERR(priv->map)) { 1114 dev_err(dev, "Failed to create regmap\n"); 1115 return PTR_ERR(priv->map); 1116 } 1117 1118 irq = platform_get_irq(pdev, 0); 1119 if (irq < 0) 1120 return irq; 1121 1122 if (soc_info->needs_dev_clk) { 1123 priv->lcd_clk = devm_clk_get(dev, "lcd"); 1124 if (IS_ERR(priv->lcd_clk)) { 1125 dev_err(dev, "Failed to get lcd clock\n"); 1126 return PTR_ERR(priv->lcd_clk); 1127 } 1128 } 1129 1130 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 1131 if (IS_ERR(priv->pix_clk)) { 1132 dev_err(dev, "Failed to get pixel clock\n"); 1133 return PTR_ERR(priv->pix_clk); 1134 } 1135 1136 priv->dma_hwdescs = dmam_alloc_coherent(dev, 1137 sizeof(*priv->dma_hwdescs), 1138 &priv->dma_hwdescs_phys, 1139 GFP_KERNEL); 1140 if (!priv->dma_hwdescs) 1141 return -ENOMEM; 1142 1143 /* Configure DMA hwdesc for foreground0 plane */ 1144 ingenic_drm_configure_hwdesc_plane(priv, 0); 1145 1146 /* Configure DMA hwdesc for foreground1 plane */ 1147 ingenic_drm_configure_hwdesc_plane(priv, 1); 1148 1149 /* Configure DMA hwdesc for palette */ 1150 ingenic_drm_configure_hwdesc_palette(priv); 1151 1152 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0; 1153 1154 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs); 1155 1156 ret = drm_universal_plane_init(drm, primary, 1, 1157 &ingenic_drm_primary_plane_funcs, 1158 priv->soc_info->formats_f1, 1159 priv->soc_info->num_formats_f1, 1160 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1161 if (ret) { 1162 dev_err(dev, "Failed to register plane: %i\n", ret); 1163 return ret; 1164 } 1165 1166 if (soc_info->map_noncoherent) 1167 drm_plane_enable_fb_damage_clips(&priv->f1); 1168 1169 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 1170 1171 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary, 1172 NULL, &ingenic_drm_crtc_funcs, NULL); 1173 if (ret) { 1174 dev_err(dev, "Failed to init CRTC: %i\n", ret); 1175 return ret; 1176 } 1177 1178 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 1179 ARRAY_SIZE(priv->dma_hwdescs->palette)); 1180 1181 if (soc_info->has_osd) { 1182 drm_plane_helper_add(&priv->f0, 1183 &ingenic_drm_plane_helper_funcs); 1184 1185 ret = drm_universal_plane_init(drm, &priv->f0, 1, 1186 &ingenic_drm_primary_plane_funcs, 1187 priv->soc_info->formats_f0, 1188 priv->soc_info->num_formats_f0, 1189 NULL, DRM_PLANE_TYPE_OVERLAY, 1190 NULL); 1191 if (ret) { 1192 dev_err(dev, "Failed to register overlay plane: %i\n", 1193 ret); 1194 return ret; 1195 } 1196 1197 if (soc_info->map_noncoherent) 1198 drm_plane_enable_fb_damage_clips(&priv->f0); 1199 1200 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 1201 ret = component_bind_all(dev, drm); 1202 if (ret) { 1203 if (ret != -EPROBE_DEFER) 1204 dev_err(dev, "Failed to bind components: %i\n", ret); 1205 return ret; 1206 } 1207 1208 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 1209 if (ret) 1210 return ret; 1211 1212 priv->ipu_plane = drm_plane_from_index(drm, 2); 1213 if (!priv->ipu_plane) { 1214 dev_err(dev, "Failed to retrieve IPU plane\n"); 1215 return -EINVAL; 1216 } 1217 } 1218 } 1219 1220 for (i = 0; ; i++) { 1221 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 1222 if (ret) { 1223 if (ret == -ENODEV) 1224 break; /* we're done */ 1225 if (ret != -EPROBE_DEFER) 1226 dev_err(dev, "Failed to get bridge handle\n"); 1227 return ret; 1228 } 1229 1230 if (panel) 1231 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 1232 DRM_MODE_CONNECTOR_DPI); 1233 1234 ib = drmm_encoder_alloc(drm, struct ingenic_drm_bridge, encoder, 1235 NULL, DRM_MODE_ENCODER_DPI, NULL); 1236 if (IS_ERR(ib)) { 1237 ret = PTR_ERR(ib); 1238 dev_err(dev, "Failed to init encoder: %d\n", ret); 1239 return ret; 1240 } 1241 1242 encoder = &ib->encoder; 1243 encoder->possible_crtcs = drm_crtc_mask(&priv->crtc); 1244 1245 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1246 1247 ib->bridge.funcs = &ingenic_drm_bridge_funcs; 1248 ib->next_bridge = bridge; 1249 1250 ret = drm_bridge_attach(encoder, &ib->bridge, NULL, 1251 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1252 if (ret) { 1253 dev_err(dev, "Unable to attach bridge\n"); 1254 return ret; 1255 } 1256 1257 connector = drm_bridge_connector_init(drm, encoder); 1258 if (IS_ERR(connector)) { 1259 dev_err(dev, "Unable to init connector\n"); 1260 return PTR_ERR(connector); 1261 } 1262 1263 drm_connector_attach_encoder(connector, encoder); 1264 } 1265 1266 drm_for_each_encoder(encoder, drm) { 1267 clone_mask |= BIT(drm_encoder_index(encoder)); 1268 } 1269 1270 drm_for_each_encoder(encoder, drm) { 1271 encoder->possible_clones = clone_mask; 1272 } 1273 1274 ret = devm_request_irq(dev, irq, ingenic_drm_irq_handler, 0, drm->driver->name, drm); 1275 if (ret) { 1276 dev_err(dev, "Unable to install IRQ handler\n"); 1277 return ret; 1278 } 1279 1280 ret = drm_vblank_init(drm, 1); 1281 if (ret) { 1282 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1283 return ret; 1284 } 1285 1286 drm_mode_config_reset(drm); 1287 1288 ret = clk_prepare_enable(priv->pix_clk); 1289 if (ret) { 1290 dev_err(dev, "Unable to start pixel clock\n"); 1291 return ret; 1292 } 1293 1294 if (priv->lcd_clk) { 1295 parent_clk = clk_get_parent(priv->lcd_clk); 1296 parent_rate = clk_get_rate(parent_clk); 1297 1298 /* LCD Device clock must be 3x the pixel clock for STN panels, 1299 * or 1.5x the pixel clock for TFT panels. To avoid having to 1300 * check for the LCD device clock everytime we do a mode change, 1301 * we set the LCD device clock to the highest rate possible. 1302 */ 1303 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1304 if (ret) { 1305 dev_err(dev, "Unable to set LCD clock rate\n"); 1306 goto err_pixclk_disable; 1307 } 1308 1309 ret = clk_prepare_enable(priv->lcd_clk); 1310 if (ret) { 1311 dev_err(dev, "Unable to start lcd clock\n"); 1312 goto err_pixclk_disable; 1313 } 1314 } 1315 1316 /* Enable OSD if available */ 1317 if (soc_info->has_osd) 1318 osdc |= JZ_LCD_OSDC_OSDEN; 1319 if (soc_info->has_alpha) 1320 osdc |= JZ_LCD_OSDC_ALPHAEN; 1321 regmap_write(priv->map, JZ_REG_LCD_OSDC, osdc); 1322 1323 mutex_init(&priv->clk_mutex); 1324 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1325 1326 parent_clk = clk_get_parent(priv->pix_clk); 1327 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1328 if (ret) { 1329 dev_err(dev, "Unable to register clock notifier\n"); 1330 goto err_devclk_disable; 1331 } 1332 1333 private_state = kzalloc(sizeof(*private_state), GFP_KERNEL); 1334 if (!private_state) { 1335 ret = -ENOMEM; 1336 goto err_clk_notifier_unregister; 1337 } 1338 1339 drm_atomic_private_obj_init(drm, &priv->private_obj, &private_state->base, 1340 &ingenic_drm_private_state_funcs); 1341 1342 ret = drmm_add_action_or_reset(drm, ingenic_drm_atomic_private_obj_fini, 1343 &priv->private_obj); 1344 if (ret) 1345 goto err_private_state_free; 1346 1347 ret = drm_dev_register(drm, 0); 1348 if (ret) { 1349 dev_err(dev, "Failed to register DRM driver\n"); 1350 goto err_clk_notifier_unregister; 1351 } 1352 1353 drm_fbdev_generic_setup(drm, 32); 1354 1355 return 0; 1356 1357 err_private_state_free: 1358 kfree(private_state); 1359 err_clk_notifier_unregister: 1360 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1361 err_devclk_disable: 1362 if (priv->lcd_clk) 1363 clk_disable_unprepare(priv->lcd_clk); 1364 err_pixclk_disable: 1365 clk_disable_unprepare(priv->pix_clk); 1366 return ret; 1367 } 1368 1369 static int ingenic_drm_bind_with_components(struct device *dev) 1370 { 1371 return ingenic_drm_bind(dev, true); 1372 } 1373 1374 static int compare_of(struct device *dev, void *data) 1375 { 1376 return dev->of_node == data; 1377 } 1378 1379 static void ingenic_drm_unbind(struct device *dev) 1380 { 1381 struct ingenic_drm *priv = dev_get_drvdata(dev); 1382 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1383 1384 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1385 if (priv->lcd_clk) 1386 clk_disable_unprepare(priv->lcd_clk); 1387 clk_disable_unprepare(priv->pix_clk); 1388 1389 drm_dev_unregister(&priv->drm); 1390 drm_atomic_helper_shutdown(&priv->drm); 1391 } 1392 1393 static const struct component_master_ops ingenic_master_ops = { 1394 .bind = ingenic_drm_bind_with_components, 1395 .unbind = ingenic_drm_unbind, 1396 }; 1397 1398 static int ingenic_drm_probe(struct platform_device *pdev) 1399 { 1400 struct device *dev = &pdev->dev; 1401 struct component_match *match = NULL; 1402 struct device_node *np; 1403 1404 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1405 return ingenic_drm_bind(dev, false); 1406 1407 /* IPU is at port address 8 */ 1408 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1409 if (!np) 1410 return ingenic_drm_bind(dev, false); 1411 1412 drm_of_component_match_add(dev, &match, compare_of, np); 1413 of_node_put(np); 1414 1415 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1416 } 1417 1418 static int ingenic_drm_remove(struct platform_device *pdev) 1419 { 1420 struct device *dev = &pdev->dev; 1421 1422 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1423 ingenic_drm_unbind(dev); 1424 else 1425 component_master_del(dev, &ingenic_master_ops); 1426 1427 return 0; 1428 } 1429 1430 static int __maybe_unused ingenic_drm_suspend(struct device *dev) 1431 { 1432 struct ingenic_drm *priv = dev_get_drvdata(dev); 1433 1434 return drm_mode_config_helper_suspend(&priv->drm); 1435 } 1436 1437 static int __maybe_unused ingenic_drm_resume(struct device *dev) 1438 { 1439 struct ingenic_drm *priv = dev_get_drvdata(dev); 1440 1441 return drm_mode_config_helper_resume(&priv->drm); 1442 } 1443 1444 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume); 1445 1446 static const u32 jz4740_formats[] = { 1447 DRM_FORMAT_XRGB1555, 1448 DRM_FORMAT_RGB565, 1449 DRM_FORMAT_XRGB8888, 1450 }; 1451 1452 static const u32 jz4725b_formats_f1[] = { 1453 DRM_FORMAT_XRGB1555, 1454 DRM_FORMAT_RGB565, 1455 DRM_FORMAT_XRGB8888, 1456 }; 1457 1458 static const u32 jz4725b_formats_f0[] = { 1459 DRM_FORMAT_C8, 1460 DRM_FORMAT_XRGB1555, 1461 DRM_FORMAT_RGB565, 1462 DRM_FORMAT_XRGB8888, 1463 }; 1464 1465 static const u32 jz4770_formats_f1[] = { 1466 DRM_FORMAT_XRGB1555, 1467 DRM_FORMAT_RGB565, 1468 DRM_FORMAT_RGB888, 1469 DRM_FORMAT_XRGB8888, 1470 DRM_FORMAT_XRGB2101010, 1471 }; 1472 1473 static const u32 jz4770_formats_f0[] = { 1474 DRM_FORMAT_C8, 1475 DRM_FORMAT_XRGB1555, 1476 DRM_FORMAT_RGB565, 1477 DRM_FORMAT_RGB888, 1478 DRM_FORMAT_XRGB8888, 1479 DRM_FORMAT_XRGB2101010, 1480 }; 1481 1482 static const struct jz_soc_info jz4740_soc_info = { 1483 .needs_dev_clk = true, 1484 .has_osd = false, 1485 .map_noncoherent = false, 1486 .max_width = 800, 1487 .max_height = 600, 1488 .formats_f1 = jz4740_formats, 1489 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1490 /* JZ4740 has only one plane */ 1491 }; 1492 1493 static const struct jz_soc_info jz4725b_soc_info = { 1494 .needs_dev_clk = false, 1495 .has_osd = true, 1496 .map_noncoherent = false, 1497 .max_width = 800, 1498 .max_height = 600, 1499 .formats_f1 = jz4725b_formats_f1, 1500 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1501 .formats_f0 = jz4725b_formats_f0, 1502 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1503 }; 1504 1505 static const struct jz_soc_info jz4770_soc_info = { 1506 .needs_dev_clk = false, 1507 .has_osd = true, 1508 .map_noncoherent = true, 1509 .max_width = 1280, 1510 .max_height = 720, 1511 .formats_f1 = jz4770_formats_f1, 1512 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1513 .formats_f0 = jz4770_formats_f0, 1514 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1515 }; 1516 1517 static const struct jz_soc_info jz4780_soc_info = { 1518 .needs_dev_clk = true, 1519 .has_osd = true, 1520 .has_alpha = true, 1521 .use_extended_hwdesc = true, 1522 .plane_f0_not_working = true, /* REVISIT */ 1523 .max_width = 4096, 1524 .max_height = 2048, 1525 .formats_f1 = jz4770_formats_f1, 1526 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1527 .formats_f0 = jz4770_formats_f0, 1528 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1529 }; 1530 1531 static const struct of_device_id ingenic_drm_of_match[] = { 1532 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1533 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1534 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1535 { .compatible = "ingenic,jz4780-lcd", .data = &jz4780_soc_info }, 1536 { /* sentinel */ }, 1537 }; 1538 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1539 1540 static struct platform_driver ingenic_drm_driver = { 1541 .driver = { 1542 .name = "ingenic-drm", 1543 .pm = pm_ptr(&ingenic_drm_pm_ops), 1544 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1545 }, 1546 .probe = ingenic_drm_probe, 1547 .remove = ingenic_drm_remove, 1548 }; 1549 1550 static int ingenic_drm_init(void) 1551 { 1552 int err; 1553 1554 if (drm_firmware_drivers_only()) 1555 return -ENODEV; 1556 1557 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1558 err = platform_driver_register(ingenic_ipu_driver_ptr); 1559 if (err) 1560 return err; 1561 } 1562 1563 return platform_driver_register(&ingenic_drm_driver); 1564 } 1565 module_init(ingenic_drm_init); 1566 1567 static void ingenic_drm_exit(void) 1568 { 1569 platform_driver_unregister(&ingenic_drm_driver); 1570 1571 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1572 platform_driver_unregister(ingenic_ipu_driver_ptr); 1573 } 1574 module_exit(ingenic_drm_exit); 1575 1576 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1577 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1578 MODULE_LICENSE("GPL v2"); 1579