1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/component.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of_device.h> 15 #include <linux/of_reserved_mem.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/regmap.h> 19 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_color_mgmt.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_encoder.h> 28 #include <drm/drm_gem_cma_helper.h> 29 #include <drm/drm_fb_cma_helper.h> 30 #include <drm/drm_fb_helper.h> 31 #include <drm/drm_fourcc.h> 32 #include <drm/drm_gem_atomic_helper.h> 33 #include <drm/drm_gem_framebuffer_helper.h> 34 #include <drm/drm_irq.h> 35 #include <drm/drm_managed.h> 36 #include <drm/drm_of.h> 37 #include <drm/drm_panel.h> 38 #include <drm/drm_plane.h> 39 #include <drm/drm_plane_helper.h> 40 #include <drm/drm_probe_helper.h> 41 #include <drm/drm_vblank.h> 42 43 struct ingenic_dma_hwdesc { 44 u32 next; 45 u32 addr; 46 u32 id; 47 u32 cmd; 48 } __aligned(16); 49 50 struct ingenic_dma_hwdescs { 51 struct ingenic_dma_hwdesc hwdesc_f0; 52 struct ingenic_dma_hwdesc hwdesc_f1; 53 struct ingenic_dma_hwdesc hwdesc_pal; 54 u16 palette[256] __aligned(16); 55 }; 56 57 struct jz_soc_info { 58 bool needs_dev_clk; 59 bool has_osd; 60 unsigned int max_width, max_height; 61 const u32 *formats_f0, *formats_f1; 62 unsigned int num_formats_f0, num_formats_f1; 63 }; 64 65 struct ingenic_drm { 66 struct drm_device drm; 67 /* 68 * f1 (aka. foreground1) is our primary plane, on top of which 69 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 70 * hardware and cannot be changed. 71 */ 72 struct drm_plane f0, f1, *ipu_plane; 73 struct drm_crtc crtc; 74 75 struct device *dev; 76 struct regmap *map; 77 struct clk *lcd_clk, *pix_clk; 78 const struct jz_soc_info *soc_info; 79 80 struct ingenic_dma_hwdescs *dma_hwdescs; 81 dma_addr_t dma_hwdescs_phys; 82 83 bool panel_is_sharp; 84 bool no_vblank; 85 86 /* 87 * clk_mutex is used to synchronize the pixel clock rate update with 88 * the VBLANK. When the pixel clock's parent clock needs to be updated, 89 * clock_nb's notifier function will lock the mutex, then wait until the 90 * next VBLANK. At that point, the parent clock's rate can be updated, 91 * and the mutex is then unlocked. If an atomic commit happens in the 92 * meantime, it will lock on the mutex, effectively waiting until the 93 * clock update process finishes. Finally, the pixel clock's rate will 94 * be recomputed when the mutex has been released, in the pending atomic 95 * commit, or a future one. 96 */ 97 struct mutex clk_mutex; 98 bool update_clk_rate; 99 struct notifier_block clock_nb; 100 }; 101 102 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 103 { 104 switch (reg) { 105 case JZ_REG_LCD_IID: 106 case JZ_REG_LCD_SA0: 107 case JZ_REG_LCD_FID0: 108 case JZ_REG_LCD_CMD0: 109 case JZ_REG_LCD_SA1: 110 case JZ_REG_LCD_FID1: 111 case JZ_REG_LCD_CMD1: 112 return false; 113 default: 114 return true; 115 } 116 } 117 118 static const struct regmap_config ingenic_drm_regmap_config = { 119 .reg_bits = 32, 120 .val_bits = 32, 121 .reg_stride = 4, 122 123 .max_register = JZ_REG_LCD_SIZE1, 124 .writeable_reg = ingenic_drm_writeable_reg, 125 }; 126 127 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 128 { 129 return container_of(drm, struct ingenic_drm, drm); 130 } 131 132 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 133 { 134 return container_of(crtc, struct ingenic_drm, crtc); 135 } 136 137 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 138 { 139 return container_of(nb, struct ingenic_drm, clock_nb); 140 } 141 142 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 143 unsigned long action, 144 void *data) 145 { 146 struct ingenic_drm *priv = drm_nb_get_priv(nb); 147 148 switch (action) { 149 case PRE_RATE_CHANGE: 150 mutex_lock(&priv->clk_mutex); 151 priv->update_clk_rate = true; 152 drm_crtc_wait_one_vblank(&priv->crtc); 153 return NOTIFY_OK; 154 default: 155 mutex_unlock(&priv->clk_mutex); 156 return NOTIFY_OK; 157 } 158 } 159 160 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 161 struct drm_atomic_state *state) 162 { 163 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 164 165 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 166 167 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 168 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 169 JZ_LCD_CTRL_ENABLE); 170 171 drm_crtc_vblank_on(crtc); 172 } 173 174 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 175 struct drm_atomic_state *state) 176 { 177 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 178 unsigned int var; 179 180 drm_crtc_vblank_off(crtc); 181 182 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 183 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 184 185 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 186 var & JZ_LCD_STATE_DISABLED, 187 1000, 0); 188 } 189 190 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 191 struct drm_display_mode *mode) 192 { 193 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 194 195 vpe = mode->crtc_vsync_end - mode->crtc_vsync_start; 196 vds = mode->crtc_vtotal - mode->crtc_vsync_start; 197 vde = vds + mode->crtc_vdisplay; 198 vt = vde + mode->crtc_vsync_start - mode->crtc_vdisplay; 199 200 hpe = mode->crtc_hsync_end - mode->crtc_hsync_start; 201 hds = mode->crtc_htotal - mode->crtc_hsync_start; 202 hde = hds + mode->crtc_hdisplay; 203 ht = hde + mode->crtc_hsync_start - mode->crtc_hdisplay; 204 205 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 206 0 << JZ_LCD_VSYNC_VPS_OFFSET | 207 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 208 209 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 210 0 << JZ_LCD_HSYNC_HPS_OFFSET | 211 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 212 213 regmap_write(priv->map, JZ_REG_LCD_VAT, 214 ht << JZ_LCD_VAT_HT_OFFSET | 215 vt << JZ_LCD_VAT_VT_OFFSET); 216 217 regmap_write(priv->map, JZ_REG_LCD_DAH, 218 hds << JZ_LCD_DAH_HDS_OFFSET | 219 hde << JZ_LCD_DAH_HDE_OFFSET); 220 regmap_write(priv->map, JZ_REG_LCD_DAV, 221 vds << JZ_LCD_DAV_VDS_OFFSET | 222 vde << JZ_LCD_DAV_VDE_OFFSET); 223 224 if (priv->panel_is_sharp) { 225 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 226 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 227 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 228 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 229 } 230 231 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 232 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 233 234 /* 235 * IPU restart - specify how much time the LCDC will wait before 236 * transferring a new frame from the IPU. The value is the one 237 * suggested in the programming manual. 238 */ 239 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 240 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 241 } 242 243 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 244 struct drm_atomic_state *state) 245 { 246 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 247 crtc); 248 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 249 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 250 251 if (crtc_state->gamma_lut && 252 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 253 dev_dbg(priv->dev, "Invalid palette size\n"); 254 return -EINVAL; 255 } 256 257 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 258 f1_state = drm_atomic_get_plane_state(crtc_state->state, 259 &priv->f1); 260 if (IS_ERR(f1_state)) 261 return PTR_ERR(f1_state); 262 263 f0_state = drm_atomic_get_plane_state(crtc_state->state, 264 &priv->f0); 265 if (IS_ERR(f0_state)) 266 return PTR_ERR(f0_state); 267 268 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 269 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 270 priv->ipu_plane); 271 if (IS_ERR(ipu_state)) 272 return PTR_ERR(ipu_state); 273 274 /* IPU and F1 planes cannot be enabled at the same time. */ 275 if (f1_state->fb && ipu_state->fb) { 276 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 277 return -EINVAL; 278 } 279 } 280 281 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 282 priv->no_vblank = !f1_state->fb && !f0_state->fb && 283 !(ipu_state && ipu_state->fb); 284 } 285 286 return 0; 287 } 288 289 static enum drm_mode_status 290 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 291 { 292 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 293 long rate; 294 295 if (mode->hdisplay > priv->soc_info->max_width) 296 return MODE_BAD_HVALUE; 297 if (mode->vdisplay > priv->soc_info->max_height) 298 return MODE_BAD_VVALUE; 299 300 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 301 if (rate < 0) 302 return MODE_CLOCK_RANGE; 303 304 return MODE_OK; 305 } 306 307 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 308 struct drm_atomic_state *state) 309 { 310 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 311 crtc); 312 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 313 u32 ctrl = 0; 314 315 if (priv->soc_info->has_osd && 316 drm_atomic_crtc_needs_modeset(crtc_state)) { 317 /* 318 * If IPU plane is enabled, enable IPU as source for the F1 319 * plane; otherwise use regular DMA. 320 */ 321 if (priv->ipu_plane && priv->ipu_plane->state->fb) 322 ctrl |= JZ_LCD_OSDCTRL_IPU; 323 324 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 325 JZ_LCD_OSDCTRL_IPU, ctrl); 326 } 327 } 328 329 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 330 struct drm_atomic_state *state) 331 { 332 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 333 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 334 crtc); 335 struct drm_pending_vblank_event *event = crtc_state->event; 336 337 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 338 ingenic_drm_crtc_update_timings(priv, &crtc_state->adjusted_mode); 339 priv->update_clk_rate = true; 340 } 341 342 if (priv->update_clk_rate) { 343 mutex_lock(&priv->clk_mutex); 344 clk_set_rate(priv->pix_clk, 345 crtc_state->adjusted_mode.clock * 1000); 346 priv->update_clk_rate = false; 347 mutex_unlock(&priv->clk_mutex); 348 } 349 350 if (event) { 351 crtc_state->event = NULL; 352 353 spin_lock_irq(&crtc->dev->event_lock); 354 if (drm_crtc_vblank_get(crtc) == 0) 355 drm_crtc_arm_vblank_event(crtc, event); 356 else 357 drm_crtc_send_vblank_event(crtc, event); 358 spin_unlock_irq(&crtc->dev->event_lock); 359 } 360 } 361 362 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 363 struct drm_atomic_state *state) 364 { 365 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 366 plane); 367 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 368 plane); 369 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 370 struct drm_crtc_state *crtc_state; 371 struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc; 372 int ret; 373 374 if (!crtc) 375 return 0; 376 377 crtc_state = drm_atomic_get_existing_crtc_state(state, 378 crtc); 379 if (WARN_ON(!crtc_state)) 380 return -EINVAL; 381 382 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 383 DRM_PLANE_HELPER_NO_SCALING, 384 DRM_PLANE_HELPER_NO_SCALING, 385 priv->soc_info->has_osd, 386 true); 387 if (ret) 388 return ret; 389 390 /* 391 * If OSD is not available, check that the width/height match. 392 * Note that state->src_* are in 16.16 fixed-point format. 393 */ 394 if (!priv->soc_info->has_osd && 395 (new_plane_state->src_x != 0 || 396 (new_plane_state->src_w >> 16) != new_plane_state->crtc_w || 397 (new_plane_state->src_h >> 16) != new_plane_state->crtc_h)) 398 return -EINVAL; 399 400 /* 401 * Require full modeset if enabling or disabling a plane, or changing 402 * its position, size or depth. 403 */ 404 if (priv->soc_info->has_osd && 405 (!old_plane_state->fb || !new_plane_state->fb || 406 old_plane_state->crtc_x != new_plane_state->crtc_x || 407 old_plane_state->crtc_y != new_plane_state->crtc_y || 408 old_plane_state->crtc_w != new_plane_state->crtc_w || 409 old_plane_state->crtc_h != new_plane_state->crtc_h || 410 old_plane_state->fb->format->format != new_plane_state->fb->format->format)) 411 crtc_state->mode_changed = true; 412 413 return 0; 414 } 415 416 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 417 struct drm_plane *plane) 418 { 419 unsigned int en_bit; 420 421 if (priv->soc_info->has_osd) { 422 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 423 en_bit = JZ_LCD_OSDC_F1EN; 424 else 425 en_bit = JZ_LCD_OSDC_F0EN; 426 427 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 428 } 429 } 430 431 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 432 { 433 struct ingenic_drm *priv = dev_get_drvdata(dev); 434 unsigned int en_bit; 435 436 if (priv->soc_info->has_osd) { 437 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 438 en_bit = JZ_LCD_OSDC_F1EN; 439 else 440 en_bit = JZ_LCD_OSDC_F0EN; 441 442 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 443 } 444 } 445 446 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 447 struct drm_atomic_state *state) 448 { 449 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 450 451 ingenic_drm_plane_disable(priv->dev, plane); 452 } 453 454 void ingenic_drm_plane_config(struct device *dev, 455 struct drm_plane *plane, u32 fourcc) 456 { 457 struct ingenic_drm *priv = dev_get_drvdata(dev); 458 struct drm_plane_state *state = plane->state; 459 unsigned int xy_reg, size_reg; 460 unsigned int ctrl = 0; 461 462 ingenic_drm_plane_enable(priv, plane); 463 464 if (priv->soc_info->has_osd && 465 plane->type == DRM_PLANE_TYPE_PRIMARY) { 466 switch (fourcc) { 467 case DRM_FORMAT_XRGB1555: 468 ctrl |= JZ_LCD_OSDCTRL_RGB555; 469 fallthrough; 470 case DRM_FORMAT_RGB565: 471 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 472 break; 473 case DRM_FORMAT_RGB888: 474 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 475 break; 476 case DRM_FORMAT_XRGB8888: 477 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 478 break; 479 case DRM_FORMAT_XRGB2101010: 480 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 481 break; 482 } 483 484 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 485 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 486 } else { 487 switch (fourcc) { 488 case DRM_FORMAT_C8: 489 ctrl |= JZ_LCD_CTRL_BPP_8; 490 break; 491 case DRM_FORMAT_XRGB1555: 492 ctrl |= JZ_LCD_CTRL_RGB555; 493 fallthrough; 494 case DRM_FORMAT_RGB565: 495 ctrl |= JZ_LCD_CTRL_BPP_15_16; 496 break; 497 case DRM_FORMAT_RGB888: 498 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 499 break; 500 case DRM_FORMAT_XRGB8888: 501 ctrl |= JZ_LCD_CTRL_BPP_18_24; 502 break; 503 case DRM_FORMAT_XRGB2101010: 504 ctrl |= JZ_LCD_CTRL_BPP_30; 505 break; 506 } 507 508 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 509 JZ_LCD_CTRL_BPP_MASK, ctrl); 510 } 511 512 if (priv->soc_info->has_osd) { 513 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 514 xy_reg = JZ_REG_LCD_XYP1; 515 size_reg = JZ_REG_LCD_SIZE1; 516 } else { 517 xy_reg = JZ_REG_LCD_XYP0; 518 size_reg = JZ_REG_LCD_SIZE0; 519 } 520 521 regmap_write(priv->map, xy_reg, 522 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 523 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 524 regmap_write(priv->map, size_reg, 525 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 526 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 527 } 528 } 529 530 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 531 const struct drm_color_lut *lut) 532 { 533 unsigned int i; 534 535 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 536 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 537 | drm_color_lut_extract(lut[i].green, 6) << 5 538 | drm_color_lut_extract(lut[i].blue, 5); 539 540 priv->dma_hwdescs->palette[i] = color; 541 } 542 } 543 544 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 545 struct drm_atomic_state *state) 546 { 547 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 548 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 549 plane); 550 struct drm_crtc_state *crtc_state; 551 struct ingenic_dma_hwdesc *hwdesc; 552 unsigned int width, height, cpp, offset; 553 dma_addr_t addr; 554 u32 fourcc; 555 556 if (newstate && newstate->fb) { 557 crtc_state = newstate->crtc->state; 558 559 addr = drm_fb_cma_get_gem_addr(newstate->fb, newstate, 0); 560 width = newstate->src_w >> 16; 561 height = newstate->src_h >> 16; 562 cpp = newstate->fb->format->cpp[0]; 563 564 if (!priv->soc_info->has_osd || plane->type == DRM_PLANE_TYPE_OVERLAY) 565 hwdesc = &priv->dma_hwdescs->hwdesc_f0; 566 else 567 hwdesc = &priv->dma_hwdescs->hwdesc_f1; 568 569 hwdesc->addr = addr; 570 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 571 572 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 573 fourcc = newstate->fb->format->format; 574 575 ingenic_drm_plane_config(priv->dev, plane, fourcc); 576 577 if (fourcc == DRM_FORMAT_C8) 578 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_pal); 579 else 580 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 581 582 priv->dma_hwdescs->hwdesc_f0.next = priv->dma_hwdescs_phys + offset; 583 584 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 585 } 586 587 if (crtc_state->color_mgmt_changed) 588 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 589 } 590 } 591 592 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 593 struct drm_crtc_state *crtc_state, 594 struct drm_connector_state *conn_state) 595 { 596 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 597 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 598 struct drm_connector *conn = conn_state->connector; 599 struct drm_display_info *info = &conn->display_info; 600 unsigned int cfg, rgbcfg = 0; 601 602 priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS; 603 604 if (priv->panel_is_sharp) { 605 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 606 } else { 607 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 608 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 609 } 610 611 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 612 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 613 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 614 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 615 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 616 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 617 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 618 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 619 620 if (!priv->panel_is_sharp) { 621 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) { 622 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 623 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 624 else 625 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 626 } else { 627 switch (*info->bus_formats) { 628 case MEDIA_BUS_FMT_RGB565_1X16: 629 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 630 break; 631 case MEDIA_BUS_FMT_RGB666_1X18: 632 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 633 break; 634 case MEDIA_BUS_FMT_RGB888_1X24: 635 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 636 break; 637 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 638 rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; 639 fallthrough; 640 case MEDIA_BUS_FMT_RGB888_3X8: 641 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 642 break; 643 default: 644 break; 645 } 646 } 647 } 648 649 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 650 regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); 651 } 652 653 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, 654 struct drm_crtc_state *crtc_state, 655 struct drm_connector_state *conn_state) 656 { 657 struct drm_display_info *info = &conn_state->connector->display_info; 658 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 659 660 if (info->num_bus_formats != 1) 661 return -EINVAL; 662 663 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 664 return 0; 665 666 switch (*info->bus_formats) { 667 case MEDIA_BUS_FMT_RGB888_3X8: 668 case MEDIA_BUS_FMT_RGB888_3X8_DELTA: 669 /* 670 * The LCD controller expects timing values in dot-clock ticks, 671 * which is 3x the timing values in pixels when using a 3x8-bit 672 * display; but it will count the display area size in pixels 673 * either way. Go figure. 674 */ 675 mode->crtc_clock = mode->clock * 3; 676 mode->crtc_hsync_start = mode->hsync_start * 3 - mode->hdisplay * 2; 677 mode->crtc_hsync_end = mode->hsync_end * 3 - mode->hdisplay * 2; 678 mode->crtc_hdisplay = mode->hdisplay; 679 mode->crtc_htotal = mode->htotal * 3 - mode->hdisplay * 2; 680 return 0; 681 case MEDIA_BUS_FMT_RGB565_1X16: 682 case MEDIA_BUS_FMT_RGB666_1X18: 683 case MEDIA_BUS_FMT_RGB888_1X24: 684 return 0; 685 default: 686 return -EINVAL; 687 } 688 } 689 690 static void ingenic_drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state) 691 { 692 /* 693 * Just your regular drm_atomic_helper_commit_tail(), but only calls 694 * drm_atomic_helper_wait_for_vblanks() if priv->no_vblank. 695 */ 696 struct drm_device *dev = old_state->dev; 697 struct ingenic_drm *priv = drm_device_get_priv(dev); 698 699 drm_atomic_helper_commit_modeset_disables(dev, old_state); 700 701 drm_atomic_helper_commit_planes(dev, old_state, 0); 702 703 drm_atomic_helper_commit_modeset_enables(dev, old_state); 704 705 drm_atomic_helper_commit_hw_done(old_state); 706 707 if (!priv->no_vblank) 708 drm_atomic_helper_wait_for_vblanks(dev, old_state); 709 710 drm_atomic_helper_cleanup_planes(dev, old_state); 711 } 712 713 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 714 { 715 struct ingenic_drm *priv = drm_device_get_priv(arg); 716 unsigned int state; 717 718 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 719 720 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 721 JZ_LCD_STATE_EOF_IRQ, 0); 722 723 if (state & JZ_LCD_STATE_EOF_IRQ) 724 drm_crtc_handle_vblank(&priv->crtc); 725 726 return IRQ_HANDLED; 727 } 728 729 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 730 { 731 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 732 733 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 734 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 735 736 return 0; 737 } 738 739 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 740 { 741 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 742 743 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 744 } 745 746 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 747 748 static const struct drm_driver ingenic_drm_driver_data = { 749 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 750 .name = "ingenic-drm", 751 .desc = "DRM module for Ingenic SoCs", 752 .date = "20200716", 753 .major = 1, 754 .minor = 1, 755 .patchlevel = 0, 756 757 .fops = &ingenic_drm_fops, 758 DRM_GEM_CMA_DRIVER_OPS, 759 760 .irq_handler = ingenic_drm_irq_handler, 761 }; 762 763 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 764 .update_plane = drm_atomic_helper_update_plane, 765 .disable_plane = drm_atomic_helper_disable_plane, 766 .reset = drm_atomic_helper_plane_reset, 767 .destroy = drm_plane_cleanup, 768 769 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 770 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 771 }; 772 773 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 774 .set_config = drm_atomic_helper_set_config, 775 .page_flip = drm_atomic_helper_page_flip, 776 .reset = drm_atomic_helper_crtc_reset, 777 .destroy = drm_crtc_cleanup, 778 779 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 780 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 781 782 .enable_vblank = ingenic_drm_enable_vblank, 783 .disable_vblank = ingenic_drm_disable_vblank, 784 }; 785 786 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 787 .atomic_update = ingenic_drm_plane_atomic_update, 788 .atomic_check = ingenic_drm_plane_atomic_check, 789 .atomic_disable = ingenic_drm_plane_atomic_disable, 790 .prepare_fb = drm_gem_plane_helper_prepare_fb, 791 }; 792 793 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 794 .atomic_enable = ingenic_drm_crtc_atomic_enable, 795 .atomic_disable = ingenic_drm_crtc_atomic_disable, 796 .atomic_begin = ingenic_drm_crtc_atomic_begin, 797 .atomic_flush = ingenic_drm_crtc_atomic_flush, 798 .atomic_check = ingenic_drm_crtc_atomic_check, 799 .mode_valid = ingenic_drm_crtc_mode_valid, 800 }; 801 802 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 803 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 804 .atomic_check = ingenic_drm_encoder_atomic_check, 805 }; 806 807 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 808 .fb_create = drm_gem_fb_create, 809 .output_poll_changed = drm_fb_helper_output_poll_changed, 810 .atomic_check = drm_atomic_helper_check, 811 .atomic_commit = drm_atomic_helper_commit, 812 }; 813 814 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 815 .atomic_commit_tail = ingenic_drm_atomic_helper_commit_tail, 816 }; 817 818 static void ingenic_drm_unbind_all(void *d) 819 { 820 struct ingenic_drm *priv = d; 821 822 component_unbind_all(priv->dev, &priv->drm); 823 } 824 825 static void __maybe_unused ingenic_drm_release_rmem(void *d) 826 { 827 of_reserved_mem_device_release(d); 828 } 829 830 static int ingenic_drm_bind(struct device *dev, bool has_components) 831 { 832 struct platform_device *pdev = to_platform_device(dev); 833 const struct jz_soc_info *soc_info; 834 struct ingenic_drm *priv; 835 struct clk *parent_clk; 836 struct drm_plane *primary; 837 struct drm_bridge *bridge; 838 struct drm_panel *panel; 839 struct drm_encoder *encoder; 840 struct drm_device *drm; 841 void __iomem *base; 842 long parent_rate; 843 unsigned int i, clone_mask = 0; 844 dma_addr_t dma_hwdesc_phys_f0, dma_hwdesc_phys_f1; 845 int ret, irq; 846 847 soc_info = of_device_get_match_data(dev); 848 if (!soc_info) { 849 dev_err(dev, "Missing platform data\n"); 850 return -EINVAL; 851 } 852 853 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 854 ret = of_reserved_mem_device_init(dev); 855 856 if (ret && ret != -ENODEV) 857 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 858 859 if (!ret) { 860 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 861 if (ret) 862 return ret; 863 } 864 } 865 866 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 867 struct ingenic_drm, drm); 868 if (IS_ERR(priv)) 869 return PTR_ERR(priv); 870 871 priv->soc_info = soc_info; 872 priv->dev = dev; 873 drm = &priv->drm; 874 875 platform_set_drvdata(pdev, priv); 876 877 ret = drmm_mode_config_init(drm); 878 if (ret) 879 return ret; 880 881 drm->mode_config.min_width = 0; 882 drm->mode_config.min_height = 0; 883 drm->mode_config.max_width = soc_info->max_width; 884 drm->mode_config.max_height = 4095; 885 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 886 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 887 888 base = devm_platform_ioremap_resource(pdev, 0); 889 if (IS_ERR(base)) { 890 dev_err(dev, "Failed to get memory resource\n"); 891 return PTR_ERR(base); 892 } 893 894 priv->map = devm_regmap_init_mmio(dev, base, 895 &ingenic_drm_regmap_config); 896 if (IS_ERR(priv->map)) { 897 dev_err(dev, "Failed to create regmap\n"); 898 return PTR_ERR(priv->map); 899 } 900 901 irq = platform_get_irq(pdev, 0); 902 if (irq < 0) 903 return irq; 904 905 if (soc_info->needs_dev_clk) { 906 priv->lcd_clk = devm_clk_get(dev, "lcd"); 907 if (IS_ERR(priv->lcd_clk)) { 908 dev_err(dev, "Failed to get lcd clock\n"); 909 return PTR_ERR(priv->lcd_clk); 910 } 911 } 912 913 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 914 if (IS_ERR(priv->pix_clk)) { 915 dev_err(dev, "Failed to get pixel clock\n"); 916 return PTR_ERR(priv->pix_clk); 917 } 918 919 priv->dma_hwdescs = dmam_alloc_coherent(dev, 920 sizeof(*priv->dma_hwdescs), 921 &priv->dma_hwdescs_phys, 922 GFP_KERNEL); 923 if (!priv->dma_hwdescs) 924 return -ENOMEM; 925 926 927 /* Configure DMA hwdesc for foreground0 plane */ 928 dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys 929 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 930 priv->dma_hwdescs->hwdesc_f0.next = dma_hwdesc_phys_f0; 931 priv->dma_hwdescs->hwdesc_f0.id = 0xf0; 932 933 /* Configure DMA hwdesc for foreground1 plane */ 934 dma_hwdesc_phys_f1 = priv->dma_hwdescs_phys 935 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f1); 936 priv->dma_hwdescs->hwdesc_f1.next = dma_hwdesc_phys_f1; 937 priv->dma_hwdescs->hwdesc_f1.id = 0xf1; 938 939 /* Configure DMA hwdesc for palette */ 940 priv->dma_hwdescs->hwdesc_pal.next = priv->dma_hwdescs_phys 941 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 942 priv->dma_hwdescs->hwdesc_pal.id = 0xc0; 943 priv->dma_hwdescs->hwdesc_pal.addr = priv->dma_hwdescs_phys 944 + offsetof(struct ingenic_dma_hwdescs, palette); 945 priv->dma_hwdescs->hwdesc_pal.cmd = JZ_LCD_CMD_ENABLE_PAL 946 | (sizeof(priv->dma_hwdescs->palette) / 4); 947 948 if (soc_info->has_osd) 949 priv->ipu_plane = drm_plane_from_index(drm, 0); 950 951 primary = priv->soc_info->has_osd ? &priv->f1 : &priv->f0; 952 953 drm_plane_helper_add(primary, &ingenic_drm_plane_helper_funcs); 954 955 ret = drm_universal_plane_init(drm, primary, 1, 956 &ingenic_drm_primary_plane_funcs, 957 priv->soc_info->formats_f1, 958 priv->soc_info->num_formats_f1, 959 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 960 if (ret) { 961 dev_err(dev, "Failed to register plane: %i\n", ret); 962 return ret; 963 } 964 965 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 966 967 ret = drm_crtc_init_with_planes(drm, &priv->crtc, primary, 968 NULL, &ingenic_drm_crtc_funcs, NULL); 969 if (ret) { 970 dev_err(dev, "Failed to init CRTC: %i\n", ret); 971 return ret; 972 } 973 974 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 975 ARRAY_SIZE(priv->dma_hwdescs->palette)); 976 977 if (soc_info->has_osd) { 978 drm_plane_helper_add(&priv->f0, 979 &ingenic_drm_plane_helper_funcs); 980 981 ret = drm_universal_plane_init(drm, &priv->f0, 1, 982 &ingenic_drm_primary_plane_funcs, 983 priv->soc_info->formats_f0, 984 priv->soc_info->num_formats_f0, 985 NULL, DRM_PLANE_TYPE_OVERLAY, 986 NULL); 987 if (ret) { 988 dev_err(dev, "Failed to register overlay plane: %i\n", 989 ret); 990 return ret; 991 } 992 993 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 994 ret = component_bind_all(dev, drm); 995 if (ret) { 996 if (ret != -EPROBE_DEFER) 997 dev_err(dev, "Failed to bind components: %i\n", ret); 998 return ret; 999 } 1000 1001 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 1002 if (ret) 1003 return ret; 1004 1005 priv->ipu_plane = drm_plane_from_index(drm, 2); 1006 if (!priv->ipu_plane) { 1007 dev_err(dev, "Failed to retrieve IPU plane\n"); 1008 return -EINVAL; 1009 } 1010 } 1011 } 1012 1013 for (i = 0; ; i++) { 1014 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 1015 if (ret) { 1016 if (ret == -ENODEV) 1017 break; /* we're done */ 1018 if (ret != -EPROBE_DEFER) 1019 dev_err(dev, "Failed to get bridge handle\n"); 1020 return ret; 1021 } 1022 1023 if (panel) 1024 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 1025 DRM_MODE_CONNECTOR_DPI); 1026 1027 encoder = drmm_plain_encoder_alloc(drm, NULL, DRM_MODE_ENCODER_DPI, NULL); 1028 if (IS_ERR(encoder)) { 1029 ret = PTR_ERR(encoder); 1030 dev_err(dev, "Failed to init encoder: %d\n", ret); 1031 return ret; 1032 } 1033 1034 encoder->possible_crtcs = 1; 1035 1036 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1037 1038 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1039 if (ret) { 1040 dev_err(dev, "Unable to attach bridge\n"); 1041 return ret; 1042 } 1043 } 1044 1045 drm_for_each_encoder(encoder, drm) { 1046 clone_mask |= BIT(drm_encoder_index(encoder)); 1047 } 1048 1049 drm_for_each_encoder(encoder, drm) { 1050 encoder->possible_clones = clone_mask; 1051 } 1052 1053 ret = drm_irq_install(drm, irq); 1054 if (ret) { 1055 dev_err(dev, "Unable to install IRQ handler\n"); 1056 return ret; 1057 } 1058 1059 ret = drm_vblank_init(drm, 1); 1060 if (ret) { 1061 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1062 return ret; 1063 } 1064 1065 drm_mode_config_reset(drm); 1066 1067 ret = clk_prepare_enable(priv->pix_clk); 1068 if (ret) { 1069 dev_err(dev, "Unable to start pixel clock\n"); 1070 return ret; 1071 } 1072 1073 if (priv->lcd_clk) { 1074 parent_clk = clk_get_parent(priv->lcd_clk); 1075 parent_rate = clk_get_rate(parent_clk); 1076 1077 /* LCD Device clock must be 3x the pixel clock for STN panels, 1078 * or 1.5x the pixel clock for TFT panels. To avoid having to 1079 * check for the LCD device clock everytime we do a mode change, 1080 * we set the LCD device clock to the highest rate possible. 1081 */ 1082 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1083 if (ret) { 1084 dev_err(dev, "Unable to set LCD clock rate\n"); 1085 goto err_pixclk_disable; 1086 } 1087 1088 ret = clk_prepare_enable(priv->lcd_clk); 1089 if (ret) { 1090 dev_err(dev, "Unable to start lcd clock\n"); 1091 goto err_pixclk_disable; 1092 } 1093 } 1094 1095 /* Set address of our DMA descriptor chain */ 1096 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0); 1097 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1); 1098 1099 /* Enable OSD if available */ 1100 if (soc_info->has_osd) 1101 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); 1102 1103 mutex_init(&priv->clk_mutex); 1104 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1105 1106 parent_clk = clk_get_parent(priv->pix_clk); 1107 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1108 if (ret) { 1109 dev_err(dev, "Unable to register clock notifier\n"); 1110 goto err_devclk_disable; 1111 } 1112 1113 ret = drm_dev_register(drm, 0); 1114 if (ret) { 1115 dev_err(dev, "Failed to register DRM driver\n"); 1116 goto err_clk_notifier_unregister; 1117 } 1118 1119 drm_fbdev_generic_setup(drm, 32); 1120 1121 return 0; 1122 1123 err_clk_notifier_unregister: 1124 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1125 err_devclk_disable: 1126 if (priv->lcd_clk) 1127 clk_disable_unprepare(priv->lcd_clk); 1128 err_pixclk_disable: 1129 clk_disable_unprepare(priv->pix_clk); 1130 return ret; 1131 } 1132 1133 static int ingenic_drm_bind_with_components(struct device *dev) 1134 { 1135 return ingenic_drm_bind(dev, true); 1136 } 1137 1138 static int compare_of(struct device *dev, void *data) 1139 { 1140 return dev->of_node == data; 1141 } 1142 1143 static void ingenic_drm_unbind(struct device *dev) 1144 { 1145 struct ingenic_drm *priv = dev_get_drvdata(dev); 1146 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1147 1148 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1149 if (priv->lcd_clk) 1150 clk_disable_unprepare(priv->lcd_clk); 1151 clk_disable_unprepare(priv->pix_clk); 1152 1153 drm_dev_unregister(&priv->drm); 1154 drm_atomic_helper_shutdown(&priv->drm); 1155 } 1156 1157 static const struct component_master_ops ingenic_master_ops = { 1158 .bind = ingenic_drm_bind_with_components, 1159 .unbind = ingenic_drm_unbind, 1160 }; 1161 1162 static int ingenic_drm_probe(struct platform_device *pdev) 1163 { 1164 struct device *dev = &pdev->dev; 1165 struct component_match *match = NULL; 1166 struct device_node *np; 1167 1168 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1169 return ingenic_drm_bind(dev, false); 1170 1171 /* IPU is at port address 8 */ 1172 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1173 if (!np) 1174 return ingenic_drm_bind(dev, false); 1175 1176 drm_of_component_match_add(dev, &match, compare_of, np); 1177 of_node_put(np); 1178 1179 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1180 } 1181 1182 static int ingenic_drm_remove(struct platform_device *pdev) 1183 { 1184 struct device *dev = &pdev->dev; 1185 1186 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1187 ingenic_drm_unbind(dev); 1188 else 1189 component_master_del(dev, &ingenic_master_ops); 1190 1191 return 0; 1192 } 1193 1194 static int __maybe_unused ingenic_drm_suspend(struct device *dev) 1195 { 1196 struct ingenic_drm *priv = dev_get_drvdata(dev); 1197 1198 return drm_mode_config_helper_suspend(&priv->drm); 1199 } 1200 1201 static int __maybe_unused ingenic_drm_resume(struct device *dev) 1202 { 1203 struct ingenic_drm *priv = dev_get_drvdata(dev); 1204 1205 return drm_mode_config_helper_resume(&priv->drm); 1206 } 1207 1208 static SIMPLE_DEV_PM_OPS(ingenic_drm_pm_ops, ingenic_drm_suspend, ingenic_drm_resume); 1209 1210 static const u32 jz4740_formats[] = { 1211 DRM_FORMAT_XRGB1555, 1212 DRM_FORMAT_RGB565, 1213 DRM_FORMAT_XRGB8888, 1214 }; 1215 1216 static const u32 jz4725b_formats_f1[] = { 1217 DRM_FORMAT_XRGB1555, 1218 DRM_FORMAT_RGB565, 1219 DRM_FORMAT_XRGB8888, 1220 }; 1221 1222 static const u32 jz4725b_formats_f0[] = { 1223 DRM_FORMAT_C8, 1224 DRM_FORMAT_XRGB1555, 1225 DRM_FORMAT_RGB565, 1226 DRM_FORMAT_XRGB8888, 1227 }; 1228 1229 static const u32 jz4770_formats_f1[] = { 1230 DRM_FORMAT_XRGB1555, 1231 DRM_FORMAT_RGB565, 1232 DRM_FORMAT_RGB888, 1233 DRM_FORMAT_XRGB8888, 1234 DRM_FORMAT_XRGB2101010, 1235 }; 1236 1237 static const u32 jz4770_formats_f0[] = { 1238 DRM_FORMAT_C8, 1239 DRM_FORMAT_XRGB1555, 1240 DRM_FORMAT_RGB565, 1241 DRM_FORMAT_RGB888, 1242 DRM_FORMAT_XRGB8888, 1243 DRM_FORMAT_XRGB2101010, 1244 }; 1245 1246 static const struct jz_soc_info jz4740_soc_info = { 1247 .needs_dev_clk = true, 1248 .has_osd = false, 1249 .max_width = 800, 1250 .max_height = 600, 1251 .formats_f1 = jz4740_formats, 1252 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1253 /* JZ4740 has only one plane */ 1254 }; 1255 1256 static const struct jz_soc_info jz4725b_soc_info = { 1257 .needs_dev_clk = false, 1258 .has_osd = true, 1259 .max_width = 800, 1260 .max_height = 600, 1261 .formats_f1 = jz4725b_formats_f1, 1262 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1263 .formats_f0 = jz4725b_formats_f0, 1264 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1265 }; 1266 1267 static const struct jz_soc_info jz4770_soc_info = { 1268 .needs_dev_clk = false, 1269 .has_osd = true, 1270 .max_width = 1280, 1271 .max_height = 720, 1272 .formats_f1 = jz4770_formats_f1, 1273 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1274 .formats_f0 = jz4770_formats_f0, 1275 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1276 }; 1277 1278 static const struct of_device_id ingenic_drm_of_match[] = { 1279 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1280 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1281 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1282 { /* sentinel */ }, 1283 }; 1284 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1285 1286 static struct platform_driver ingenic_drm_driver = { 1287 .driver = { 1288 .name = "ingenic-drm", 1289 .pm = pm_ptr(&ingenic_drm_pm_ops), 1290 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1291 }, 1292 .probe = ingenic_drm_probe, 1293 .remove = ingenic_drm_remove, 1294 }; 1295 1296 static int ingenic_drm_init(void) 1297 { 1298 int err; 1299 1300 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1301 err = platform_driver_register(ingenic_ipu_driver_ptr); 1302 if (err) 1303 return err; 1304 } 1305 1306 return platform_driver_register(&ingenic_drm_driver); 1307 } 1308 module_init(ingenic_drm_init); 1309 1310 static void ingenic_drm_exit(void) 1311 { 1312 platform_driver_unregister(&ingenic_drm_driver); 1313 1314 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1315 platform_driver_unregister(ingenic_ipu_driver_ptr); 1316 } 1317 module_exit(ingenic_drm_exit); 1318 1319 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1320 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1321 MODULE_LICENSE("GPL v2"); 1322