1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ47xx KMS driver 4 // 5 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 6 7 #include "ingenic-drm.h" 8 9 #include <linux/component.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of_device.h> 15 #include <linux/of_reserved_mem.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_bridge.h> 22 #include <drm/drm_color_mgmt.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_drv.h> 26 #include <drm/drm_gem_cma_helper.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_fb_helper.h> 29 #include <drm/drm_fourcc.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_irq.h> 32 #include <drm/drm_managed.h> 33 #include <drm/drm_of.h> 34 #include <drm/drm_panel.h> 35 #include <drm/drm_plane.h> 36 #include <drm/drm_plane_helper.h> 37 #include <drm/drm_probe_helper.h> 38 #include <drm/drm_simple_kms_helper.h> 39 #include <drm/drm_vblank.h> 40 41 struct ingenic_dma_hwdesc { 42 u32 next; 43 u32 addr; 44 u32 id; 45 u32 cmd; 46 } __aligned(16); 47 48 struct ingenic_dma_hwdescs { 49 struct ingenic_dma_hwdesc hwdesc_f0; 50 struct ingenic_dma_hwdesc hwdesc_f1; 51 struct ingenic_dma_hwdesc hwdesc_pal; 52 u16 palette[256] __aligned(16); 53 }; 54 55 struct jz_soc_info { 56 bool needs_dev_clk; 57 bool has_osd; 58 unsigned int max_width, max_height; 59 const u32 *formats_f0, *formats_f1; 60 unsigned int num_formats_f0, num_formats_f1; 61 }; 62 63 struct ingenic_drm { 64 struct drm_device drm; 65 /* 66 * f1 (aka. foreground1) is our primary plane, on top of which 67 * f0 (aka. foreground0) can be overlayed. Z-order is fixed in 68 * hardware and cannot be changed. 69 */ 70 struct drm_plane f0, f1, *ipu_plane; 71 struct drm_crtc crtc; 72 73 struct device *dev; 74 struct regmap *map; 75 struct clk *lcd_clk, *pix_clk; 76 const struct jz_soc_info *soc_info; 77 78 struct ingenic_dma_hwdescs *dma_hwdescs; 79 dma_addr_t dma_hwdescs_phys; 80 81 bool panel_is_sharp; 82 bool no_vblank; 83 84 /* 85 * clk_mutex is used to synchronize the pixel clock rate update with 86 * the VBLANK. When the pixel clock's parent clock needs to be updated, 87 * clock_nb's notifier function will lock the mutex, then wait until the 88 * next VBLANK. At that point, the parent clock's rate can be updated, 89 * and the mutex is then unlocked. If an atomic commit happens in the 90 * meantime, it will lock on the mutex, effectively waiting until the 91 * clock update process finishes. Finally, the pixel clock's rate will 92 * be recomputed when the mutex has been released, in the pending atomic 93 * commit, or a future one. 94 */ 95 struct mutex clk_mutex; 96 bool update_clk_rate; 97 struct notifier_block clock_nb; 98 }; 99 100 static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) 101 { 102 switch (reg) { 103 case JZ_REG_LCD_IID: 104 case JZ_REG_LCD_SA0: 105 case JZ_REG_LCD_FID0: 106 case JZ_REG_LCD_CMD0: 107 case JZ_REG_LCD_SA1: 108 case JZ_REG_LCD_FID1: 109 case JZ_REG_LCD_CMD1: 110 return false; 111 default: 112 return true; 113 } 114 } 115 116 static const struct regmap_config ingenic_drm_regmap_config = { 117 .reg_bits = 32, 118 .val_bits = 32, 119 .reg_stride = 4, 120 121 .max_register = JZ_REG_LCD_SIZE1, 122 .writeable_reg = ingenic_drm_writeable_reg, 123 }; 124 125 static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm) 126 { 127 return container_of(drm, struct ingenic_drm, drm); 128 } 129 130 static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) 131 { 132 return container_of(crtc, struct ingenic_drm, crtc); 133 } 134 135 static inline struct ingenic_drm *drm_nb_get_priv(struct notifier_block *nb) 136 { 137 return container_of(nb, struct ingenic_drm, clock_nb); 138 } 139 140 static int ingenic_drm_update_pixclk(struct notifier_block *nb, 141 unsigned long action, 142 void *data) 143 { 144 struct ingenic_drm *priv = drm_nb_get_priv(nb); 145 146 switch (action) { 147 case PRE_RATE_CHANGE: 148 mutex_lock(&priv->clk_mutex); 149 priv->update_clk_rate = true; 150 drm_crtc_wait_one_vblank(&priv->crtc); 151 return NOTIFY_OK; 152 default: 153 mutex_unlock(&priv->clk_mutex); 154 return NOTIFY_OK; 155 } 156 } 157 158 static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, 159 struct drm_atomic_state *state) 160 { 161 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 162 163 regmap_write(priv->map, JZ_REG_LCD_STATE, 0); 164 165 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 166 JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, 167 JZ_LCD_CTRL_ENABLE); 168 169 drm_crtc_vblank_on(crtc); 170 } 171 172 static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, 173 struct drm_atomic_state *state) 174 { 175 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 176 unsigned int var; 177 178 drm_crtc_vblank_off(crtc); 179 180 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 181 JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE); 182 183 regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var, 184 var & JZ_LCD_STATE_DISABLED, 185 1000, 0); 186 } 187 188 static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, 189 struct drm_display_mode *mode) 190 { 191 unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht; 192 193 vpe = mode->vsync_end - mode->vsync_start; 194 vds = mode->vtotal - mode->vsync_start; 195 vde = vds + mode->vdisplay; 196 vt = vde + mode->vsync_start - mode->vdisplay; 197 198 hpe = mode->hsync_end - mode->hsync_start; 199 hds = mode->htotal - mode->hsync_start; 200 hde = hds + mode->hdisplay; 201 ht = hde + mode->hsync_start - mode->hdisplay; 202 203 regmap_write(priv->map, JZ_REG_LCD_VSYNC, 204 0 << JZ_LCD_VSYNC_VPS_OFFSET | 205 vpe << JZ_LCD_VSYNC_VPE_OFFSET); 206 207 regmap_write(priv->map, JZ_REG_LCD_HSYNC, 208 0 << JZ_LCD_HSYNC_HPS_OFFSET | 209 hpe << JZ_LCD_HSYNC_HPE_OFFSET); 210 211 regmap_write(priv->map, JZ_REG_LCD_VAT, 212 ht << JZ_LCD_VAT_HT_OFFSET | 213 vt << JZ_LCD_VAT_VT_OFFSET); 214 215 regmap_write(priv->map, JZ_REG_LCD_DAH, 216 hds << JZ_LCD_DAH_HDS_OFFSET | 217 hde << JZ_LCD_DAH_HDE_OFFSET); 218 regmap_write(priv->map, JZ_REG_LCD_DAV, 219 vds << JZ_LCD_DAV_VDS_OFFSET | 220 vde << JZ_LCD_DAV_VDE_OFFSET); 221 222 if (priv->panel_is_sharp) { 223 regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1)); 224 regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1)); 225 regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1)); 226 regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16); 227 } 228 229 regmap_set_bits(priv->map, JZ_REG_LCD_CTRL, 230 JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); 231 232 /* 233 * IPU restart - specify how much time the LCDC will wait before 234 * transferring a new frame from the IPU. The value is the one 235 * suggested in the programming manual. 236 */ 237 regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN | 238 (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); 239 } 240 241 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, 242 struct drm_atomic_state *state) 243 { 244 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 245 crtc); 246 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 247 struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; 248 249 if (crtc_state->gamma_lut && 250 drm_color_lut_size(crtc_state->gamma_lut) != ARRAY_SIZE(priv->dma_hwdescs->palette)) { 251 dev_dbg(priv->dev, "Invalid palette size\n"); 252 return -EINVAL; 253 } 254 255 if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { 256 f1_state = drm_atomic_get_plane_state(crtc_state->state, 257 &priv->f1); 258 if (IS_ERR(f1_state)) 259 return PTR_ERR(f1_state); 260 261 f0_state = drm_atomic_get_plane_state(crtc_state->state, 262 &priv->f0); 263 if (IS_ERR(f0_state)) 264 return PTR_ERR(f0_state); 265 266 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { 267 ipu_state = drm_atomic_get_plane_state(crtc_state->state, 268 priv->ipu_plane); 269 if (IS_ERR(ipu_state)) 270 return PTR_ERR(ipu_state); 271 272 /* IPU and F1 planes cannot be enabled at the same time. */ 273 if (f1_state->fb && ipu_state->fb) { 274 dev_dbg(priv->dev, "Cannot enable both F1 and IPU\n"); 275 return -EINVAL; 276 } 277 } 278 279 /* If all the planes are disabled, we won't get a VBLANK IRQ */ 280 priv->no_vblank = !f1_state->fb && !f0_state->fb && 281 !(ipu_state && ipu_state->fb); 282 } 283 284 return 0; 285 } 286 287 static enum drm_mode_status 288 ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) 289 { 290 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 291 long rate; 292 293 if (mode->hdisplay > priv->soc_info->max_width) 294 return MODE_BAD_HVALUE; 295 if (mode->vdisplay > priv->soc_info->max_height) 296 return MODE_BAD_VVALUE; 297 298 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); 299 if (rate < 0) 300 return MODE_CLOCK_RANGE; 301 302 return MODE_OK; 303 } 304 305 static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, 306 struct drm_atomic_state *state) 307 { 308 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 309 u32 ctrl = 0; 310 311 if (priv->soc_info->has_osd && 312 drm_atomic_crtc_needs_modeset(crtc->state)) { 313 /* 314 * If IPU plane is enabled, enable IPU as source for the F1 315 * plane; otherwise use regular DMA. 316 */ 317 if (priv->ipu_plane && priv->ipu_plane->state->fb) 318 ctrl |= JZ_LCD_OSDCTRL_IPU; 319 320 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 321 JZ_LCD_OSDCTRL_IPU, ctrl); 322 } 323 } 324 325 static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, 326 struct drm_atomic_state *state) 327 { 328 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 329 struct drm_crtc_state *crtc_state = crtc->state; 330 struct drm_pending_vblank_event *event = crtc_state->event; 331 332 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 333 ingenic_drm_crtc_update_timings(priv, &crtc_state->mode); 334 priv->update_clk_rate = true; 335 } 336 337 if (priv->update_clk_rate) { 338 mutex_lock(&priv->clk_mutex); 339 clk_set_rate(priv->pix_clk, 340 crtc_state->adjusted_mode.clock * 1000); 341 priv->update_clk_rate = false; 342 mutex_unlock(&priv->clk_mutex); 343 } 344 345 if (event) { 346 crtc_state->event = NULL; 347 348 spin_lock_irq(&crtc->dev->event_lock); 349 if (drm_crtc_vblank_get(crtc) == 0) 350 drm_crtc_arm_vblank_event(crtc, event); 351 else 352 drm_crtc_send_vblank_event(crtc, event); 353 spin_unlock_irq(&crtc->dev->event_lock); 354 } 355 } 356 357 static int ingenic_drm_plane_atomic_check(struct drm_plane *plane, 358 struct drm_plane_state *state) 359 { 360 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 361 struct drm_crtc_state *crtc_state; 362 struct drm_crtc *crtc = state->crtc ?: plane->state->crtc; 363 int ret; 364 365 if (!crtc) 366 return 0; 367 368 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 369 if (WARN_ON(!crtc_state)) 370 return -EINVAL; 371 372 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 373 DRM_PLANE_HELPER_NO_SCALING, 374 DRM_PLANE_HELPER_NO_SCALING, 375 priv->soc_info->has_osd, 376 true); 377 if (ret) 378 return ret; 379 380 /* 381 * If OSD is not available, check that the width/height match. 382 * Note that state->src_* are in 16.16 fixed-point format. 383 */ 384 if (!priv->soc_info->has_osd && 385 (state->src_x != 0 || 386 (state->src_w >> 16) != state->crtc_w || 387 (state->src_h >> 16) != state->crtc_h)) 388 return -EINVAL; 389 390 /* 391 * Require full modeset if enabling or disabling a plane, or changing 392 * its position, size or depth. 393 */ 394 if (priv->soc_info->has_osd && 395 (!plane->state->fb || !state->fb || 396 plane->state->crtc_x != state->crtc_x || 397 plane->state->crtc_y != state->crtc_y || 398 plane->state->crtc_w != state->crtc_w || 399 plane->state->crtc_h != state->crtc_h || 400 plane->state->fb->format->format != state->fb->format->format)) 401 crtc_state->mode_changed = true; 402 403 return 0; 404 } 405 406 static void ingenic_drm_plane_enable(struct ingenic_drm *priv, 407 struct drm_plane *plane) 408 { 409 unsigned int en_bit; 410 411 if (priv->soc_info->has_osd) { 412 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 413 en_bit = JZ_LCD_OSDC_F1EN; 414 else 415 en_bit = JZ_LCD_OSDC_F0EN; 416 417 regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 418 } 419 } 420 421 void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane) 422 { 423 struct ingenic_drm *priv = dev_get_drvdata(dev); 424 unsigned int en_bit; 425 426 if (priv->soc_info->has_osd) { 427 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 428 en_bit = JZ_LCD_OSDC_F1EN; 429 else 430 en_bit = JZ_LCD_OSDC_F0EN; 431 432 regmap_clear_bits(priv->map, JZ_REG_LCD_OSDC, en_bit); 433 } 434 } 435 436 static void ingenic_drm_plane_atomic_disable(struct drm_plane *plane, 437 struct drm_plane_state *old_state) 438 { 439 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 440 441 ingenic_drm_plane_disable(priv->dev, plane); 442 } 443 444 void ingenic_drm_plane_config(struct device *dev, 445 struct drm_plane *plane, u32 fourcc) 446 { 447 struct ingenic_drm *priv = dev_get_drvdata(dev); 448 struct drm_plane_state *state = plane->state; 449 unsigned int xy_reg, size_reg; 450 unsigned int ctrl = 0; 451 452 ingenic_drm_plane_enable(priv, plane); 453 454 if (priv->soc_info->has_osd && 455 plane->type == DRM_PLANE_TYPE_PRIMARY) { 456 switch (fourcc) { 457 case DRM_FORMAT_XRGB1555: 458 ctrl |= JZ_LCD_OSDCTRL_RGB555; 459 fallthrough; 460 case DRM_FORMAT_RGB565: 461 ctrl |= JZ_LCD_OSDCTRL_BPP_15_16; 462 break; 463 case DRM_FORMAT_RGB888: 464 ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP; 465 break; 466 case DRM_FORMAT_XRGB8888: 467 ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; 468 break; 469 case DRM_FORMAT_XRGB2101010: 470 ctrl |= JZ_LCD_OSDCTRL_BPP_30; 471 break; 472 } 473 474 regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, 475 JZ_LCD_OSDCTRL_BPP_MASK, ctrl); 476 } else { 477 switch (fourcc) { 478 case DRM_FORMAT_C8: 479 ctrl |= JZ_LCD_CTRL_BPP_8; 480 break; 481 case DRM_FORMAT_XRGB1555: 482 ctrl |= JZ_LCD_CTRL_RGB555; 483 fallthrough; 484 case DRM_FORMAT_RGB565: 485 ctrl |= JZ_LCD_CTRL_BPP_15_16; 486 break; 487 case DRM_FORMAT_RGB888: 488 ctrl |= JZ_LCD_CTRL_BPP_24_COMP; 489 break; 490 case DRM_FORMAT_XRGB8888: 491 ctrl |= JZ_LCD_CTRL_BPP_18_24; 492 break; 493 case DRM_FORMAT_XRGB2101010: 494 ctrl |= JZ_LCD_CTRL_BPP_30; 495 break; 496 } 497 498 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 499 JZ_LCD_CTRL_BPP_MASK, ctrl); 500 } 501 502 if (priv->soc_info->has_osd) { 503 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 504 xy_reg = JZ_REG_LCD_XYP1; 505 size_reg = JZ_REG_LCD_SIZE1; 506 } else { 507 xy_reg = JZ_REG_LCD_XYP0; 508 size_reg = JZ_REG_LCD_SIZE0; 509 } 510 511 regmap_write(priv->map, xy_reg, 512 state->crtc_x << JZ_LCD_XYP01_XPOS_LSB | 513 state->crtc_y << JZ_LCD_XYP01_YPOS_LSB); 514 regmap_write(priv->map, size_reg, 515 state->crtc_w << JZ_LCD_SIZE01_WIDTH_LSB | 516 state->crtc_h << JZ_LCD_SIZE01_HEIGHT_LSB); 517 } 518 } 519 520 static void ingenic_drm_update_palette(struct ingenic_drm *priv, 521 const struct drm_color_lut *lut) 522 { 523 unsigned int i; 524 525 for (i = 0; i < ARRAY_SIZE(priv->dma_hwdescs->palette); i++) { 526 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11 527 | drm_color_lut_extract(lut[i].green, 6) << 5 528 | drm_color_lut_extract(lut[i].blue, 5); 529 530 priv->dma_hwdescs->palette[i] = color; 531 } 532 } 533 534 static void ingenic_drm_plane_atomic_update(struct drm_plane *plane, 535 struct drm_plane_state *oldstate) 536 { 537 struct ingenic_drm *priv = drm_device_get_priv(plane->dev); 538 struct drm_plane_state *state = plane->state; 539 struct drm_crtc_state *crtc_state; 540 struct ingenic_dma_hwdesc *hwdesc; 541 unsigned int width, height, cpp, offset; 542 dma_addr_t addr; 543 u32 fourcc; 544 545 if (state && state->fb) { 546 crtc_state = state->crtc->state; 547 548 addr = drm_fb_cma_get_gem_addr(state->fb, state, 0); 549 width = state->src_w >> 16; 550 height = state->src_h >> 16; 551 cpp = state->fb->format->cpp[0]; 552 553 if (priv->soc_info->has_osd && plane->type == DRM_PLANE_TYPE_OVERLAY) 554 hwdesc = &priv->dma_hwdescs->hwdesc_f0; 555 else 556 hwdesc = &priv->dma_hwdescs->hwdesc_f1; 557 558 hwdesc->addr = addr; 559 hwdesc->cmd = JZ_LCD_CMD_EOF_IRQ | (width * height * cpp / 4); 560 561 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 562 fourcc = state->fb->format->format; 563 564 ingenic_drm_plane_config(priv->dev, plane, fourcc); 565 566 if (fourcc == DRM_FORMAT_C8) 567 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_pal); 568 else 569 offset = offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 570 571 priv->dma_hwdescs->hwdesc_f0.next = priv->dma_hwdescs_phys + offset; 572 573 crtc_state->color_mgmt_changed = fourcc == DRM_FORMAT_C8; 574 } 575 576 if (crtc_state->color_mgmt_changed) 577 ingenic_drm_update_palette(priv, crtc_state->gamma_lut->data); 578 } 579 } 580 581 static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, 582 struct drm_crtc_state *crtc_state, 583 struct drm_connector_state *conn_state) 584 { 585 struct ingenic_drm *priv = drm_device_get_priv(encoder->dev); 586 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 587 struct drm_connector *conn = conn_state->connector; 588 struct drm_display_info *info = &conn->display_info; 589 unsigned int cfg; 590 591 priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS; 592 593 if (priv->panel_is_sharp) { 594 cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY; 595 } else { 596 cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE 597 | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE; 598 } 599 600 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 601 cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW; 602 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 603 cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW; 604 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 605 cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW; 606 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 607 cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE; 608 609 if (!priv->panel_is_sharp) { 610 if (conn->connector_type == DRM_MODE_CONNECTOR_TV) { 611 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 612 cfg |= JZ_LCD_CFG_MODE_TV_OUT_I; 613 else 614 cfg |= JZ_LCD_CFG_MODE_TV_OUT_P; 615 } else { 616 switch (*info->bus_formats) { 617 case MEDIA_BUS_FMT_RGB565_1X16: 618 cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT; 619 break; 620 case MEDIA_BUS_FMT_RGB666_1X18: 621 cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT; 622 break; 623 case MEDIA_BUS_FMT_RGB888_1X24: 624 cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; 625 break; 626 case MEDIA_BUS_FMT_RGB888_3X8: 627 cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; 628 break; 629 default: 630 break; 631 } 632 } 633 } 634 635 regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); 636 } 637 638 static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, 639 struct drm_crtc_state *crtc_state, 640 struct drm_connector_state *conn_state) 641 { 642 struct drm_display_info *info = &conn_state->connector->display_info; 643 644 if (info->num_bus_formats != 1) 645 return -EINVAL; 646 647 if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) 648 return 0; 649 650 switch (*info->bus_formats) { 651 case MEDIA_BUS_FMT_RGB565_1X16: 652 case MEDIA_BUS_FMT_RGB666_1X18: 653 case MEDIA_BUS_FMT_RGB888_1X24: 654 case MEDIA_BUS_FMT_RGB888_3X8: 655 return 0; 656 default: 657 return -EINVAL; 658 } 659 } 660 661 static void ingenic_drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state) 662 { 663 /* 664 * Just your regular drm_atomic_helper_commit_tail(), but only calls 665 * drm_atomic_helper_wait_for_vblanks() if priv->no_vblank. 666 */ 667 struct drm_device *dev = old_state->dev; 668 struct ingenic_drm *priv = drm_device_get_priv(dev); 669 670 drm_atomic_helper_commit_modeset_disables(dev, old_state); 671 672 drm_atomic_helper_commit_planes(dev, old_state, 0); 673 674 drm_atomic_helper_commit_modeset_enables(dev, old_state); 675 676 drm_atomic_helper_commit_hw_done(old_state); 677 678 if (!priv->no_vblank) 679 drm_atomic_helper_wait_for_vblanks(dev, old_state); 680 681 drm_atomic_helper_cleanup_planes(dev, old_state); 682 } 683 684 static irqreturn_t ingenic_drm_irq_handler(int irq, void *arg) 685 { 686 struct ingenic_drm *priv = drm_device_get_priv(arg); 687 unsigned int state; 688 689 regmap_read(priv->map, JZ_REG_LCD_STATE, &state); 690 691 regmap_update_bits(priv->map, JZ_REG_LCD_STATE, 692 JZ_LCD_STATE_EOF_IRQ, 0); 693 694 if (state & JZ_LCD_STATE_EOF_IRQ) 695 drm_crtc_handle_vblank(&priv->crtc); 696 697 return IRQ_HANDLED; 698 } 699 700 static int ingenic_drm_enable_vblank(struct drm_crtc *crtc) 701 { 702 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 703 704 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, 705 JZ_LCD_CTRL_EOF_IRQ, JZ_LCD_CTRL_EOF_IRQ); 706 707 return 0; 708 } 709 710 static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) 711 { 712 struct ingenic_drm *priv = drm_crtc_get_priv(crtc); 713 714 regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_EOF_IRQ, 0); 715 } 716 717 DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops); 718 719 static struct drm_driver ingenic_drm_driver_data = { 720 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 721 .name = "ingenic-drm", 722 .desc = "DRM module for Ingenic SoCs", 723 .date = "20200716", 724 .major = 1, 725 .minor = 1, 726 .patchlevel = 0, 727 728 .fops = &ingenic_drm_fops, 729 DRM_GEM_CMA_DRIVER_OPS, 730 731 .irq_handler = ingenic_drm_irq_handler, 732 }; 733 734 static const struct drm_plane_funcs ingenic_drm_primary_plane_funcs = { 735 .update_plane = drm_atomic_helper_update_plane, 736 .disable_plane = drm_atomic_helper_disable_plane, 737 .reset = drm_atomic_helper_plane_reset, 738 .destroy = drm_plane_cleanup, 739 740 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 741 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 742 }; 743 744 static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { 745 .set_config = drm_atomic_helper_set_config, 746 .page_flip = drm_atomic_helper_page_flip, 747 .reset = drm_atomic_helper_crtc_reset, 748 .destroy = drm_crtc_cleanup, 749 750 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 751 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 752 753 .enable_vblank = ingenic_drm_enable_vblank, 754 .disable_vblank = ingenic_drm_disable_vblank, 755 756 .gamma_set = drm_atomic_helper_legacy_gamma_set, 757 }; 758 759 static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { 760 .atomic_update = ingenic_drm_plane_atomic_update, 761 .atomic_check = ingenic_drm_plane_atomic_check, 762 .atomic_disable = ingenic_drm_plane_atomic_disable, 763 .prepare_fb = drm_gem_fb_prepare_fb, 764 }; 765 766 static const struct drm_crtc_helper_funcs ingenic_drm_crtc_helper_funcs = { 767 .atomic_enable = ingenic_drm_crtc_atomic_enable, 768 .atomic_disable = ingenic_drm_crtc_atomic_disable, 769 .atomic_begin = ingenic_drm_crtc_atomic_begin, 770 .atomic_flush = ingenic_drm_crtc_atomic_flush, 771 .atomic_check = ingenic_drm_crtc_atomic_check, 772 .mode_valid = ingenic_drm_crtc_mode_valid, 773 }; 774 775 static const struct drm_encoder_helper_funcs ingenic_drm_encoder_helper_funcs = { 776 .atomic_mode_set = ingenic_drm_encoder_atomic_mode_set, 777 .atomic_check = ingenic_drm_encoder_atomic_check, 778 }; 779 780 static const struct drm_mode_config_funcs ingenic_drm_mode_config_funcs = { 781 .fb_create = drm_gem_fb_create, 782 .output_poll_changed = drm_fb_helper_output_poll_changed, 783 .atomic_check = drm_atomic_helper_check, 784 .atomic_commit = drm_atomic_helper_commit, 785 }; 786 787 static struct drm_mode_config_helper_funcs ingenic_drm_mode_config_helpers = { 788 .atomic_commit_tail = ingenic_drm_atomic_helper_commit_tail, 789 }; 790 791 static void ingenic_drm_unbind_all(void *d) 792 { 793 struct ingenic_drm *priv = d; 794 795 component_unbind_all(priv->dev, &priv->drm); 796 } 797 798 static void __maybe_unused ingenic_drm_release_rmem(void *d) 799 { 800 of_reserved_mem_device_release(d); 801 } 802 803 static int ingenic_drm_bind(struct device *dev, bool has_components) 804 { 805 struct platform_device *pdev = to_platform_device(dev); 806 const struct jz_soc_info *soc_info; 807 struct ingenic_drm *priv; 808 struct clk *parent_clk; 809 struct drm_bridge *bridge; 810 struct drm_panel *panel; 811 struct drm_encoder *encoder; 812 struct drm_device *drm; 813 void __iomem *base; 814 long parent_rate; 815 unsigned int i, clone_mask = 0; 816 dma_addr_t dma_hwdesc_phys_f0, dma_hwdesc_phys_f1; 817 int ret, irq; 818 819 soc_info = of_device_get_match_data(dev); 820 if (!soc_info) { 821 dev_err(dev, "Missing platform data\n"); 822 return -EINVAL; 823 } 824 825 if (IS_ENABLED(CONFIG_OF_RESERVED_MEM)) { 826 ret = of_reserved_mem_device_init(dev); 827 828 if (ret && ret != -ENODEV) 829 dev_warn(dev, "Failed to get reserved memory: %d\n", ret); 830 831 if (!ret) { 832 ret = devm_add_action_or_reset(dev, ingenic_drm_release_rmem, dev); 833 if (ret) 834 return ret; 835 } 836 } 837 838 priv = devm_drm_dev_alloc(dev, &ingenic_drm_driver_data, 839 struct ingenic_drm, drm); 840 if (IS_ERR(priv)) 841 return PTR_ERR(priv); 842 843 priv->soc_info = soc_info; 844 priv->dev = dev; 845 drm = &priv->drm; 846 847 platform_set_drvdata(pdev, priv); 848 849 ret = drmm_mode_config_init(drm); 850 if (ret) 851 return ret; 852 853 drm->mode_config.min_width = 0; 854 drm->mode_config.min_height = 0; 855 drm->mode_config.max_width = soc_info->max_width; 856 drm->mode_config.max_height = 4095; 857 drm->mode_config.funcs = &ingenic_drm_mode_config_funcs; 858 drm->mode_config.helper_private = &ingenic_drm_mode_config_helpers; 859 860 base = devm_platform_ioremap_resource(pdev, 0); 861 if (IS_ERR(base)) { 862 dev_err(dev, "Failed to get memory resource\n"); 863 return PTR_ERR(base); 864 } 865 866 priv->map = devm_regmap_init_mmio(dev, base, 867 &ingenic_drm_regmap_config); 868 if (IS_ERR(priv->map)) { 869 dev_err(dev, "Failed to create regmap\n"); 870 return PTR_ERR(priv->map); 871 } 872 873 irq = platform_get_irq(pdev, 0); 874 if (irq < 0) 875 return irq; 876 877 if (soc_info->needs_dev_clk) { 878 priv->lcd_clk = devm_clk_get(dev, "lcd"); 879 if (IS_ERR(priv->lcd_clk)) { 880 dev_err(dev, "Failed to get lcd clock\n"); 881 return PTR_ERR(priv->lcd_clk); 882 } 883 } 884 885 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); 886 if (IS_ERR(priv->pix_clk)) { 887 dev_err(dev, "Failed to get pixel clock\n"); 888 return PTR_ERR(priv->pix_clk); 889 } 890 891 priv->dma_hwdescs = dmam_alloc_coherent(dev, 892 sizeof(*priv->dma_hwdescs), 893 &priv->dma_hwdescs_phys, 894 GFP_KERNEL); 895 if (!priv->dma_hwdescs) 896 return -ENOMEM; 897 898 899 /* Configure DMA hwdesc for foreground0 plane */ 900 dma_hwdesc_phys_f0 = priv->dma_hwdescs_phys 901 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 902 priv->dma_hwdescs->hwdesc_f0.next = dma_hwdesc_phys_f0; 903 priv->dma_hwdescs->hwdesc_f0.id = 0xf0; 904 905 /* Configure DMA hwdesc for foreground1 plane */ 906 dma_hwdesc_phys_f1 = priv->dma_hwdescs_phys 907 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f1); 908 priv->dma_hwdescs->hwdesc_f1.next = dma_hwdesc_phys_f1; 909 priv->dma_hwdescs->hwdesc_f1.id = 0xf1; 910 911 /* Configure DMA hwdesc for palette */ 912 priv->dma_hwdescs->hwdesc_pal.next = priv->dma_hwdescs_phys 913 + offsetof(struct ingenic_dma_hwdescs, hwdesc_f0); 914 priv->dma_hwdescs->hwdesc_pal.id = 0xc0; 915 priv->dma_hwdescs->hwdesc_pal.addr = priv->dma_hwdescs_phys 916 + offsetof(struct ingenic_dma_hwdescs, palette); 917 priv->dma_hwdescs->hwdesc_pal.cmd = JZ_LCD_CMD_ENABLE_PAL 918 | (sizeof(priv->dma_hwdescs->palette) / 4); 919 920 if (soc_info->has_osd) 921 priv->ipu_plane = drm_plane_from_index(drm, 0); 922 923 drm_plane_helper_add(&priv->f1, &ingenic_drm_plane_helper_funcs); 924 925 ret = drm_universal_plane_init(drm, &priv->f1, 1, 926 &ingenic_drm_primary_plane_funcs, 927 priv->soc_info->formats_f1, 928 priv->soc_info->num_formats_f1, 929 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 930 if (ret) { 931 dev_err(dev, "Failed to register plane: %i\n", ret); 932 return ret; 933 } 934 935 drm_crtc_helper_add(&priv->crtc, &ingenic_drm_crtc_helper_funcs); 936 937 ret = drm_crtc_init_with_planes(drm, &priv->crtc, &priv->f1, 938 NULL, &ingenic_drm_crtc_funcs, NULL); 939 if (ret) { 940 dev_err(dev, "Failed to init CRTC: %i\n", ret); 941 return ret; 942 } 943 944 drm_crtc_enable_color_mgmt(&priv->crtc, 0, false, 945 ARRAY_SIZE(priv->dma_hwdescs->palette)); 946 947 if (soc_info->has_osd) { 948 drm_plane_helper_add(&priv->f0, 949 &ingenic_drm_plane_helper_funcs); 950 951 ret = drm_universal_plane_init(drm, &priv->f0, 1, 952 &ingenic_drm_primary_plane_funcs, 953 priv->soc_info->formats_f0, 954 priv->soc_info->num_formats_f0, 955 NULL, DRM_PLANE_TYPE_OVERLAY, 956 NULL); 957 if (ret) { 958 dev_err(dev, "Failed to register overlay plane: %i\n", 959 ret); 960 return ret; 961 } 962 963 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && has_components) { 964 ret = component_bind_all(dev, drm); 965 if (ret) { 966 if (ret != -EPROBE_DEFER) 967 dev_err(dev, "Failed to bind components: %i\n", ret); 968 return ret; 969 } 970 971 ret = devm_add_action_or_reset(dev, ingenic_drm_unbind_all, priv); 972 if (ret) 973 return ret; 974 975 priv->ipu_plane = drm_plane_from_index(drm, 2); 976 if (!priv->ipu_plane) { 977 dev_err(dev, "Failed to retrieve IPU plane\n"); 978 return -EINVAL; 979 } 980 } 981 } 982 983 for (i = 0; ; i++) { 984 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, i, &panel, &bridge); 985 if (ret) { 986 if (ret == -ENODEV) 987 break; /* we're done */ 988 if (ret != -EPROBE_DEFER) 989 dev_err(dev, "Failed to get bridge handle\n"); 990 return ret; 991 } 992 993 if (panel) 994 bridge = devm_drm_panel_bridge_add_typed(dev, panel, 995 DRM_MODE_CONNECTOR_DPI); 996 997 encoder = devm_kzalloc(dev, sizeof(*encoder), GFP_KERNEL); 998 if (!encoder) 999 return -ENOMEM; 1000 1001 encoder->possible_crtcs = 1; 1002 1003 drm_encoder_helper_add(encoder, &ingenic_drm_encoder_helper_funcs); 1004 1005 ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_DPI); 1006 if (ret) { 1007 dev_err(dev, "Failed to init encoder: %d\n", ret); 1008 return ret; 1009 } 1010 1011 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1012 if (ret) { 1013 dev_err(dev, "Unable to attach bridge\n"); 1014 return ret; 1015 } 1016 } 1017 1018 drm_for_each_encoder(encoder, drm) { 1019 clone_mask |= BIT(drm_encoder_index(encoder)); 1020 } 1021 1022 drm_for_each_encoder(encoder, drm) { 1023 encoder->possible_clones = clone_mask; 1024 } 1025 1026 ret = drm_irq_install(drm, irq); 1027 if (ret) { 1028 dev_err(dev, "Unable to install IRQ handler\n"); 1029 return ret; 1030 } 1031 1032 ret = drm_vblank_init(drm, 1); 1033 if (ret) { 1034 dev_err(dev, "Failed calling drm_vblank_init()\n"); 1035 return ret; 1036 } 1037 1038 drm_mode_config_reset(drm); 1039 1040 ret = clk_prepare_enable(priv->pix_clk); 1041 if (ret) { 1042 dev_err(dev, "Unable to start pixel clock\n"); 1043 return ret; 1044 } 1045 1046 if (priv->lcd_clk) { 1047 parent_clk = clk_get_parent(priv->lcd_clk); 1048 parent_rate = clk_get_rate(parent_clk); 1049 1050 /* LCD Device clock must be 3x the pixel clock for STN panels, 1051 * or 1.5x the pixel clock for TFT panels. To avoid having to 1052 * check for the LCD device clock everytime we do a mode change, 1053 * we set the LCD device clock to the highest rate possible. 1054 */ 1055 ret = clk_set_rate(priv->lcd_clk, parent_rate); 1056 if (ret) { 1057 dev_err(dev, "Unable to set LCD clock rate\n"); 1058 goto err_pixclk_disable; 1059 } 1060 1061 ret = clk_prepare_enable(priv->lcd_clk); 1062 if (ret) { 1063 dev_err(dev, "Unable to start lcd clock\n"); 1064 goto err_pixclk_disable; 1065 } 1066 } 1067 1068 /* Set address of our DMA descriptor chain */ 1069 regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0); 1070 regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1); 1071 1072 /* Enable OSD if available */ 1073 if (soc_info->has_osd) 1074 regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); 1075 1076 mutex_init(&priv->clk_mutex); 1077 priv->clock_nb.notifier_call = ingenic_drm_update_pixclk; 1078 1079 parent_clk = clk_get_parent(priv->pix_clk); 1080 ret = clk_notifier_register(parent_clk, &priv->clock_nb); 1081 if (ret) { 1082 dev_err(dev, "Unable to register clock notifier\n"); 1083 goto err_devclk_disable; 1084 } 1085 1086 ret = drm_dev_register(drm, 0); 1087 if (ret) { 1088 dev_err(dev, "Failed to register DRM driver\n"); 1089 goto err_clk_notifier_unregister; 1090 } 1091 1092 drm_fbdev_generic_setup(drm, 32); 1093 1094 return 0; 1095 1096 err_clk_notifier_unregister: 1097 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1098 err_devclk_disable: 1099 if (priv->lcd_clk) 1100 clk_disable_unprepare(priv->lcd_clk); 1101 err_pixclk_disable: 1102 clk_disable_unprepare(priv->pix_clk); 1103 return ret; 1104 } 1105 1106 static int ingenic_drm_bind_with_components(struct device *dev) 1107 { 1108 return ingenic_drm_bind(dev, true); 1109 } 1110 1111 static int compare_of(struct device *dev, void *data) 1112 { 1113 return dev->of_node == data; 1114 } 1115 1116 static void ingenic_drm_unbind(struct device *dev) 1117 { 1118 struct ingenic_drm *priv = dev_get_drvdata(dev); 1119 struct clk *parent_clk = clk_get_parent(priv->pix_clk); 1120 1121 clk_notifier_unregister(parent_clk, &priv->clock_nb); 1122 if (priv->lcd_clk) 1123 clk_disable_unprepare(priv->lcd_clk); 1124 clk_disable_unprepare(priv->pix_clk); 1125 1126 drm_dev_unregister(&priv->drm); 1127 drm_atomic_helper_shutdown(&priv->drm); 1128 } 1129 1130 static const struct component_master_ops ingenic_master_ops = { 1131 .bind = ingenic_drm_bind_with_components, 1132 .unbind = ingenic_drm_unbind, 1133 }; 1134 1135 static int ingenic_drm_probe(struct platform_device *pdev) 1136 { 1137 struct device *dev = &pdev->dev; 1138 struct component_match *match = NULL; 1139 struct device_node *np; 1140 1141 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1142 return ingenic_drm_bind(dev, false); 1143 1144 /* IPU is at port address 8 */ 1145 np = of_graph_get_remote_node(dev->of_node, 8, 0); 1146 if (!np) 1147 return ingenic_drm_bind(dev, false); 1148 1149 drm_of_component_match_add(dev, &match, compare_of, np); 1150 of_node_put(np); 1151 1152 return component_master_add_with_match(dev, &ingenic_master_ops, match); 1153 } 1154 1155 static int ingenic_drm_remove(struct platform_device *pdev) 1156 { 1157 struct device *dev = &pdev->dev; 1158 1159 if (!IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1160 ingenic_drm_unbind(dev); 1161 else 1162 component_master_del(dev, &ingenic_master_ops); 1163 1164 return 0; 1165 } 1166 1167 static const u32 jz4740_formats[] = { 1168 DRM_FORMAT_XRGB1555, 1169 DRM_FORMAT_RGB565, 1170 DRM_FORMAT_XRGB8888, 1171 }; 1172 1173 static const u32 jz4725b_formats_f1[] = { 1174 DRM_FORMAT_XRGB1555, 1175 DRM_FORMAT_RGB565, 1176 DRM_FORMAT_XRGB8888, 1177 }; 1178 1179 static const u32 jz4725b_formats_f0[] = { 1180 DRM_FORMAT_C8, 1181 DRM_FORMAT_XRGB1555, 1182 DRM_FORMAT_RGB565, 1183 DRM_FORMAT_XRGB8888, 1184 }; 1185 1186 static const u32 jz4770_formats_f1[] = { 1187 DRM_FORMAT_XRGB1555, 1188 DRM_FORMAT_RGB565, 1189 DRM_FORMAT_RGB888, 1190 DRM_FORMAT_XRGB8888, 1191 DRM_FORMAT_XRGB2101010, 1192 }; 1193 1194 static const u32 jz4770_formats_f0[] = { 1195 DRM_FORMAT_C8, 1196 DRM_FORMAT_XRGB1555, 1197 DRM_FORMAT_RGB565, 1198 DRM_FORMAT_RGB888, 1199 DRM_FORMAT_XRGB8888, 1200 DRM_FORMAT_XRGB2101010, 1201 }; 1202 1203 static const struct jz_soc_info jz4740_soc_info = { 1204 .needs_dev_clk = true, 1205 .has_osd = false, 1206 .max_width = 800, 1207 .max_height = 600, 1208 .formats_f1 = jz4740_formats, 1209 .num_formats_f1 = ARRAY_SIZE(jz4740_formats), 1210 /* JZ4740 has only one plane */ 1211 }; 1212 1213 static const struct jz_soc_info jz4725b_soc_info = { 1214 .needs_dev_clk = false, 1215 .has_osd = true, 1216 .max_width = 800, 1217 .max_height = 600, 1218 .formats_f1 = jz4725b_formats_f1, 1219 .num_formats_f1 = ARRAY_SIZE(jz4725b_formats_f1), 1220 .formats_f0 = jz4725b_formats_f0, 1221 .num_formats_f0 = ARRAY_SIZE(jz4725b_formats_f0), 1222 }; 1223 1224 static const struct jz_soc_info jz4770_soc_info = { 1225 .needs_dev_clk = false, 1226 .has_osd = true, 1227 .max_width = 1280, 1228 .max_height = 720, 1229 .formats_f1 = jz4770_formats_f1, 1230 .num_formats_f1 = ARRAY_SIZE(jz4770_formats_f1), 1231 .formats_f0 = jz4770_formats_f0, 1232 .num_formats_f0 = ARRAY_SIZE(jz4770_formats_f0), 1233 }; 1234 1235 static const struct of_device_id ingenic_drm_of_match[] = { 1236 { .compatible = "ingenic,jz4740-lcd", .data = &jz4740_soc_info }, 1237 { .compatible = "ingenic,jz4725b-lcd", .data = &jz4725b_soc_info }, 1238 { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info }, 1239 { /* sentinel */ }, 1240 }; 1241 MODULE_DEVICE_TABLE(of, ingenic_drm_of_match); 1242 1243 static struct platform_driver ingenic_drm_driver = { 1244 .driver = { 1245 .name = "ingenic-drm", 1246 .of_match_table = of_match_ptr(ingenic_drm_of_match), 1247 }, 1248 .probe = ingenic_drm_probe, 1249 .remove = ingenic_drm_remove, 1250 }; 1251 1252 static int ingenic_drm_init(void) 1253 { 1254 int err; 1255 1256 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) { 1257 err = platform_driver_register(ingenic_ipu_driver_ptr); 1258 if (err) 1259 return err; 1260 } 1261 1262 return platform_driver_register(&ingenic_drm_driver); 1263 } 1264 module_init(ingenic_drm_init); 1265 1266 static void ingenic_drm_exit(void) 1267 { 1268 platform_driver_unregister(&ingenic_drm_driver); 1269 1270 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU)) 1271 platform_driver_unregister(ingenic_ipu_driver_ptr); 1272 } 1273 module_exit(ingenic_drm_exit); 1274 1275 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 1276 MODULE_DESCRIPTION("DRM driver for the Ingenic SoCs\n"); 1277 MODULE_LICENSE("GPL v2"); 1278