1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2019 NXP. 4 */ 5 6 #ifndef __DCSS_PRV_H__ 7 #define __DCSS_PRV_H__ 8 9 #include <drm/drm_fourcc.h> 10 #include <drm/drm_plane.h> 11 #include <linux/io.h> 12 #include <video/videomode.h> 13 14 #define SET 0x04 15 #define CLR 0x08 16 #define TGL 0x0C 17 18 #define dcss_writel(v, c) writel((v), (c)) 19 #define dcss_readl(c) readl(c) 20 #define dcss_set(v, c) writel((v), (c) + SET) 21 #define dcss_clr(v, c) writel((v), (c) + CLR) 22 #define dcss_toggle(v, c) writel((v), (c) + TGL) 23 24 static inline void dcss_update(u32 v, u32 m, void __iomem *c) 25 { 26 writel((readl(c) & ~(m)) | (v), (c)); 27 } 28 29 #define DCSS_DBG_REG(reg) {.name = #reg, .ofs = reg} 30 31 enum { 32 DCSS_IMX8MQ = 0, 33 }; 34 35 struct dcss_type_data { 36 const char *name; 37 u32 blkctl_ofs; 38 u32 ctxld_ofs; 39 u32 rdsrc_ofs; 40 u32 wrscl_ofs; 41 u32 dtg_ofs; 42 u32 scaler_ofs; 43 u32 ss_ofs; 44 u32 dpr_ofs; 45 u32 dtrc_ofs; 46 u32 dec400d_ofs; 47 u32 hdr10_ofs; 48 }; 49 50 struct dcss_debug_reg { 51 char *name; 52 u32 ofs; 53 }; 54 55 enum dcss_ctxld_ctx_type { 56 CTX_DB, 57 CTX_SB_HP, /* high-priority */ 58 CTX_SB_LP, /* low-priority */ 59 }; 60 61 struct dcss_dev { 62 struct device *dev; 63 const struct dcss_type_data *devtype; 64 struct device_node *of_port; 65 66 u32 start_addr; 67 68 struct dcss_blkctl *blkctl; 69 struct dcss_ctxld *ctxld; 70 struct dcss_dpr *dpr; 71 struct dcss_dtg *dtg; 72 struct dcss_ss *ss; 73 struct dcss_hdr10 *hdr10; 74 struct dcss_scaler *scaler; 75 struct dcss_dtrc *dtrc; 76 struct dcss_dec400d *dec400d; 77 struct dcss_wrscl *wrscl; 78 struct dcss_rdsrc *rdsrc; 79 80 struct clk *apb_clk; 81 struct clk *axi_clk; 82 struct clk *pix_clk; 83 struct clk *rtrm_clk; 84 struct clk *dtrc_clk; 85 struct clk *pll_src_clk; 86 struct clk *pll_phy_ref_clk; 87 88 bool hdmi_output; 89 90 void (*disable_callback)(void *data); 91 struct completion disable_completion; 92 }; 93 94 struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev); 95 struct drm_device *dcss_drv_dev_to_drm(struct device *dev); 96 struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output); 97 void dcss_dev_destroy(struct dcss_dev *dcss); 98 int dcss_dev_runtime_suspend(struct device *dev); 99 int dcss_dev_runtime_resume(struct device *dev); 100 int dcss_dev_suspend(struct device *dev); 101 int dcss_dev_resume(struct device *dev); 102 void dcss_enable_dtg_and_ss(struct dcss_dev *dcss); 103 void dcss_disable_dtg_and_ss(struct dcss_dev *dcss); 104 105 /* BLKCTL */ 106 int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base); 107 void dcss_blkctl_cfg(struct dcss_blkctl *blkctl); 108 void dcss_blkctl_exit(struct dcss_blkctl *blkctl); 109 110 /* CTXLD */ 111 int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long ctxld_base); 112 void dcss_ctxld_exit(struct dcss_ctxld *ctxld); 113 void dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id, 114 u32 val, u32 reg_idx); 115 int dcss_ctxld_resume(struct dcss_ctxld *dcss_ctxld); 116 int dcss_ctxld_suspend(struct dcss_ctxld *dcss_ctxld); 117 void dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctlxd, u32 ctx_id, u32 val, 118 u32 reg_ofs); 119 void dcss_ctxld_kick(struct dcss_ctxld *ctxld); 120 bool dcss_ctxld_is_flushed(struct dcss_ctxld *ctxld); 121 int dcss_ctxld_enable(struct dcss_ctxld *ctxld); 122 void dcss_ctxld_register_completion(struct dcss_ctxld *ctxld, 123 struct completion *dis_completion); 124 void dcss_ctxld_assert_locked(struct dcss_ctxld *ctxld); 125 126 /* DPR */ 127 int dcss_dpr_init(struct dcss_dev *dcss, unsigned long dpr_base); 128 void dcss_dpr_exit(struct dcss_dpr *dpr); 129 void dcss_dpr_write_sysctrl(struct dcss_dpr *dpr); 130 void dcss_dpr_set_res(struct dcss_dpr *dpr, int ch_num, u32 xres, u32 yres); 131 void dcss_dpr_addr_set(struct dcss_dpr *dpr, int ch_num, u32 luma_base_addr, 132 u32 chroma_base_addr, u16 pitch); 133 void dcss_dpr_enable(struct dcss_dpr *dpr, int ch_num, bool en); 134 void dcss_dpr_format_set(struct dcss_dpr *dpr, int ch_num, 135 const struct drm_format_info *format, u64 modifier); 136 void dcss_dpr_set_rotation(struct dcss_dpr *dpr, int ch_num, u32 rotation); 137 138 /* DTG */ 139 int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base); 140 void dcss_dtg_exit(struct dcss_dtg *dtg); 141 bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg); 142 void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en); 143 void dcss_dtg_vblank_irq_clear(struct dcss_dtg *dtg); 144 void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm); 145 void dcss_dtg_css_set(struct dcss_dtg *dtg); 146 void dcss_dtg_enable(struct dcss_dtg *dtg); 147 void dcss_dtg_shutoff(struct dcss_dtg *dtg); 148 bool dcss_dtg_is_enabled(struct dcss_dtg *dtg); 149 void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en); 150 bool dcss_dtg_global_alpha_changed(struct dcss_dtg *dtg, int ch_num, int alpha); 151 void dcss_dtg_plane_alpha_set(struct dcss_dtg *dtg, int ch_num, 152 const struct drm_format_info *format, int alpha); 153 void dcss_dtg_plane_pos_set(struct dcss_dtg *dtg, int ch_num, 154 int px, int py, int pw, int ph); 155 void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en); 156 157 /* SUBSAM */ 158 int dcss_ss_init(struct dcss_dev *dcss, unsigned long subsam_base); 159 void dcss_ss_exit(struct dcss_ss *ss); 160 void dcss_ss_enable(struct dcss_ss *ss); 161 void dcss_ss_shutoff(struct dcss_ss *ss); 162 void dcss_ss_subsam_set(struct dcss_ss *ss); 163 void dcss_ss_sync_set(struct dcss_ss *ss, struct videomode *vm, 164 bool phsync, bool pvsync); 165 166 /* SCALER */ 167 int dcss_scaler_init(struct dcss_dev *dcss, unsigned long scaler_base); 168 void dcss_scaler_exit(struct dcss_scaler *scl); 169 void dcss_scaler_set_filter(struct dcss_scaler *scl, int ch_num, 170 enum drm_scaling_filter scaling_filter); 171 void dcss_scaler_setup(struct dcss_scaler *scl, int ch_num, 172 const struct drm_format_info *format, 173 int src_xres, int src_yres, int dst_xres, int dst_yres, 174 u32 vrefresh_hz); 175 void dcss_scaler_ch_enable(struct dcss_scaler *scl, int ch_num, bool en); 176 int dcss_scaler_get_min_max_ratios(struct dcss_scaler *scl, int ch_num, 177 int *min, int *max); 178 void dcss_scaler_write_sclctrl(struct dcss_scaler *scl); 179 180 #endif /* __DCSS_PRV_H__ */ 181