1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2018 Intel Corporation 5 */ 6 #include "gt/intel_gpu_commands.h" 7 #include "gt/intel_gt.h" 8 9 #include "gem/i915_gem_internal.h" 10 #include "gem/selftests/igt_gem_utils.h" 11 12 #include "igt_spinner.h" 13 14 int igt_spinner_init(struct igt_spinner *spin, struct intel_gt *gt) 15 { 16 int err; 17 18 memset(spin, 0, sizeof(*spin)); 19 spin->gt = gt; 20 21 spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); 22 if (IS_ERR(spin->hws)) { 23 err = PTR_ERR(spin->hws); 24 goto err; 25 } 26 i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC); 27 28 spin->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); 29 if (IS_ERR(spin->obj)) { 30 err = PTR_ERR(spin->obj); 31 goto err_hws; 32 } 33 34 return 0; 35 36 err_hws: 37 i915_gem_object_put(spin->hws); 38 err: 39 return err; 40 } 41 42 static void *igt_spinner_pin_obj(struct intel_context *ce, 43 struct i915_gem_ww_ctx *ww, 44 struct drm_i915_gem_object *obj, 45 unsigned int mode, struct i915_vma **vma) 46 { 47 void *vaddr; 48 int ret; 49 50 *vma = i915_vma_instance(obj, ce->vm, NULL); 51 if (IS_ERR(*vma)) 52 return ERR_CAST(*vma); 53 54 ret = i915_gem_object_lock(obj, ww); 55 if (ret) 56 return ERR_PTR(ret); 57 58 vaddr = i915_gem_object_pin_map(obj, mode); 59 60 if (!ww) 61 i915_gem_object_unlock(obj); 62 63 if (IS_ERR(vaddr)) 64 return vaddr; 65 66 if (ww) 67 ret = i915_vma_pin_ww(*vma, ww, 0, 0, PIN_USER); 68 else 69 ret = i915_vma_pin(*vma, 0, 0, PIN_USER); 70 71 if (ret) { 72 i915_gem_object_unpin_map(obj); 73 return ERR_PTR(ret); 74 } 75 76 return vaddr; 77 } 78 79 int igt_spinner_pin(struct igt_spinner *spin, 80 struct intel_context *ce, 81 struct i915_gem_ww_ctx *ww) 82 { 83 void *vaddr; 84 85 if (spin->ce && WARN_ON(spin->ce != ce)) 86 return -ENODEV; 87 spin->ce = ce; 88 89 if (!spin->seqno) { 90 vaddr = igt_spinner_pin_obj(ce, ww, spin->hws, I915_MAP_WB, &spin->hws_vma); 91 if (IS_ERR(vaddr)) 92 return PTR_ERR(vaddr); 93 94 spin->seqno = memset(vaddr, 0xff, PAGE_SIZE); 95 } 96 97 if (!spin->batch) { 98 unsigned int mode; 99 100 mode = i915_coherent_map_type(spin->gt->i915, spin->obj, false); 101 vaddr = igt_spinner_pin_obj(ce, ww, spin->obj, mode, &spin->batch_vma); 102 if (IS_ERR(vaddr)) 103 return PTR_ERR(vaddr); 104 105 spin->batch = vaddr; 106 } 107 108 return 0; 109 } 110 111 static unsigned int seqno_offset(u64 fence) 112 { 113 return offset_in_page(sizeof(u32) * fence); 114 } 115 116 static u64 hws_address(const struct i915_vma *hws, 117 const struct i915_request *rq) 118 { 119 return hws->node.start + seqno_offset(rq->fence.context); 120 } 121 122 static int move_to_active(struct i915_vma *vma, 123 struct i915_request *rq, 124 unsigned int flags) 125 { 126 int err; 127 128 i915_vma_lock(vma); 129 err = i915_vma_move_to_active(vma, rq, flags); 130 i915_vma_unlock(vma); 131 132 return err; 133 } 134 135 struct i915_request * 136 igt_spinner_create_request(struct igt_spinner *spin, 137 struct intel_context *ce, 138 u32 arbitration_command) 139 { 140 struct intel_engine_cs *engine = ce->engine; 141 struct i915_request *rq = NULL; 142 struct i915_vma *hws, *vma; 143 unsigned int flags; 144 u32 *batch; 145 int err; 146 147 GEM_BUG_ON(spin->gt != ce->vm->gt); 148 149 if (!intel_engine_can_store_dword(ce->engine)) 150 return ERR_PTR(-ENODEV); 151 152 if (!spin->batch) { 153 err = igt_spinner_pin(spin, ce, NULL); 154 if (err) 155 return ERR_PTR(err); 156 } 157 158 hws = spin->hws_vma; 159 vma = spin->batch_vma; 160 161 rq = intel_context_create_request(ce); 162 if (IS_ERR(rq)) 163 return ERR_CAST(rq); 164 165 err = move_to_active(vma, rq, 0); 166 if (err) 167 goto cancel_rq; 168 169 err = move_to_active(hws, rq, 0); 170 if (err) 171 goto cancel_rq; 172 173 batch = spin->batch; 174 175 if (GRAPHICS_VER(rq->engine->i915) >= 8) { 176 *batch++ = MI_STORE_DWORD_IMM_GEN4; 177 *batch++ = lower_32_bits(hws_address(hws, rq)); 178 *batch++ = upper_32_bits(hws_address(hws, rq)); 179 } else if (GRAPHICS_VER(rq->engine->i915) >= 6) { 180 *batch++ = MI_STORE_DWORD_IMM_GEN4; 181 *batch++ = 0; 182 *batch++ = hws_address(hws, rq); 183 } else if (GRAPHICS_VER(rq->engine->i915) >= 4) { 184 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 185 *batch++ = 0; 186 *batch++ = hws_address(hws, rq); 187 } else { 188 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; 189 *batch++ = hws_address(hws, rq); 190 } 191 *batch++ = rq->fence.seqno; 192 193 *batch++ = arbitration_command; 194 195 if (GRAPHICS_VER(rq->engine->i915) >= 8) 196 *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1; 197 else if (IS_HASWELL(rq->engine->i915)) 198 *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW; 199 else if (GRAPHICS_VER(rq->engine->i915) >= 6) 200 *batch++ = MI_BATCH_BUFFER_START; 201 else 202 *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; 203 *batch++ = lower_32_bits(vma->node.start); 204 *batch++ = upper_32_bits(vma->node.start); 205 206 *batch++ = MI_BATCH_BUFFER_END; /* not reached */ 207 208 intel_gt_chipset_flush(engine->gt); 209 210 if (engine->emit_init_breadcrumb) { 211 err = engine->emit_init_breadcrumb(rq); 212 if (err) 213 goto cancel_rq; 214 } 215 216 flags = 0; 217 if (GRAPHICS_VER(rq->engine->i915) <= 5) 218 flags |= I915_DISPATCH_SECURE; 219 err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); 220 221 cancel_rq: 222 if (err) { 223 i915_request_set_error_once(rq, err); 224 i915_request_add(rq); 225 } 226 return err ? ERR_PTR(err) : rq; 227 } 228 229 static u32 230 hws_seqno(const struct igt_spinner *spin, const struct i915_request *rq) 231 { 232 u32 *seqno = spin->seqno + seqno_offset(rq->fence.context); 233 234 return READ_ONCE(*seqno); 235 } 236 237 void igt_spinner_end(struct igt_spinner *spin) 238 { 239 if (!spin->batch) 240 return; 241 242 *spin->batch = MI_BATCH_BUFFER_END; 243 intel_gt_chipset_flush(spin->gt); 244 } 245 246 void igt_spinner_fini(struct igt_spinner *spin) 247 { 248 igt_spinner_end(spin); 249 250 if (spin->batch) { 251 i915_vma_unpin(spin->batch_vma); 252 i915_gem_object_unpin_map(spin->obj); 253 } 254 i915_gem_object_put(spin->obj); 255 256 if (spin->seqno) { 257 i915_vma_unpin(spin->hws_vma); 258 i915_gem_object_unpin_map(spin->hws); 259 } 260 i915_gem_object_put(spin->hws); 261 } 262 263 bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq) 264 { 265 if (i915_request_is_ready(rq)) 266 intel_engine_flush_submission(rq->engine); 267 268 return !(wait_for_us(i915_seqno_passed(hws_seqno(spin, rq), 269 rq->fence.seqno), 270 100) && 271 wait_for(i915_seqno_passed(hws_seqno(spin, rq), 272 rq->fence.seqno), 273 50)); 274 } 275