1*5adacf19SAlan Previn /* SPDX-License-Identifier: MIT */ 2*5adacf19SAlan Previn /* 3*5adacf19SAlan Previn * Copyright(c) 2023, Intel Corporation. All rights reserved. 4*5adacf19SAlan Previn */ 5*5adacf19SAlan Previn 6*5adacf19SAlan Previn #ifndef __INTEL_PXP_REGS_H__ 7*5adacf19SAlan Previn #define __INTEL_PXP_REGS_H__ 8*5adacf19SAlan Previn 9*5adacf19SAlan Previn #include "i915_reg_defs.h" 10*5adacf19SAlan Previn 11*5adacf19SAlan Previn /* KCR subsystem register base address */ 12*5adacf19SAlan Previn #define GEN12_KCR_BASE 0x32000 13*5adacf19SAlan Previn #define MTL_KCR_BASE 0x386000 14*5adacf19SAlan Previn 15*5adacf19SAlan Previn /* KCR enable/disable control */ 16*5adacf19SAlan Previn #define KCR_INIT(base) _MMIO((base) + 0xf0) 17*5adacf19SAlan Previn 18*5adacf19SAlan Previn /* Setting KCR Init bit is required after system boot */ 19*5adacf19SAlan Previn #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14) 20*5adacf19SAlan Previn 21*5adacf19SAlan Previn /* KCR hwdrm session in play status 0-31 */ 22*5adacf19SAlan Previn #define KCR_SIP(base) _MMIO((base) + 0x260) 23*5adacf19SAlan Previn 24*5adacf19SAlan Previn /* PXP global terminate register for session termination */ 25*5adacf19SAlan Previn #define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8) 26*5adacf19SAlan Previn 27*5adacf19SAlan Previn #endif /* __INTEL_PXP_REGS_H__ */ 28