1 /* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __INTEL_UNCORE_H__ 26 #define __INTEL_UNCORE_H__ 27 28 #include <linux/spinlock.h> 29 #include <linux/notifier.h> 30 #include <linux/hrtimer.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 33 #include "i915_reg.h" 34 35 struct drm_i915_private; 36 struct intel_runtime_pm; 37 struct intel_uncore; 38 39 enum forcewake_domain_id { 40 FW_DOMAIN_ID_RENDER = 0, 41 FW_DOMAIN_ID_BLITTER, 42 FW_DOMAIN_ID_MEDIA, 43 FW_DOMAIN_ID_MEDIA_VDBOX0, 44 FW_DOMAIN_ID_MEDIA_VDBOX1, 45 FW_DOMAIN_ID_MEDIA_VDBOX2, 46 FW_DOMAIN_ID_MEDIA_VDBOX3, 47 FW_DOMAIN_ID_MEDIA_VEBOX0, 48 FW_DOMAIN_ID_MEDIA_VEBOX1, 49 50 FW_DOMAIN_ID_COUNT 51 }; 52 53 enum forcewake_domains { 54 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER), 55 FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER), 56 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA), 57 FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0), 58 FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1), 59 FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2), 60 FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3), 61 FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0), 62 FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1), 63 64 FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1 65 }; 66 67 struct intel_uncore_funcs { 68 void (*force_wake_get)(struct intel_uncore *uncore, 69 enum forcewake_domains domains); 70 void (*force_wake_put)(struct intel_uncore *uncore, 71 enum forcewake_domains domains); 72 73 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore, 74 i915_reg_t r); 75 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore, 76 i915_reg_t r); 77 78 u8 (*mmio_readb)(struct intel_uncore *uncore, 79 i915_reg_t r, bool trace); 80 u16 (*mmio_readw)(struct intel_uncore *uncore, 81 i915_reg_t r, bool trace); 82 u32 (*mmio_readl)(struct intel_uncore *uncore, 83 i915_reg_t r, bool trace); 84 u64 (*mmio_readq)(struct intel_uncore *uncore, 85 i915_reg_t r, bool trace); 86 87 void (*mmio_writeb)(struct intel_uncore *uncore, 88 i915_reg_t r, u8 val, bool trace); 89 void (*mmio_writew)(struct intel_uncore *uncore, 90 i915_reg_t r, u16 val, bool trace); 91 void (*mmio_writel)(struct intel_uncore *uncore, 92 i915_reg_t r, u32 val, bool trace); 93 }; 94 95 struct intel_forcewake_range { 96 u32 start; 97 u32 end; 98 99 enum forcewake_domains domains; 100 }; 101 102 struct intel_uncore { 103 void __iomem *regs; 104 105 struct drm_i915_private *i915; 106 struct intel_runtime_pm *rpm; 107 108 spinlock_t lock; /** lock is also taken in irq contexts. */ 109 110 unsigned int flags; 111 #define UNCORE_HAS_FORCEWAKE BIT(0) 112 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1) 113 #define UNCORE_HAS_DBG_UNCLAIMED BIT(2) 114 #define UNCORE_HAS_FIFO BIT(3) 115 116 const struct intel_forcewake_range *fw_domains_table; 117 unsigned int fw_domains_table_entries; 118 119 struct notifier_block pmic_bus_access_nb; 120 struct intel_uncore_funcs funcs; 121 122 unsigned int fifo_count; 123 124 enum forcewake_domains fw_domains; 125 enum forcewake_domains fw_domains_active; 126 enum forcewake_domains fw_domains_timer; 127 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */ 128 129 struct intel_uncore_forcewake_domain { 130 struct intel_uncore *uncore; 131 enum forcewake_domain_id id; 132 enum forcewake_domains mask; 133 unsigned int wake_count; 134 bool active; 135 struct hrtimer timer; 136 u32 __iomem *reg_set; 137 u32 __iomem *reg_ack; 138 } *fw_domain[FW_DOMAIN_ID_COUNT]; 139 140 struct { 141 unsigned int count; 142 143 int saved_mmio_check; 144 int saved_mmio_debug; 145 } user_forcewake; 146 147 int unclaimed_mmio_check; 148 }; 149 150 /* Iterate over initialised fw domains */ 151 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \ 152 for (tmp__ = (mask__); tmp__ ;) \ 153 for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)]) 154 155 #define for_each_fw_domain(domain__, uncore__, tmp__) \ 156 for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__) 157 158 static inline bool 159 intel_uncore_has_forcewake(const struct intel_uncore *uncore) 160 { 161 return uncore->flags & UNCORE_HAS_FORCEWAKE; 162 } 163 164 static inline bool 165 intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore) 166 { 167 return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED; 168 } 169 170 static inline bool 171 intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore) 172 { 173 return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED; 174 } 175 176 static inline bool 177 intel_uncore_has_fifo(const struct intel_uncore *uncore) 178 { 179 return uncore->flags & UNCORE_HAS_FIFO; 180 } 181 182 void intel_uncore_init_early(struct intel_uncore *uncore, 183 struct drm_i915_private *i915); 184 int intel_uncore_init_mmio(struct intel_uncore *uncore); 185 void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore); 186 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore); 187 bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore); 188 void intel_uncore_fini_mmio(struct intel_uncore *uncore); 189 void intel_uncore_suspend(struct intel_uncore *uncore); 190 void intel_uncore_resume_early(struct intel_uncore *uncore); 191 void intel_uncore_runtime_resume(struct intel_uncore *uncore); 192 193 void assert_forcewakes_inactive(struct intel_uncore *uncore); 194 void assert_forcewakes_active(struct intel_uncore *uncore, 195 enum forcewake_domains fw_domains); 196 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); 197 198 enum forcewake_domains 199 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, 200 i915_reg_t reg, unsigned int op); 201 #define FW_REG_READ (1) 202 #define FW_REG_WRITE (2) 203 204 void intel_uncore_forcewake_get(struct intel_uncore *uncore, 205 enum forcewake_domains domains); 206 void intel_uncore_forcewake_put(struct intel_uncore *uncore, 207 enum forcewake_domains domains); 208 /* Like above but the caller must manage the uncore.lock itself. 209 * Must be used with I915_READ_FW and friends. 210 */ 211 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, 212 enum forcewake_domains domains); 213 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, 214 enum forcewake_domains domains); 215 216 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore); 217 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore); 218 219 int __intel_wait_for_register(struct intel_uncore *uncore, 220 i915_reg_t reg, 221 u32 mask, 222 u32 value, 223 unsigned int fast_timeout_us, 224 unsigned int slow_timeout_ms, 225 u32 *out_value); 226 static inline int 227 intel_wait_for_register(struct intel_uncore *uncore, 228 i915_reg_t reg, 229 u32 mask, 230 u32 value, 231 unsigned int timeout_ms) 232 { 233 return __intel_wait_for_register(uncore, reg, mask, value, 2, 234 timeout_ms, NULL); 235 } 236 237 int __intel_wait_for_register_fw(struct intel_uncore *uncore, 238 i915_reg_t reg, 239 u32 mask, 240 u32 value, 241 unsigned int fast_timeout_us, 242 unsigned int slow_timeout_ms, 243 u32 *out_value); 244 static inline int 245 intel_wait_for_register_fw(struct intel_uncore *uncore, 246 i915_reg_t reg, 247 u32 mask, 248 u32 value, 249 unsigned int timeout_ms) 250 { 251 return __intel_wait_for_register_fw(uncore, reg, mask, value, 252 2, timeout_ms, NULL); 253 } 254 255 /* register access functions */ 256 #define __raw_read(x__, s__) \ 257 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \ 258 i915_reg_t reg) \ 259 { \ 260 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \ 261 } 262 263 #define __raw_write(x__, s__) \ 264 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \ 265 i915_reg_t reg, u##x__ val) \ 266 { \ 267 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \ 268 } 269 __raw_read(8, b) 270 __raw_read(16, w) 271 __raw_read(32, l) 272 __raw_read(64, q) 273 274 __raw_write(8, b) 275 __raw_write(16, w) 276 __raw_write(32, l) 277 __raw_write(64, q) 278 279 #undef __raw_read 280 #undef __raw_write 281 282 #define __uncore_read(name__, x__, s__, trace__) \ 283 static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \ 284 i915_reg_t reg) \ 285 { \ 286 return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \ 287 } 288 289 #define __uncore_write(name__, x__, s__, trace__) \ 290 static inline void intel_uncore_##name__(struct intel_uncore *uncore, \ 291 i915_reg_t reg, u##x__ val) \ 292 { \ 293 uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \ 294 } 295 296 __uncore_read(read8, 8, b, true) 297 __uncore_read(read16, 16, w, true) 298 __uncore_read(read, 32, l, true) 299 __uncore_read(read16_notrace, 16, w, false) 300 __uncore_read(read_notrace, 32, l, false) 301 302 __uncore_write(write8, 8, b, true) 303 __uncore_write(write16, 16, w, true) 304 __uncore_write(write, 32, l, true) 305 __uncore_write(write_notrace, 32, l, false) 306 307 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 308 * will be implemented using 2 32-bit writes in an arbitrary order with 309 * an arbitrary delay between them. This can cause the hardware to 310 * act upon the intermediate value, possibly leading to corruption and 311 * machine death. For this reason we do not support I915_WRITE64, or 312 * uncore->funcs.mmio_writeq. 313 * 314 * When reading a 64-bit value as two 32-bit values, the delay may cause 315 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that 316 * occasionally a 64-bit register does not actually support a full readq 317 * and must be read using two 32-bit reads. 318 * 319 * You have been warned. 320 */ 321 __uncore_read(read64, 64, q, true) 322 323 static inline u64 324 intel_uncore_read64_2x32(struct intel_uncore *uncore, 325 i915_reg_t lower_reg, i915_reg_t upper_reg) 326 { 327 u32 upper, lower, old_upper, loop = 0; 328 upper = intel_uncore_read(uncore, upper_reg); 329 do { 330 old_upper = upper; 331 lower = intel_uncore_read(uncore, lower_reg); 332 upper = intel_uncore_read(uncore, upper_reg); 333 } while (upper != old_upper && loop++ < 2); 334 return (u64)upper << 32 | lower; 335 } 336 337 #define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__)) 338 #define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__)) 339 340 #undef __uncore_read 341 #undef __uncore_write 342 343 /* These are untraced mmio-accessors that are only valid to be used inside 344 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 345 * controlled. 346 * 347 * Think twice, and think again, before using these. 348 * 349 * As an example, these accessors can possibly be used between: 350 * 351 * spin_lock_irq(&uncore->lock); 352 * intel_uncore_forcewake_get__locked(); 353 * 354 * and 355 * 356 * intel_uncore_forcewake_put__locked(); 357 * spin_unlock_irq(&uncore->lock); 358 * 359 * 360 * Note: some registers may not need forcewake held, so 361 * intel_uncore_forcewake_{get,put} can be omitted, see 362 * intel_uncore_forcewake_for_reg(). 363 * 364 * Certain architectures will die if the same cacheline is concurrently accessed 365 * by different clients (e.g. on Ivybridge). Access to registers should 366 * therefore generally be serialised, by either the dev_priv->uncore.lock or 367 * a more localised lock guarding all access to that bank of registers. 368 */ 369 #define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__) 370 #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__) 371 #define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__) 372 #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__)) 373 374 static inline void intel_uncore_rmw(struct intel_uncore *uncore, 375 i915_reg_t reg, u32 clear, u32 set) 376 { 377 u32 val; 378 379 val = intel_uncore_read(uncore, reg); 380 val &= ~clear; 381 val |= set; 382 intel_uncore_write(uncore, reg, val); 383 } 384 385 static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore, 386 i915_reg_t reg, u32 clear, u32 set) 387 { 388 u32 val; 389 390 val = intel_uncore_read_fw(uncore, reg); 391 val &= ~clear; 392 val |= set; 393 intel_uncore_write_fw(uncore, reg, val); 394 } 395 396 #define raw_reg_read(base, reg) \ 397 readl(base + i915_mmio_reg_offset(reg)) 398 #define raw_reg_write(base, reg, value) \ 399 writel(value, base + i915_mmio_reg_offset(reg)) 400 401 #endif /* !__INTEL_UNCORE_H__ */ 402